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Computer Architecture Lab 3

This document provides instructions for a lab assignment on implementing an arithmetic logic unit (ALU) using a FPGA board. Students are asked to: 1. Create a new project in Xilinx ISE called "Alu" and add a Verilog source file called "logic_unit" that implements a 4-bit ALU with inputs a and b, a 3-bit selection line sel, and outputs out, c_out, and z_f. 2. Synthesize and simulate the ALU design using the test bench. 3. Implement the synthesized ALU design on a Spartan 3 FPGA board. The assignment also requires writing a new behavioral model for

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Hasan Iqbal
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94 views

Computer Architecture Lab 3

This document provides instructions for a lab assignment on implementing an arithmetic logic unit (ALU) using a FPGA board. Students are asked to: 1. Create a new project in Xilinx ISE called "Alu" and add a Verilog source file called "logic_unit" that implements a 4-bit ALU with inputs a and b, a 3-bit selection line sel, and outputs out, c_out, and z_f. 2. Synthesize and simulate the ALU design using the test bench. 3. Implement the synthesized ALU design on a Spartan 3 FPGA board. The assignment also requires writing a new behavioral model for

Uploaded by

Hasan Iqbal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Name: _________________ Roll No:__________

Lab: Computer Architecture (8th Term)

LAB # 3
Introduction to Behavioural Modelling
through implementation of Arithmetic Logic Unit (ALU) and its
simulation using Xilinx ISE tools and implementation on FPGA
board.

NOTE: Use the name of new source same as that of verilog modules present in
notepad files.
Procedure:
1. Launch the Xilinx ISE 7.1 software as follows:

Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator

2. Start a new project as follows:

File >> New Project

3. Give the project name as : Alu

4. Select the project location as follows:


C:\CA05\2005_E_205

5. Select the top level module type as : HDL

6. Click Next.
7. In the next window of ‘Select Device and Design Flow for the Project’:
Select the simulator as : ISE simulator
In the Device Family option,
Select Spartan3
In the Device option
Select xc3s200
In the Package option
Select ft256
In the Speed Grade option
Select -5
In the Top Level Module Type option
Select HDL
In the Synthesis Tool option
Select XST(VHDL/Verilog)
In the Simulator option
Select ISE Simulator
In the Generated Simulation Language option
Select Verilog

Then, select Next.

8. In the next window of ‘Create a new source’:


Simply click Next. We shall not use this option for the time
being.
9. In the next window of ‘Add Existing Sources’:
Simply click Next. We shall not use this option for the time
being.
10. In the next window, click Finish.
11. Select Project >> New Source
12. In the ‘New Source’ window:
Select ‘Verilog module’ out of different options available in the
left hand column.
Give the file name as: Any appropriate (e.g. logic_unit )
13. In the next window of ‘Define Verilog Source’:
Simply click Next. We shall not use this option for the time
being.
14. In the next window, click Finish.

15. Use the following Verilog Code:


// ALU Coder
module logic_unit(a ,b ,sel ,out ,c_out ,z_f);
input [3:0] a ,b;
input [2:0] sel;

output reg [3:0]out;


output z_f ,c_out ;

assign z_f = (~out[3] & ~out[2] & ~out[1] & ~out[0]);


assign c_out = ((a[3]&b[3]) | ((a[3] | b[3]) & ~out[3]));

always @ (a or b or sel)

case (sel)
0: out = a + b;
1: out = a - b;
2: out = b + 1;
3: out = a - 1;
4: out = ~a;
5: out = a & b;
6: out = a | b;
7: out = ~a + 1;

endcase

endmodule

Codes of following are available & Present in a notepad file. Just copy from
there and paste.

Points to Ponder:
• Synthesis the ALU.
• See the test bench waveform.
• Implement on FPGA board. (Spartan 3)
ASSIGNMENT (To do in today lab session):

a) To implement an ALU, having two 4 bit inputs with also a 4 bit selection line. The
output should be also 4bit with a single bit carry flag and zero flag.

sel out
4’b0000 Sum the inputs
4’b0001 Subtract b from a
4’b0010 Increment b by 1
4’b0011 Decrement a by 1
4’b0100 Not a
4’b0101 Bitwise and of a & b
4’b0110 Bitwise or of a & b
4’b0111 Two’ complement of a
4’b1000 Barrel Shifter***
4’b1001 Comparator*
4’b1010 Equality**
4’b1011 Multiplication of inputs
4’b1100 Bitwise Nand of two inputs
4’b1101 Tale one’s Complement of ‘b’
4’b1110 Subtract ‘a’ from ‘b’
4’b1111 Bitwise Exclusive OR

*Comparator assigns the greater value to the output


**If the inputs are equal then output is equal to 4’b1111 otherwise 4b’0000.
*** Implement Barrel shifter in such a way that input ‘a’ acts as data and input ‘b’
acts as type and amount.

• You have to write a new code of barrel shifter at behavioural level


without using 16 X 1 Mux.
• You can use it as e.g Shif (a ,b[1:0] ,b[3:2] , out)
//
module Shif (data , amount ,type, out);

input [3:0] data;


input [1:0] amount , type;
output [3:0] out;

// Write Code
endmodule

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