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Computer Architecture Lab 2

This document provides instructions for a lab assignment on implementing carry lookahead adders at the gate level in Verilog and simulating and testing them using Xilinx ISE tools and an FPGA board. The procedures describe creating a project in ISE, adding source files for half adders and 4-bit carry lookahead adders, and synthesizing, simulating and implementing a 4-bit adder on an FPGA board. The assignment asks students to extend this to a 16-bit adder using multiple 4-bit blocks with carry lookahead and ripple carry between blocks, and also using a single 16-bit block with two levels of carry lookahead.

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Hasan Iqbal
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72 views

Computer Architecture Lab 2

This document provides instructions for a lab assignment on implementing carry lookahead adders at the gate level in Verilog and simulating and testing them using Xilinx ISE tools and an FPGA board. The procedures describe creating a project in ISE, adding source files for half adders and 4-bit carry lookahead adders, and synthesizing, simulating and implementing a 4-bit adder on an FPGA board. The assignment asks students to extend this to a 16-bit adder using multiple 4-bit blocks with carry lookahead and ripple carry between blocks, and also using a single 16-bit block with two levels of carry lookahead.

Uploaded by

Hasan Iqbal
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Name:_________________ Roll No:__________

Lab: Computer Architecture (8th Term)

LAB # 2
Introduction to Gate level & Dataflow Modelling
through implementation of Carry Look Ahead at gate level and its
simulation using Xilinx ISE tools and implementation on FPGA
board.

NOTE: Use the name of new source same as that of verilog modules present in
notepad files.
Procedure:
1. Launch the Xilinx ISE 7.1 software as follows:

Start >> Programs >> Xilinx ISE 7.1 >> Project Navigator

2. Start a new project as follows:

File >> New Project

3. Give the project name as : Ripple_Carry

4. Select the project location as follows:


C:\CA05\2005_E_205

5. Select the top level module type as : HDL

6. Click Next.
7. In the next window of ‘Select Device and Design Flow for the Project’:
Select the simulator as : ISE simulator
In the Device Family option,
Select Spartan3
In the Device option
Select xc3s200
In the Package option
Select ft256
In the Speed Grade option
Select -5
In the Top Level Module Type option
Select HDL
In the Synthesis Tool option
Select XST(VHDL/Verilog)
In the Simulator option
Select ISE Simulator
In the Generated Simulation Language option
Select Verilog

Then, select Next.

8. In the next window of ‘Create a new source’:


Simply click Next. We shall not use this option for the time
being.
9. In the next window of ‘Add Existing Sources’:
Simply click Next. We shall not use this option for the time
being.
10. In the next window, click Finish.
11. Select Project >> New Source
12. In the ‘New Source’ window:
Select ‘Verilog module’ out of different options available in the
left hand column.
Give the file name as: Any appropriate (e.g. half_adder )
13. In the next window of ‘Define Verilog Source’:
Simply click Next. We shall not use this option for the time
being.
14. In the next window, click Finish.

15. Use the following Verilog Code:

Codes of following are available & Present in a notepad file. Just copy
from there and paste.

module half_adder (sum, carry, a, b);

input a, b;
output sum, carry;
assign sum = a ^ b;
assign carry = a & b;

endmodule

16. Repeat step 11,12,13 & 14 but save now file name as cla_gen.

17. Use the following Verilog Code:

module cla_gen (p, g, ci, c);

input [3:0] p, g;
input ci;
output [3:0] c;

assign c[0] =
ci;
assign c[1] =
g[0] | (p[0]&c[0]);
assign c[2] =
g[1] | (p[1]&g[0]) | (p[1]&p[0]&c[0]);
assign c[3] =
g[2] | (p[2]&g[1]) | (p[2]&p[1]&g[0]) |
(p[2]&p[1]&p[0]&c[0]);
assign c[4] = g[3] | (p[3]&g[2]) | (p[3]&p[2]&g[1]) |
(p[3]&p[2]&p[1]&c[0]) | (p[3]&p[2]&p[1]&p[0]&c[0]);

endmodule

18. Now copy the following code and see the difference between the synthesis
implementation (RTL) of both these code.

module cla_gen2 (p, g, cin, cout);

input [3:0] p, g;
input cin;
output [4:0] cout;

assign cout[0] = cin;


assign cout[1] = g[0] | (p[0]&cout[0]);
assign cout[2] = g[1] | (p[1]&cout[1]);
assign cout[3] = g[2] | (p[2]&cout[2]);
assign cout[4] = g[3] | (p[3]&cout[3]);

endmodule
19. Repeat Step 17 with file name as four_Bit_add. And use the following code.
module four_bit_add (A, B, C_in, S, C_out);

input [3:0] A, B;
input C_in;
output [3:0] S;
output C_out;
wire [3:0] P, G;
wire [4:0] C;

half_adder HA0 (P[0], G[0], A[0], B[0]);


half_adder HA1 (P[1], G[1], A[1], B[1]);
half_adder HA2 (P[2], G[2], A[2], B[2]);
half_adder HA3 (P[3], G[3], A[3], B[3]);
cla_gen c_g (P, G, C_in, C);
assign S = {P[3]^C[3], P[2]^C[2], P[1]^C[1], P[0]^C[0]};
assign C_out = C[4];
endmodule

Points to Ponder:
• Synthesis the four_bit_add.
• See the test bench waveform.
• Implement on FPGA board. (Spartan 3)
ASSIGNMENT (To do in today lab session):

a) To implement 16 bit adder, using four 4 bits as a block with carry lookahead, and
still use ripple carry between the blocks.

b) To implement 16 bit adder combining 4 blocks of 4-bit carry-lookahead adder as a


super block, we get a 16-bit adder with 2 levels of carry-lookahead logic

The code of four_bit is as follows which has PG and GG additional output to extend
the carry lookahead block to level 2.(also C_out is missing in this new block. )

// four_bit (To be used to improve further delays)


module four_bit (A, B, C_in, S, PG, GG);

input [3:0] A, B;
input C_in;
output [3:0] S;
output PG, GG;
wire [3:0] P, G;
wire [4:0] C;

half_adder HA0 (P[0], G[0], A[0], B[0]);


half_adder HA1 (P[1], G[1], A[1], B[1]);
half_adder HA2 (P[2], G[2], A[2], B[2]);
half_adder HA3 (P[3], G[3], A[3], B[3]);
cla_gen c_g (P, G, C_in, C);
assign PG = P[0] & P[1] & P[2] & P[3];
assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) |(P[3] & P[2] & P[1]
& G[0]);
assign S = {P[3]^C[3], P[2]^C[2], P[1]^C[1], P[0]^C[0]};

endmodule
// end

// Final code
module carry_look(A, B, C_in, Sum, Cout);

input [15:0] A ,B ;
input C_in;
output [15:0] Sum;
output Cout;

// Write the code


endmodule

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