EE5320: Analog IC Design Chaitanya Kumar EE19S062 Dept. of Electrical Engg. IIT Madras Chennai 600036

EE5320: Analog IC Design
Chaitanya Kumar
EE19S062
Dept. of Electrical Engg.
IIT Madras
Chennai 600036
Assignment 4
Question 1.
Designing the differential amplifier:
1. Setting the gds of Mp1,2 and MN1,2.
This is set by the 3 dB bandwidth requirement of the diff. amplifier.
Assuming ⍵z>>⍵p and CL’ is mainly dominated by the load capacitance CL.
2. Setting the gm of MN1,2
3. Setting widths of Mp1,2 and MN1,2

Initially using length twice the minimum length transistor for NMOS and plotting the
various curves Vs current densities.
Choosing Vdsat of 70 mV and for good voltage swing. Here fug is 5 GHz so the parasitics
won’t affect the bandwidth.
So properties of MN1,2:
Current = 2.76 mA
L = 260 nm
W = 709 um
VDSAT = 70.54 mV
gm = 60.469 mS
gDS = 1.03 mS
Now for PMOS using minimum length transistors.
Current in the PMOS is fixed to 2.76 mA. Now for a common mode output of 0.6 mV and
sufficient output swing, the VDSAT of 200 mV.
Current = 2.76 mA
L = 130 nm
W = 166.2 um
VDSAT = 208 mV
gm = 23.72 mS
gDS = 0.655 mS
It turns out that gds of PMOS is sufficiently low. So gDS of NMOS can be increased a bit.
Readjusting the dimensions of NMOS (keeping the current same as 2.76 mA).
Current = 2.76 mA
L = 200 nm
W = 500.2 um
VDSAT = 66.23 mV
gm = 58.05 mS
gDS = 1.4595 mS
Transistor MP1,0 MN1,0
Current 2.76 mA 2.76 mA
Length 130 nm 200 nm
Width 166.2 um 500.2 um

Since the gm requirement was fixed, a higher width of NMOS was chosen to reduce the
current requirement. At the same time, it was made sure that the device is not going in
sub - threshold and the transistor’s parasitics don’t affect the performance of the circuit.
Moreover, if the lower width and higher current option was taken this will increase the
VGS required for the MN1,0 (which is 450 mV right now). This will leave very little voltage
room for the tail current source.
Following points were considered while designing the common mode stage:
1. The gain of the loop shall be around 60dB
2. Bandwidth must be greater than 1 MHz
3. Phase margin shall be 70 degrees
4. Since the compensation capacitor is in parallel with the load capacitance, it will
affect the differential mode bandwidth also. So to minimize it, the ratio of gm of the
second stage to that of the first stage is kept high.
5. To remove systematic offset the current densities of the transistor MN0 and the load
transistors of the first stage (which are NMOS) are kept the same.
6. The RCM shall not affect the gain of the differential amplifier. So, it is kept 10 times the
output resistance of the differential amplifier. So, RCM = 5 KΩ.
CMFB loop’s first stage
Keeping in view the above points, the transistor sizes and currents are:
Transistor MN0 (Tail of Diff amp) MPC1,2 MnC1,2
Current 5.52 mA 8.4 uA 8.4 uA
Length 130 nm 130 nm 260 nm
Width 432 um 8 um 657 nm

As mentioned above in point number 4, the gm of the second stage is required to be
significantly high to reduce the size of miller capacitance required. So, the width of the tail
device (MN0) is kept high.
Pole zero analysis of the CMFB loop

gm1 : transconductance of the input of first stage i.e. MPC1,2
ro1 : Output resistance of first stage ron||rop
C1: Gate capacitance of MN0
gm2 : transconductance of the tail current source transistor of differential amplifier of first stage
i.e. MN0.
ro2 : At point Vx (in the diagram of common mode circuit above). It is the output resistance of
2*MP1,2 in parallel with the resistance looking into the drain of MN1,2.
C2: twice the load capacitance (10 pF).
Cgg: Gate capacitance of the input of first stage i.e. MPC1,2.
gm1 = 180.5 uS
ro1 = 132.8 kΩ
C1 = 781.5 fF
gm2 = 107.5 mS
r02 =
= 610.65 Ω.
C2 = 10 pF
Cgg = 11.91 fF
The additional poles and zeros are due to the L, C in the network.
Uncompensated loop gain: DC gain is 63.3 dB and phase margin is 4.39°.

c) Compensated loop gain. Compensation capacitor used : 270 fF (135 fF on each side)
Phase margin of 70° achieved. CC = 270 fF. FUGB = 90.8 MHz. DC Gain = 63.3 dB
d) Loop gain plotted with L, C combination:
The phase is starting from -180° so, the phase margin is 360° - 290° = 70°. The Distortion seen
initially is due the the additional poles and zeros due to L, C
Circuit inserted in the loop to get the loop gain.

e) Characteristics of the differential amplifier
DC Gain = 26 V/V, F-3dB = 73.6 MHz, FUGB = 1.8 GHz
Schematic of complete circuit.

Question 2.
F-3dB = 51.04 MHz and DC Gain = 20.44 V/V
b) NTFs of various noise sources:
i) From MP1, MP2
ii) For MN1, MN2
iii) From the resistances Rs
Input referred noise
Output noise
Here M4, M3 are MP1, MP2.
R6 , R7 are Rs
M0, M1 are MN1, MN2
And R1, R0 are Rcm
fn : Flicker noise of transistors
id: thermal noise of transistors
Rn: thermal noise of resistors
Question 3:
F-3dB = 52.45 MHz and DC Gain = 20.65 V/V
b) Neglecting the output resistances of the transistors MN01, MN02:

The NTFs of the noise sources from previously present devices wouldn't change.
Input referred noise
Output noise
Here M4, M3 are MP1, MP2.
R6 , R7 are Rs
M0, M1 are MN1, MN2
M6, M11 are MN01, MN02
And R1, R0 are Rcm
fn : Flicker noise of transistors
id: thermal noise of transistors
Rn: thermal noise of Resistors

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EE5320: Analog IC Design

2. Setting the gm of MN1,2

3. Setting widths of Mp1,2 and MN1,2

Transistor MP1,0 MN1,0

Current 2.76 mA 2.76 mA

Length 130 nm 200 nm

Width 166.2 um 500.2 um

Current 5.52 mA 8.4 uA 8.4 uA

Length 130 nm 130 nm 260 nm

Width 432 um 8 um 657 nm

Pole zero analysis of the CMFB loop

Uncompensated loop gain: DC gain is 63.3 dB and phase margin is 4.39°.

d) Loop gain plotted with L, C combination:

Circuit inserted in the loop to get the loop gain.

DC Gain = 26 V/V, F-3dB = 73.6 MHz, FUGB = 1.8 GHz

Schematic of complete circuit.

b) Neglecting the output resistances of the transistors MN01, MN02:

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