May 1997

ML2281, ML2282*,
ML2284#, ML2288#
Serial I/O 8-Bit A/D Converters with
Multiplexer Options
GENERAL DESCRIPTION FEATURES
The ML2281 family are 8-bit successive approximation ■ Conversion time: 6µs
A/D converters with serial I/O and configurable input ■ Total unadjusted error: ±1/2LSB or ±1LSB
multiplexers with up to 8 input channels.
■ Sample-and-hold: 375ns acquisition
All errors of the sample-and-hold, incorporated on the ■ 2, 4 or 8-input multiplexer options
ML2281 family are accounted for in the analog-to-digital
■ 0 to 5V analog input range with single 5V
converters accuracy specification. power supply
The voltage reference can be externally set to any value ■ Operates ratiometrically or with up to 5V
between GND and VCC, thus allowing a full conversion voltage reference
over a relatively small voltage span if desired. ■ No zero or full-scale adjust required
■ ML2281 capable of digitizing a 5V, 40kHz sine wave
The ML2281 family is an enhanced double polysilicon
CMOS pin compatible second source for the ADC0831, ■ Low power: 12.5mW MAX
ADC0832, ADC0834, and ADC0838 A/D converters. The ■ Superior pin compatible replacement for ADC0831,
ML2281 series enhancements are faster conversion time, ADC0832, ADC0834, and ADC0838
true sample-and-hold function, superior power supply
rejection, improved AC common mode rejection, faster ■ Analog input protection: 25mA (min) per input
digital timing, and lower power dissipation. All parameters ■ Now in 8-Pin SOIC Package (ML2281, ML2282)
are guaranteed over temperature with a power supply (* Indicates Part is Obsolete)
voltage of 5V ±10%. (# Indicates Part is End Of Life as Of July 1, 2000)

BLOCK DIAGRAM ML2288 (8-Channel SE or 4-Channel Diff Multiplexer)

ML2284 (4-Channel SE or 2-Channel Diff Multiplexer)
ML2281 ML2284 (2-Channel SE or 1-Channel Diff Multiplexer)

CS
CONTROL
AND INPUT DI
CLK
TIMING SHIFT-REGISTER

SARS
CONTROL
DO 4-BIT CLK
OUTPUT AND
SHIFT-REGISTER TIMING CS

A/D WITH SAMPLE & HOLD FUNCTION DO

VIN+ OUTPUT
Σ
+
+ SUCCESSIVE SHIFT-REGISTER
COMP APPROXIMATION
– CH0
– REGISTER SE
8pF CH1
(ML2288 SHOWN)

CH2
MULTIPLEXER

VREF
VIN– CH3 A/D DGND
CH4 CONVERTER
WITH
D/A CH5 SAMPLE & HOLD
8pF CONVERTER FUNCTION
CH6
CH7 SHUNT
REGULATOR

VCC GND COMMON AGND VREF VCC V+

1
ML2281, ML2282, ML2284, ML2288
PIN CONFIGURATION
ML2281 ML2282
Single Differential Input 2-Channel MUX
8-Pin DIP 8-Pin DIP
CS 1 8 VCC CS 1 8 VCC (VREF)
VIN+ 2 7 CLK CH0 2 7 CLK
VIN– 3 6 DO CH1 3 6 DO
GND 4 5 VREF GND 4 5 DI

TOP VIEW TOP VIEW

ML2281 ML2282
8-Pin SOIC 8-Pin SOIC

CS 1 8 VCC CS 1 8 VCC (VREF)

VIN+ 2 7 CLK CH0 2 7 CLK
VIN– 3 6 DO CH1 3 6 DO
GND 4 5 VREF GND 4 5 DI
TOP VIEW TOP VIEW

ML2284 ML2284
14-Pin SOIC 4-Channel MUX
14-Pin DIP

V+ 1 14 VCC V+ 1 14 VCC
CS 2 13 DI
CS 2 13 DI
CH0 3 12 CLK
CH1 4 11 SARS CH0 3 12 CLK
CH2 5 10 DO CH1 4 11 SARS
CH3 6 9 VREF
CH2 5 10 DO
DGND 7 8 AGND
CH3 6 9 VREF
TOP VIEW
DGND 7 8 AGND

TOP VIEW
ML2288
8-Channel MUX ML2288
20-Pin PCC 8-Channel MUX
20-Pin DIP
CH2

CH1

CH0

VCC

V+

CH0 1 20 VCC

3 2 1 20 19 CH1 2 19 V+
CH3 4 18 CS CH2 3 18 CS

CH4 5 CH3 4 17 DI
17 DI
CH4 5 16 CLK
CH5 6 16 CLK
CH5 6 15 SARS
CH6 7 15 SARS CH6 7 14 DO
CH7 8 14 DO CH7 8 13 SE
9 10 11 12 13 COM 9 12 VREF
DGND 10 11 AGND
COM

DGND

AGND

VREF

SE

TOP VIEW

TOP VIEW

2
 ML2281, ML2282, ML2284, ML2288
PIN DESCRIPTION
NAME FUNCTION NAME FUNCTION
VCC Positive supply. 5V ± 10% DO Data out. Digital output which contains result
of A/D conversion. The serial data is clocked
DGND Digital ground. 0 volts. All digital inputs and
out on falling edges of CLK.
outputs are referenced to this point.
SARS Successive approximation register status.
AGND Analog ground. The negative reference voltage Digital output which indicates that a
for A/D converter.
conversion is in progress. When SARS goes
CH0-7, Analog inputs. Digitally selected to be single to 1, the sampling window is closed and
VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential conversion begins. When SARS goes to 0,
input. Analog range = GND - VIN - VCC. conversion is completed. When CS = 1, SARS
is in high impedance state.
COM Common reference point for analog inputs.
A/D conversion is performed on voltage CLK Clock. Digital input which clocks data in on
difference between analog input and this DI on rising edges and out on DO on falling
common reference point if single-end edges. Also used to generate clocks for A/D
conversion is specified. conversion.
VREF Reference. The positive reference voltage for DI Data input. Digital input which contains serial
A/D converter. data to program the MUX and channel
assignments.
SE Shift enable. Input controls whether LSB first
bit stream is shifted out on serial output DO. CS Chip select. Selects the chip for multiplexer
If SE = 1, MSB first is shifted out only. If SE = 0, and channel assignment and A/D conversion.
an MSB first bit stream is shifted out, then a When CS = 1, all digital outputs are in high
second bit stream with LSB first is shifted out impedance state. When CS = 0, normal A./D
after end of conversion. conversion takes place.
V+ Input to the Shunt Regulator.

3
ML2281, ML2282, ML2284, ML2288
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which Lead Temperature (Soldering 10 sec.)
the device could be permanently damaged. Absolute Dual-In-Line Package (Molded) .......................... 260°C
maximum ratings are stress ratings only and functional Dual-In-Line Package (Ceramic) ......................... 300°C
device operation is not implied. Molded Chip Carrier Package
Vapor Phase (60 sec.) ..................................... 215°C
Current into V+ ...................................................... 15mA Infrared (15 sec.) ............................................. 220°C
Supply Voltage, VCC ................................................. 6.5V
Voltage OPERATING CONDITIONS
Logic Inputs ........................................... –7 to VCC +7V
Analog Inputs ................................ –0.3V to VCC +0.3V Supply Voltage, VCC ............................ 4.5VDC to 6.3VDC
Input Current per Pin (Note 1) .............................. ±25mA Temperature Range (Note 2) ................. T MIN - TA - TMAX
Storage Temperature ................................ –65°C to 150°C ML2281/2/4/8 BIX .................................. –40°C to 85°C
Package Dissipation ML2281/2/4/8 CIX
at TA = 25°C (Board Mount) ............................. 800mW ML2281/2/4/8 BCX .................................... 0°C to 70°C
ML2281/2/4/8 CCX

ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = TMIN to TMAX, VCC = VREF = 5V ±10%, and fCLK = 1.333MHz.
ML228XB ML228XC
TYP TYP
SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX MIN NOTE 3 MAX UNITS
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted VREF = VCC (Notes 4, 6) ±1/2 ±1 LSB
Error
Reference Input (Notes 4, 7) 10 15 20 10 15 20 kW
Resistance
Common-Mode (Notes 4, 8) GND VCC GND VCC V
Input Range –0.05 +0.05 –0.05 +0.05
DC Common-Mode Common mode voltage ±1/16 ±1/4 ±1/16 ±1/4 LSB
Error voltage GND to VCC/2
(Note 5)
AC Common-Mode Common mode voltage ±1/4 ±1/4 LSB
Error GND to VCC/2,
0 to 50kHz (Note 5)
DC Power Supply VCC = 5V ±10% ±1/32 ±1/4 ±1/32 ±1/4 LSB
Sensitivity VREF - VCC +0.1V
(Note 5)
AC Power Supply 100mVP-P, 25kHz sine ±1/4 ±1/4 LSB
Sensitivity on VCC (Note 5)
Change in Zero 15mA into V+ ±1/2 ±1/2 LSB
Error from VCC=5V VCC = N.C. VREF = 5V
to Internal Zener (Note 5)
Operation
VZ Internal Diode 15mA into V+ 6.9 6.9 V
Regulated Break-
down (at V+)
V+ Input Resistance (Note 4) 20 35 20 35 kW

4
 ML2281, ML2282, ML2284, ML2288
ELECTRICAL CHARACTERISTICS (Continued)
ML228XB ML228XC
TYP TYP
SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX MIN NOTE 3 MAX UNITS
CONVERTER AND MULTIPLEXER CHARACTERISTICS (CONTINUED)
IOFF Off Channel On channel = VCC –1 –1 µA
Leakage Current Off channel = 0V
(Notes 4, 9)
On channel = 0V +1 +1 µA
Off channel = VCC
(Notes 4, 9)
ION On Channel On channel = 0V –1 –1 µA
Leakage Current Off channel = VCC
(Notes 4, 9)
On channel = VCC +1 +1 µA
Off channel = 0V
(Notes 4, 9)
DIGITAL AND DC CHARACTERISTICS
VIN(1) Logical “1” (Note 4) 2.0 2.0 V
Input Voltage
VIN(0) Logical “0” (Note 4) 0.8 0.8 V
Input Voltage
IIN(1) Logical “1” Input VIN = VCC (Note 4) 1 1 µA
Current
IIN(0) Logical “0” Input VIN = 0V (Note 4) –1 –1 µA
Current
VOUT(1) Logical “1” IOUT = –2mA (Note 4) 4.0 4.0 V
Output Voltage
VOUT(0) Logical “0” IOUT = 2mA (Note 4) 0.4 0.4 V
Output Voltage
IOUT HI-Z Output VOUT = 0V (Note 4) –1 –1 µA
Current VOUT = VCC 1 1 µA
ISOURCE Output Source VOUT = 0V (Note 4) –6.5 –6.5 mA
Current
ISINK Output Sink Current VOUT = VCC (Note 4) 8.0 8.0 mA
ICC Supply Current ML2281, ML2284 1.3 2.5 1.3 2.5 mA
ML2288 (Note 4)
ML2282 Includes ladder 1.8 3.5 1.8 3.5 mA
Current (Note 4)

5
ML2281, ML2282, ML2284, ML2288
ELECTRICAL CHARACTERISTICS (Continued)
TYP LIMIT
SYMBOL PARAMETER CONDITIONS MIN NOTE 3 MAX UNITS
AC ELECTRICAL CHARACTERISTICS
fCLK Clock Frequency (Note 4) 10 1.333 kHz
tACQ Sample-and-Hold Acquisition 1/2 1/fCLK
tC Conversion Time Not including MUX adddressing time 8 1/fCLK
SNR Signal to Noise Ratio VIN = 40kHz, 5V sine. fCLK = 1.333MHz 47 dB
ML2281 (fSAMPLING » 120kHz). Noise is sum of all
nonfundamental components up to 1/2
of fSAMPLING (Note 11)
THD Total Harmonic Distortion VIN = 40kHz, 5V sine. fCLK = 1.333MHz –60 dB
ML2281 (fSAMPLING » 120kHz). THD is sum of 2,
3, 4, 5 harmonics relative to fundamental
(Note 11)
IMD Intermodulation Distortion VIN = fA + fB. fA = 40kHz, 2.5V sine. –60 dB
ML2281 fB = 39.8kHz, 2.5V Sine, fCLK = 1.333MHz
(fSAMPLING » 120kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental (Note 11)
Clock Duty Cycle (Notes 4, 10) 40 60 %
tSET-UP CS Falling Edge or Data Input (Note 4) 130 ns
Valid to CLK Rising Edge
tHOLD Data Input Valid after (Note 4) 80 ns
CLK Rising Edge
tPD1, CLK Falling Edge to Output CL = 100pF (Note 4 & 12)
tPD0 Data Valid Data MSB first 90 200 ns
Data LSB first 50 110 ns
t1H, Rising Edge of CS to Data CL = 10pF, RL = 10k (see high impedance 40 90 ns
t0H Output and SARS Hi-Z test circuits) (Note 5)
CL = 100pF, RL = 2k (Note 4) 80 160 ns
CIN Capacitance of Logic Input 5 pF
COUT Capacitance of Logic Outputs 5 pF

Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA
or less.
Note 2: 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% production tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7: Cannot be tested for ML2282.
Note 8: For VIN– ³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
analog input voltages one diode drop below ground or one diode drop greater than the VCC supply. Be careful, during testing at low VCC levels (4.5V), as high level
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog V IN or VREF does not exceed the supply voltage by more than 50mV, the output code will be
correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950VDC over temperature variations, initial
tolerance and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the
minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be V IN = 34kHz, 5V sine (fSAMPLING » 102kHz); ML2284 VIN = 32kHz, 5V sine
(fSAMPLING » 95kHz); ML2288 VIN = 30kHz, 5V sine (fSAMPLING » 89kHz).
Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
comparator response time.

6
 ML2281, ML2282, ML2284, ML2288
t1H t1H

tr
VCC
DATA 90%
OUTPUT CS 50%
RL GND 10%
CL
t1H
VOH
DO AND 90%
SARS OUTPUTS
GND

t0H t0H

VCC tr
VCC
90%
RL CS 50%
GND 10%
DATA
OUTPUT t0H
CL VCC
DO AND
SARS OUTPUTS
VOL 10%

Figure 1. High Impedance Test Circuits and Waveforms

Data Input Timing Data Output Timing

CLK CLK

tPD0, tPD1 tPD0, tPD1

tSET-UP
DATA
CS OUT (DO)
tSET-UP
tSET-UP
tHOLD tHOLD
DATA
IN (DI) SE

ML2281 Start Conversion Timing

CLK

tSET-UP

CS
START CONVERSION

DO

BIT 7 BIT 6
(MSB)

Figure 2. Timing Diagrams

7
 ML2281, ML2282, ML2284, ML2288
ML2281 Timing

1 2 3 4 5 6 7 8 9 10 11
CLOCK (CLK)

tSET-UP

CHIP SELECT (CS)

tC

DATA OUT (DO) *

HI-Z HI-Z
7 6 5 4 3 2 1 0
SAMPLE & HOLD (MSB) (LSB)
ACQUISITION (tACQ)
*LSB FIRST OUTPUT NOT AVAILABLE ON ML2281

ML2282 Timing

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
CLOCK (CLK)

tSET-UP OUTPUT DATA

CHIP SELECT (CS) ADDRESS MUX

START ODD/
BIT SIGN
DATA IN (DI) DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)

SGL/DIF MSB FIRST DATA LSB FIRST DATA

DATA OUT (DO)

HI-Z HI-Z
7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
SAMPLE & HOLD
ACQUISITION (tACQ) (MSB) (LSB) (MSB)

ML2284 Timing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

CLOCK (CLK)

tSET-UP OUTPUT DATA

CHIP SELECT (CS) ADDRESS MUX

START
BIT ODD/SIGN

DATA IN (DI) DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)

SGL/DIF SELECT A/D CONVERSION IN PROCESS

BIT 1
SAR STATUS (SARS)
HI-Z HI-Z
MSB FIRST DATA LSB FIRST DATA

DATA OUT (DO)

HI-Z HI-Z

SAMPLE & HOLD 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7

ACQUISITION (tACQ) (MSB) (LSB) (MSB)

Figure 2. Timing Diagrams (Continued)

8
 ML2281, ML2282, ML2284, ML2288

ML2288 Timing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CLOCK (CLK)

tSET-UP OUTPUT DATA

CHIP SELECT (CS) ADDRESS MUX

START ODD/ SELECT

BIT SIGN BIT 0
DATA IN (DI) DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
SGL/DIF SELECT A/D CONVERSION IN PROCESS
BIT 1
SAR STATUS (SARS) HI-Z HI-Z

MSB FIRST DATA LSB FIRST DATA

SE = “0”
DATA OUT (DO) HI-Z HI-Z
 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
(MSB) (LSB) (MSB)
 SE tSET-UP

USING SE 
TO CONTROL  MSB FIRST DATA DATA HELD LSB FIRST DATA
LSB FIRST

OUTPUT DO

HI-Z HI-Z
SAMPLE & HOLD 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7
ACQUISITION (tACQ) (MSB) (LSB) (MSB)

Figure 2. Timing Diagrams (Continued)

1.0
VCC = 5V
VREF = 5V

0.75
LINEARITY ERROR (LSB)

0.5
125 C

–55 C

0.25
25 C

0
0 0.01 0.1 1
CLOCK FREQUENCY (MHz)

Figure 3. Linearity Error vs fCLK

9
ML2281, ML2282, ML2284, ML2288
1 1
VCC = 5V
VCC = 5V VIN = 0V
fCLK = 1.333MHz fCLK = 1.333MHz
TA = 25 C
0.75 0.75
LINEARITY ERROR (LSB)

OFFSET ERROR (LSB)

0.5 0.5
125 C

–55 C 25 C
0.25 0.25

0 0
0 1 2 3 4 5 0 1 2 3 4 5
VREF (VDC) VREF (VDC)

Figure 4. Linearity Error vs VREF Voltage Figure 5. Unadjusted Offset Error vs VREF Voltage

10
 ML2281, ML2282, ML2284, ML2288

17
DI*
18
CS

R R R R R D
5-BIT SHIFT-REGISTER
ODD/ CS
START SGL/DIF SIGN SELECT 1 SELECT 0 C

START

16
CLK 13
VCC MUX SE*
ADDRESS NOTE 1 NOTE 1 CS
SARS*
1 + 15
CH0* Σ TD CS
2 – TIME C R
CH1* DELAY
3 Q D
CH2 DSTART 2

4 D Q
CH3
ANALOG +
5 MUX DSTART 1
CH4* – C R CS
(EQUIVALENT)
DEOC
6 D Q
CH5* C

7 CS
CH6* C R CS
CS
8
CH7* C
CS 14
9 R Q
COM* DO
COMP EOC D
B7
C R R C
12 B6
VREF
B5
VCC TO INTERNAL R SAR 9-BIT
B4
20 CIRCUITRY LOGIC SHIFT
LADDER B3
INPUT V AND REGISTER
CC AND
V+* 13 LATCH B2
TO DECODER
16 B1
DGND* 7V SHUNT INTERNAL
17
REGULATOR 18 CIRCUITS B0

COMP EOC

INPUT PROTECTION—ALL LOGIC INPUTS

AGND*

LSB FIRST

MSB FIRST

PARALLEL XFR
TO SHIFT REGISTER

*SOME OF THESE FUNCTIONS/PINS ARE NOT AVAILABLE WITH OTHER OPTIONS.

NOTE 1: FOR THE ML2284 DI IS INPUT DIRECTLY TO THE D INPUT OF SELECT 1. SELECT 0 IS FORCED TO A “1”. FOR THE ML2282, DI IS INPUT DIRECTLY TO THE D
INPUT OF ODD/SIGN. SELECT 0 IS FORCED TO A “1” AND SELECT 1 IS FORCED TO A “0”.

Figure 6. ML2288 Functional Block Diagram

11
ML2281, ML2282, ML2284, ML2288
FUNCTIONAL DESCRIPTION SINGLE-ENDED MUX MODE

MUX ADDRESS ANALOG SINGLE-ENDED CHANNEL#

MULTIPLEXER ADDRESSING SELECT
SGL/ ODD/
The design of these converters utilizes a sample data DIF SIGN 1 0 0 1 2 3 4 5 6 7 COM
comparator structure which provides for a differential
analog input to be converted by a successive 1 0 0 0 + –
approximation routine. 1 0 0 1 + –
1 0 1 0 + –
The actual voltage converted is always the difference 1 0 1 1 + –
between an assigned “+” input terminal and a “–” input
terminal. The polarity of each input terminal of the pair 1 1 0 0 + –
being converted indicates which line the converter expects 1 1 0 1 + –
to be the most positive. If the assigned “+” input is less than 1 1 1 0 + –
the “–” input, the converter responds with an all zeros
1 1 1 1 + –
output code.

A unique input multiplexing scheme has been utilized DIFFERENTIAL MUX MODE
to provide multiple analog channels with software MUX ADDRESS ANALOG DIFFERENTIAL
configurable single ended, differential, or pseudo
CHANNEL-PAIR#
differential options. The pseudo differential option will
convert the difference between the voltage at any analog SELECT 0 1 2 3
SGL/ ODD/
input and a common terminal. One converter package DIF SIGN 1 0 0 1 2 3 4 5 6 7
can now accommodate ground referenced inputs and
0 0 0 0 + –
true differential inputs as well as signals with some
arbitrary reference voltage. 0 0 0 1 + –
0 0 1 0 + –
A particular input configuration is assigned during the MUX 0 0 1 1 + –
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be 0 1 0 0 – +
enabled and whether this input is single ended or 0 1 0 1 – +
differential. In the differential case, it also assigns the 0 1 1 0 – +
polarity of the analog channels. Differential inputs are
0 1 1 1 – +
restricted to adjacent channel pairs. For example, channel 0
and channel 1 may be selected as a different pair but Table 1. ML2288 MUX Addressing 8 Single-Ended
channel 0 or channel 1 cannot act differentially with any or 4 Differential Channels
other channel. In addition to selecting the differential mode,
the sign may also be selected. Channel 0 may be selected as SINGLE-ENDED MUX MODE
the positive input and channel 1 as the negative input or
vice versa. This programmability is illustrated by the MUX MUX ADDRESS CHANNEL#
addressing codes shown in Tables 1, 2, and 3. SELECT
SGL/ ODD/
The MUX address is shifted into the converter via the DI DIF SIGN 1 0 1 2 3
input. Since the ML2281 contains only one differential 1 0 0 +
input channel with a fixed polarity assignment, it does 1 0 1 +
not require addressing. 1 1 0 +
The common input line on the ML2288 can be used as a 1 1 1 +
pseudo differential input. In this mode, the voltage on the COM is internally tied to AGND

COM pin is treated as the “–” input for any of the other
input channels. This voltage does not have to be analog DIFFERENTIAL MUX MODE
ground; it can be any reference potential which is common
MUX ADDRESS CHANNEL#
to all of the inputs. This feature is most useful in single
supply applications where the analog circuitry may be SELECT
SGL/ ODD/
biased at a potential other than ground and the output DIF SIGN 1 0 1 2 3
signals are all referred to this potential.
0 0 0 + –
Since the input configuration is under software control, it 0 0 1 + –
can be modified, as required, at each conversion. A channel 0 1 0 – +
can be treated as a single-ended, ground referenced input 0 1 1 – +
for one conversion; then it can be reconfigured as part of a
differential channel for another conversion. Figure 7 Table 2. ML2284 MUX Addressing 4 Single-Ended
illustrates these different input modes. or 2 Differential Channel

12
 ML2281, ML2282, ML2284, ML2288
SINGLE-ENDED MUX MODE DIGITAL INTERFACE
MUX ADDRESS CHANNEL# The block diagram and timing diagrams in Figures 2-5
illustrate how a conversion sequence is performed.
SGL/DIF ODD/SIGN 0 1
1 0 + A conversion is initiated when CS is pulsed low. This line
must me held low for the entire conversion. The converter is
1 1 + now waiting for a start bit and its MUX assignment word.

DIFFERENTIAL MUX MODE A clock is applied to the CLK input. On each rising edge
of the clock, the data on DI is clocked into the MUX
MUX ADDRESS CHANNEL#
address shift register. The start bit is the first logic “1” that
SGL/DIF ODD/SIGN 0 1 appears on the DI input (all leading edge zeros are
0 0 + – ignored). After the start bit, the device clocks in the next 2
to 4 bits for the MUX assignment word.
0 1 – +
When the start bit has been shifted into the start location
Table 3. ML2282 MUX Addressing 2 Single-Ended
of the MUX register, the input channel has been assigned
or 1 Differential Channel
and a conversion is about to begin. An interval of 1/2
clock period is used for sample & hold settling through the
selected MUX channels. The SAR status output goes high
8 Single-Ended 8 Pseudo-Differential at this time to signal that a conversion is now in progress
and the DI input is ignored.
0 + 0 +

1 + 1 +
The DO output comes out of High impedance and
provides a leading zero for this one clock period.
2 + 2 +

3 + 3 + When the conversion begins, the output of the

4 + 4 + comparator, which indicates whether the analog input is
greater than or less than each successive voltage from the
5 + 5 +
internal DAC, appears at the DO output on each falling
6 + 6 + edge of the clock. This data is the result of the conversion
7 + 7 + being shifted out (with MSB coming first) and can be read
by external logic or µP immediately.
COM (–) COM (–)
+
VBIAS After 8 clock periods, the conversion is completed. The SAR
status line returns low to indicate this 1/2 clock cycle later.

The serial data is always shifted out MSB first during the
conversion. After the conversion has been completed, the
data can be shifted out a second time with LSB first,
depending on level of SE input. For the case of ML2288, if
4 Differential Mixed Mode SE = 1, the data is shifted out MSB first during the
conversion only. If SE is brought low before the end of
+ conversion (which is signalled by the high to low transition
+ (–) 0, 1
0, 1 – of SARS), the data is shifted out again immediately after the
– (+)
–
end of conversion; this time LSB first. If SE is brought low
+ (–) 2, 3 after end of conversion, the LSB first data is shifted out on
2, 3 +
– (+) falling edges of clock after SE goes low. For ML2282 and
4 + 2284, SE is internally tied low, so data is shifted out MSB
+ (–)
4, 5 5 + first, then shifted out a second time LSB first at end of
– (+) conversion. For ML2281, SE is internally tied high, so data is
6 +
+ (–) shifted out only once MSB first.
6, 7 7 +
– (+)
COM (–) All internal registers are cleared when the CS input is
+ high. If another conversion is desired, CS must make a
VBIAS
high to low transition followed by address information.

The DI input and DO output can be tied together and

controlled through a bidirectional µP I/O bit with one
Figure 7. Analog Input Multiplexer Functional connection. This is possible because the DI input is only
Options for ML2288 latched in during the MUX addressing interval while the
DO output is still in the high impedance state.

13
ML2281, ML2282, ML2284, ML2288
REFERENCE The signal at the analog input is sampled during the interval
when the sampling switch is closed prior to conversion
The voltage applied to the reference input to these
start. The sampling window (S/H acquisition time) is 1/2
converters defines the voltage span of the analog input
CLK period wide and occurs 1/2 CLK period before DO
(the difference between VIN MAX and VIN MIN) over which
goes from high impedance to active low state. When the
the 256 possible output codes apply. The devices can be
sampling switch closes at the start of the S/H acquisition
used in either ratiometric applications or in systems
time, 8pF of capacitance is thrown onto the analog input.
requiring absolute accuracy. The reference pin must be
1/2 CLK period later, the sampling switch is opened and the
connected
signal present at the analog input is stored. Any error on the
to a voltage source capable of driving the reference input
analog input at the end of the S/H acquisition time will
resistance, typically 10k. This pin is the top of a resistor
cause additional conversion error. Care should be taken to
divider string used for the successive approximation
allow adequate charging or settling time from the source.
conversion.
If more charging or settling time is needed to reduce these
analog input errors, a longer CLK period can be used.
In a ratiometric system, the analog input voltage is
proportional to the voltage used for the A/D reference.
The ML2281X family has improved latchup immunity.
This voltage is typically the system power supply, so the
Each analog input has dual diodes to the supply rails, and
VREF pin can be tied to VCC. This technique relaxes the
a minimum of ±25mA (±100mA typically) can be injected
stability requirements of the system reference as the analog
into each analog input without causing latchup.
input and A/D reference move together maintaining the
same output code for a given input condition.
DYNAMIC PERFORMANCE
For absolute accuracy, where the analog input varies
between specific voltage limits, the reference pin can be Signal-to-Noise-Ratio
biased with a time and temperature stable voltage source.
Signal-to-noise ration (SNR) is the measured signal-to-noise
at the output of the converter. The signal is the RMS
The maximum value of the reference is limited to the VCC
magnitude of the fundamental. Noise is the RMS sum of all
supply voltage. The minimum value, however, can be quire
the nonfundamental signals up to half the sampling
small to allow direct conversion of inputs with less than 5V
frequency. SNR is dependent on the number of quantization
of voltage span. Particular care must be taken with regard to
levels used in the digitization process; the more levels, the
noise pickup, circuit layout and system error voltage sources
smaller the quantization noise. The theoretical SNR for a
when operating with a reduced span due to the increased
sine wave is given by
sensitivity of the converter.
SNR = (6.02N + 1.76)dB
ANALOG INPUTS AND SAMPLE/HOLD
where N is the number of bits. Thus for ideal 8-bit converter,
An important feature of the ML2281 family of devices is that
SNR = 49.92dB.
they can be located at the source of the analog signal and
then communicate with a controlling µP with just a few
wires. This avoids bussing the analog inputs long distances Harmonic Distortion
and thus reduces noise pickup on these analog lines.
Harmonic distortion is the ratio of the RMS sum of
However, in some cases, the analog inputs have a large
harmonics to the fundamental. Total harmonic distortion
common mode voltage or even some noise present along
(THD) of the ML2281 Series is defined as
with the valid analog signal.
 V 2 + V 2 + V 2 + V 2
The differential input of these converters reduces the effects
 2 3 4 5

of common mode input noise. Thus, if a common mode THD = 20 log
voltage is present on both “+” and “–” inputs, such as 60Hz, V1
the converter will reject this common mode voltage since it
only converts the difference between “+” and “–” inputs. where V1 is the RMS amplitude of the fundamental and V2,
V3, V4, V5 are the RMS amplitudes of the individual
The ML2281 family have a true sample and hold circuit harmonics.
which samples both “+” and “–” inputs simultaneously. This
simultaneous sampling with a true S/H will give common Intermodulation Distortion
mode rejection and AC linearity performance that is superior
to devices where the two input terminals are not sampled at With inputs consisting of sine waves at two frequencies, fA
the same instant and where true sample and hold capability and fB, any active device with nonlinearities will create
does not exist. Thus, the ML2281 family of devices can distortion products, of order (m + n), at sum and difference
reject AC common mode signals from DC-50kHz as well as frequencies of mfA + nfB, where m, n = 0, 1, 2, 3… .
maintain linearity for signals from DC-50kHz. Intermodulation terms are those for which m or n is not
equal to zero. The (IMD) intermodulation distortion
specification includes the second order terms (fA + fB) and
(fA – fB) and the third order terms (2fA + fB), (2fA – fB),
(fA + 2fB) and (fA – 2fB) only.

14
 ML2281, ML2282, ML2284, ML2288
ZERO ERROR ADJUSTMENT (where the LSB is calculated for the desired analog span,
1 LSB = analog span/256) is applied to selected “+” input
The zero of the A/D does not require adjustment. If the
and the zero reference voltage at the corresponding “–”
minimum analog input voltage value, VIN MIN is not ground,
input should then be adjusted to just obtain the 00000000
a zero offset can be done. The converter can be made to
to 00000001 code transition.
output 00000000 digital code for this minimum input
voltage by biasing any VIN– input at this VIN MIN value.
The full-scale adjustment should be made by forcing a
This utilizes the differential mode operation of the A/D.
voltage to the VIN+ input which is given be:
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be  (V − VMIN) 
measured by grounding the VIN– input and applying a VIN + fs adjust = VMAX − 1.5 ×  MAX 
 256 
small magnitude positive voltage to the VIN+ input. Zero
error is the difference between the actual DC input
voltage which is necessary to just cause an output digital
code transition from 00000000 to 00000001 and the ideal where VMAX = high end of the analog input range
1/2 LSB value (1/2 LSB = 9.8mV for VREF = 5.000VDC). VMIN = low end (offset zero) of the analog range
The VREF or VCC voltage is then adjusted to provide a
code change from 11111110 to 11111111.
FULL-SCALE ADJUSTMENT
The full-scale adjustment can be made by applying a SHUNT REGULATOR
differential input voltage which is 1-1/2 LSB down from
the desired analog full-scale voltage range and then A unique feature of ML2288 and ML2284 is the inclusion
adjusting the magnitude of the VREF input or VCC for a of a shunt regulator connected from V+ terminal to
digital output code which is just changing from 11111110 ground which also connects to the VCC terminal (which is
to 11111111. the actual converter supply) through a silicon diode as
shown in Figure 8. When the regulator is turned on, the
V+ voltage is clamped at 11VBE set by the internal resistor
ADJUSTMENT FOR AN ARBITRARY ANALOG ratio. The typical I-V of the shunt regulator is shown in
INPUT VOLTAGE RANGE Figure 9. It should be noted that before V+ voltage is high
If the analog zero voltage of the A/D is shifted away from enough to turn on the shunt regulator (which occurs at
ground (for example, to accommodate an analog input about 5.5V), 35kW resistance is observed between V+ and
signal which does not go to ground), this new zero GND. When the shunt regulator is not used, V+ pin
reference should be properly adjusted first. A VIN+ voltage should be either left floating or tied to GND. The
which equals this desired zero reference plus 1/2 LSB temperature coefficient of the regulator is –22mV/°C.

12V V+ VCC I+

I+→
28.8k 15mA
CURRENT LIMITING
RESISTOR, I+ ≤15mA

3.2k

3.2k
GND SLOPE = 1
35k
V+
5.5V 6.9V

Figure 8. Shunt Regulator Figure 9. I-V Characteristic of the Shunt Regulator

15
ML2281, ML2282, ML2284, ML2288
APPLICATIONS

CH0 CS P13

CLK P12
ML2288 8051

DI P11

CH7 DO P10

8051 Interface and Controlling Software

MNEMONIC INSTRUCTION
START ANL P1, #0F7H ;SELECT A/D (CS = 0)
MOV B, #5 ;BIT COUNTER ¬ 5
MOV A, #ADDR ;A ¬ MUX BIT
LOOP 1: RRC A ;CY ¬ ADDRESS BIT
JC ONE ;TEST BIT
;BIT = 0
ZERO: ANL P1, #0FEH ;DI ¬ 0
SJMP CONT ;CONTINUE
;BIT = 1
ONE: ORL P1, #1 ;D1 ¬ 1
CONT: ACALL PULSE ;PULSE SK 0 ® 1 ® 0
DJNZ B, LOOP 1 ;CONTINUE UNTIL DONE
ACALL PULSE ;EXTRA CLOCK FOR SYNC
MOV B, #8 ;BIT COUNTER ¬ 8
LOOP 2: ACALL PULSE ;PULSE SK 0 ® 1 ® 0
MOV A, P1 ;CY ¬ DO
RRC A
RRC A
MOV A, C ;A ¬ RESULT
RLC A ;A(0) BIT ¬ AND SHIFT
MOV C, A ;C ¬ RESULT
DJNZ B, LOOP 2 ;CONTINUE UNTIL DONE
RETI
;PULSE SUBROUTINE
PULSE: ORL P1, #04 ;SK ¬ 1
NOP ;DELAY
ANL P1, #0FBH ;SK ¬ 0
RET

16
 ML2281, ML2282, ML2284, ML2288
APPLICATIONS (Continued)

MUX ADDRESS

5VDC

51kΩ (4) START BIT

SGL/DIF

11 12 13 14 3 4 5 6 7
15 PARALLEL INPUTS GND 7
CLK INT
DO NC
CLK 2 INPUT SHIFT REGISTER
CLK 74HC165
+ 1 SHIFT/ 9
LOAD SIN VCC DO
10 14
START
NC 5VDC

5VDC (OR VIN)

1kΩ (8) 1/8 VCC

8 7 6 5 4 3 2 1 9

START 18 7 6 5 4 3 2 1 0 COM 17
CS D1
5 VDC ANALOG INPUTS 5VDC
CLK 16 13
CLK ML2288 SE
15 51kΩ
10kΩ NC SARS
0.01µF 14
VREF AGND DGND V+ VCC DO
CLK 12 11 10 19 20

CLOSE TO 10kΩ
START THE
A/D CONVERSION 0.001µF
1 14
CLR VCC 1
7 SI A
CLOCK GND + 10µF
GENERATOR
OUTPUT SHIFT REGISTER
74HC164
CLK 8 2
CLK
QH QA SI B
CLK
13 12 11 10 6 5 4 3
Q D
CLK
1.3kΩ (8)

1/2 74HC74 5VDC

MSB DATA DISPLAY LSB

ML2288 “Stand-Alone” or Evaluation Circuit

17
ML2281, ML2282, ML2284, ML2288

VCC
(5 VDC)

TA 3kΩ

VIN (+) VCC

LM335 +
10µF

ML2281

10kΩ 10kΩ
TA MIN VIN (–) VREF TA MAX
ADJ. ADJ.

Low-Cost Remote Temperature Sensor

18
 ML2281, ML2282, ML2284, ML2288
APPLICATIONS (Continued)

330Ω
VCC
10V
(5VDC)
6.8kΩ 5.1V

1kΩ + VCC
VIN (+) VCC GAIN VREF CLK
+ + STRAIN GAUGE –
VIN 10µF LOAD CELL DUAL
10kΩ 300Ω/30mV FS 2.7kΩ
FS 1.2kΩ 10kΩ 1MΩ
ADJ. ML2281 CS
ML2281
+
–IN
1kΩ –
SET DUAL
VIN (–) VREF VOLTAGE SPAN +IN DO
3V
+ 1MΩ 20kΩ
SETS ZERO 10V
1µF
CODE VOLTAGE 330Ω 10kΩ
OFFSET
1kΩ
2.7kΩ 2VDC
ZERO ADJ.
20kΩ

• USES ONE MORE WIRE THAN LOAD CELL ITSELF

• TWO MINI-DIPs COULD BE MOUNTED INSIDE LOAD CELL
FOR DIGITAL OUTPUT TRANSDUCER
• ELECTRONIC OFFSET AND GAIN TRIMS RELAX MECHANICAL
SPECS FOR GAUGE FACTOR AND OFFSET
• LOW LEVEL CELL OUTPUT IS CONVERTED IMMEDIATELY FOR
HIGH NOISE IMMUNITY

Zero-Shift and Span Adjust: 2V - VIN - 5V Digital Load Cell

tREF
TYPE J
+ +
T1 1kΩ CH0 VCC
– –
88.2k

ML2288
CH7 SERIAL I/O
1kΩ 910Ω
VCC
2kΩ TL064
+
22kΩ COM VREF
–

tREF LM335
TYPE J TL064 TL064
+ + – –
T8 1kΩ tREF
– – + +
88.2kΩ 820Ω 20kΩ
VCC
3kΩ
1kΩ
LM385

USES THE PSEUDO-DIFFERENTIAL MODE TO KEEP THE

DIFFERENTIAL INPUTS CONSTANT WITH CHANGES IN REFERENCE TEMPERATURE (TREF)

Convert 8 Thermocouples with only One Cold-Junction Compensator

19
ML2281, ML2282, ML2284, ML2288
APPLICATIONS (Continued)
VCC
(5VDC)

VCC 15VDC
OP

((
AMP
+ 600Ω
VIN VIN (+) VCC
+ – +
–
R 10µF
> 2.5V ≤ 2.5V
–15VDC
– + – ML2281
VREF +

ML2281
VIN (–)
R

DIODE CLAMPING IS NOT NEEDED

IF CURRENT IS LIMITED TO 25mA
CONTROLLER PERFORMS A ROUTINE TO DETERMINE WHICH
INPUT POLARITY PROVIDES A NON-ZERO OUTPUT CODE.
THIS INFORMATION PROVIDES THE EXTRA BITS.

Obtaining 9-Bit Resolution Protecting the Input

VCC 0.1Ω → ILOAD (2A FULL-SCALE)

(5VDC)
100Ω VCC
(5VDC)
VIN (–) VCC LOAD
+
240kΩ 10µF 2kΩ

ML2281 9.1kΩ

100Ω – LM336
ZERO VIN (+) VREF + 1kΩ
ADJ. + FS
3kΩ 1µF
ADJ.

120kΩ

Digitizing a Current Flow

VCC
(5VDC)
VCC
(5VDC)
20kΩ

VXDR
XDR VIN (+) VCC + VIN (+) VCC
+ +
1kΩ VIN 10µF
VIN (–)* 10µF
ZERO
ADJ. 2kΩ
10kΩ
3kΩ ML2281 10kΩ ML2281 FS
ADJ.

1kΩ –
–
VREF 1kΩ VIN (–) VREF
0.7 VCC +
FS
+
+
+ ADJ. 1µF SET FOR 3V
1µF
24kΩ
*VIN (–) = 0.15VCC
15% OF VCC ≤VXDR ≤85% OF VCC

Operating with Ratiometric Transducers Span Adjust: 0V - VIN - 3V

20
 ML2281, ML2282, ML2284, ML2288
APPLICATIONS (Continued)

→
100kΩ = 50kHZ
4mA–20mA 1N4148 1/6 74HC14

+
100Ω
1000pF
10µF
INP VCC
24kΩ 6.2kΩ 200kΩ
CD4024
VCC
VO5
+IN CLK
47µF
50pF
ML2281 100kΩ
10kΩ –IN CS
LM385–2.5V 6N139
OPTO COUPLER

3 2 10kΩ
5kΩ VREF DO VCC
LM385–2.5V 5
GND
3.9kΩ
6 8
300kΩ V+
47kΩ
VO
GND
→

• ALL POWER SUPPLIED BY LOOP

• 1500V ISOLATION AT OUTPUT

4mA–20mA Current Loop Converter

TRANSFORMER 1N4148
TRW-TC-SSD-32
VCC OUT
3 +
100µF
5 47kΩ
10kΩ 7 1N4148
CLK 2N2222
2
1
6V VCC
6
100kΩ
6V CLK
470Ω
CS VCC
VCC
4N28

100kΩ ML2288
6V
10kΩ 470Ω 8 ANALOG
CS D1 CHANNELS
2N2222 VCC
4N28
DO

10kΩ 6.8kΩ
DI 2N2222 8 2
6
5 3
• NO POWER REQUIRED REMOTELY
6N139 HIGH GAIN • 1500V ISOLATION
OPTOCOUPLER

Isolated Data Converter

21
ML2281, ML2282, ML2284, ML2288
APPLICATIONS (Continued)

START

LS193 S Q

LOAD B0
COUNT R
A B C D DOWN TMS320
SERIES
D Q

5V Q

D Q

DSP
Q

D Q

Q
ML2281 FSR
CLK CLK
VIN+
VIN– CS
DO DR
CLK

Sampling Rate 111kHz, Data Rate 1.33MHz

CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14

START

CS

FSR

HI-Z HI-Z
DO D7 D6 D5 D4 D3 D2 D1 D0

Interfacing ML2281 to TMS320 Series

22
 ML2281, ML2282, ML2284, ML2288
PHYSICAL DIMMENSIONS inches (millimeters)

Package: P08
8-Pin PDIP
0.365 - 0.385
(9.27 - 9.77)
0.055 - 0.065
(1.39 - 1.65)

0.240 - 0.260 0.299 - 0.335

PIN 1 ID
(6.09 - 6.60) (7.59 - 8.50)

1
0.020 MIN
(0.51 MIN)
(4 PLACES) 0.100 BSC
(2.54 BSC)

0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)

0.016 - 0.020 0.008 - 0.012

0.125 MIN (0.40 - 0.51) 0º - 15º (0.20 - 0.31)
(3.18 MIN)
SEATING PLANE

Package: S08
8-Pin SOIC
0.189 - 0.199
(4.80 - 5.06)
8

0.148 - 0.158 0.228 - 0.244

PIN 1 ID
(3.76 - 4.01) (5.79 - 6.20)

1
0.017 - 0.027 0.050 BSC
(0.43 - 0.69) (1.27 BSC)
(4 PLACES)
0.059 - 0.069
(1.49 - 1.75)

0º - 8º

0.012 - 0.020 0.015 - 0.035

0.055 - 0.061 0.004 - 0.010 0.006 - 0.010
(0.30 - 0.51) (0.38 - 0.89)
(1.40 - 1.55) (0.10 - 0.26) (0.15 - 0.26)
SEATING PLANE

23
ML2281, ML2282, ML2284, ML2288
PHYSICAL DIMMENSIONS inches (millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)

14

0.240 - 0.260 0.295 - 0.325

PIN 1 ID
(6.09 - 6.61) (7.49 - 8.25)

1
0.070 MIN
(1.77 MIN) 0.050 - 0.065 0.100 BSC
(4 PLACES) (1.27 - 1.65) (2.54 BSC)

0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)

0.016 - 0.022 SEATING PLANE 0.008 - 0.012

0.125 MIN (0.40 - 0.56) 0º - 15º (0.20 - 0.31)
(3.18 MIN)

Package: S14
14-Pin SOIC
0.337 - 0.347
(8.56 - 8.81)
14

0.148 - 0.158 0.228 - 0.244

PIN 1 ID
(3.76 - 4.01) (5.79 - 6.20)

1
0.017 - 0.027 0.050 BSC
(0.43 - 0.69) (1.27 BSC)
(4 PLACES) 0.059 - 0.069
(1.49 - 1.75)

0º - 8º

0.012 - 0.020 0.015 - 0.035

0.055 - 0.061 0.004 - 0.010 0.006 - 0.010
(0.30 - 0.51) SEATING PLANE (0.38 - 0.89)
(1.40 - 1.55) (0.10 - 0.26) (0.15 - 0.26)

24
 ML2281, ML2282, ML2284, ML2288
PHYSICAL DIMMENSIONS inches (millimeters)
Package: P20
20-Pin PDIP
1.010 - 1.035
(25.65 - 26.29)

20

0.240 - 0.260 0.295 - 0.325

PIN 1 ID
(6.09 - 6.61) (7.49 - 8.26)

1
0.060 MIN
(1.52 MIN) 0.055 - 0.065 0.100 BSC
(4 PLACES) (1.40 - 1.65) (2.54 BSC)

0.015 MIN
(0.38 MIN)
0.170 MAX
(4.32 MAX)

0.016 - 0.022 SEATING PLANE 0.008 - 0.012

0.125 MIN (0.40 - 0.56) 0º - 15º (0.20 - 0.31)
(3.18 MIN)

Package: Q20
20-Pin PLCC
0.385 - 0.395
(9.78 - 10.03) 0.042 - 0.056
(1.07 - 1.42)
0.350 - 0.356
(8.89 - 9.04) 0.025 - 0.045
(0.63 - 1.14)
1 (RADIUS)

0.042 - 0.048 PIN 1 ID 0.350 - 0.356 0.385 - 0.395 0.200 BSC 0.290 - 0.330
6 16
(1.07 - 1.22) (8.89 - 9.04) (9.78 - 10.03) (5.08 BSC) (7.36 - 8.38)

11
0.009 - 0.011
0.050 BSC (0.23 - 0.28)
(1.27 BSC)
0.100 - 0.110
(2.54 - 2.79)
0.026 - 0.032 0.165 - 0.180 0.146 - 0.156
(0.66 - 0.81) (4.19 - 4.57) (3.71 - 3.96)

0.013 - 0.021
(0.33 - 0.53)
SEATING PLANE

25
ML2281, ML2282, ML2284, ML2288
ORDERING INFORMATION
ALTERNATE TOTAL TEMPERATURE
PART NUMBER PART NUMBER UNADJUSTED ERROR RANGE PACKAGE

SINGLE ANALOG INPUT, 8-PIN PACKAGE

ML2281BIP (Obsolete) ADC0831CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P08)
ML2281BCP ADC0831BCN 0°C to 70°C Molded DIP (P08)
ML2281BCS (Obsolete — 0°C to 70°C Plastic SOIC (S08)

ML2281CIP (End of Life) ADC0831BCN ±1 LSB –40°C to 85°C Plastic DIP (P08)
ML2281CCP (End of Life) ADC0831CCN 0°C to 70°C Molded DIP (P08)
ML2281CCS (End of Life) — 0°C to 70°C Plastic SOIC (S08)

TWO ANALOG INPUTS, 8-PIN PACKAGE

ML2282BIP (Obsolete) ADC0832CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P08)
ML2282BCP (Obsolete) ADC0832BCN 0°C to 70°C Molded DIP (P08)
ML2282BCS (Obsolete) — 0°C to 70°C Plastic SOIC (S08)

ML2282CIP (Obsolete) ADC0832BCN ±1 LSB –40°C to 85°C Plastic DIP (P08)

ML2282CCP (Obsolete) ADC0832CCN 0°C to 70°C Molded DIP (P08)
ML2282CCS (Obsolete) — 0°C to 70°C Plastic SOIC (S08)

FOUR ANALOG INPUTS, 14-PIN PACKAGE

ML2284BIP (Obsolete) ADC0834CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P14)
ML2284BCP (Obsolete) ADC0834BCN 0°C to 70°C Molded DIP (P14)
ML2284BCS (Obsolete) — 0°C to 70°C Plastic SOIC (S14)

ML2284CIP (Obsolete) ADC0834BCN ±1 LSB –40°C to 85°C Plastic DIP (P14)

ML2284CCP (End of Life) ADC0834CCN 0°C to 70°C Molded DIP (P14)
ML2284CCS (Obsolete) — 0°C to 70°C Plastic SOIC (S14)

EIGHT ANALOG INPUTS, 20-PIN PACKAGE

ML2288BIP (Obsolete) ADC0838CCN ±1/2 LSB –40°C to 85°C Plastic DIP (P20)
ML2288BCP (Obsolete) ADC0838BCN 0°C to 70°C Molded DIP (P20)
ML2288BCQ (Obsolete) ADC0838BCV 0°C to 70°C Molded PCC (Q20)

ML2288CIP (Obsolete) ADC0838CCN ±1 LSB –40°C to 85°C Plastic DIP (P20)

ML2288CCP (Obsolete) ADC0838CCN 0°C to 70°C Molded DIP (P20)
ML2288CCQ (End of Life) ADC0838CCV 0°C to 70°C Molded PCC (Q20)

DS2281_82_84_88-01
© Micro Linear 1997 is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. 2092 Concourse Drive
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this San Jose, CA 95131
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to Tel: 408/433-5200
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility Fax: 408/432-0295
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.
5/5/97 Printed in U.S.A.
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