DATASHEET

Platform Architect

SoC architecture Overview

analysis and Synopsys Platform Architect with Multicore Optimization (MCO) technology is a
SystemC TLM standards-based graphical environment for capturing, configuring,
optimization for simulating, and analyzing the system- level performance and power of multicore
performance and systems and next-generation SoC architectures.

power Platform Architect enables system designers to explore and optimize the hardware-
software partitioning and the configuration of the SoC infrastructure, specifically the
global interconnect and memory subsystem, to achieve the right system performance,
power and cost.

Its efficient turnaround time, powerful analysis views, and available IP models make
Platform Architect the premier choice for system-level analysis and optimization of
ARM AMBA®-based SoCs.

Platform Assembly/Configuration

Performance and Power Analysis/Optimization

Figure 1: Graphical platform assembly, configuration, performance and power analysis,

and optimization of AMBA-based SoC designs in Synopsys Platform Architect

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Platform Architect is a production- proven solution used by leading Systems OEMs and Semiconductor companies worldwide.

Highlights
• Hardware-software partitioning and optimization of multicore systems
• SoC interconnect and memory sub-system performance and power optimization
• Efficient exploration using traffic generation and cycle-accurate TLM interconnect models
• Unified view of activity, performance and power for root-cause analysis
• Spreadsheet -in/spreadsheet-out sensitivity analysis
• Hardware-software validation using cycle-accurate TLM processor models
• IEEE 1666-2011 SystemC TLM-2.0

Problem: Predicting System Performance and Power

Predicting the dynamic system performance and power of today’s multi-function, multi-application SoCs requires simulation.
This impacts both system OEMs and semiconductor companies, and creates an opportunity for information sharing and
collaboration within the supply chain.

Challenges with Traditional Methods

Discovering problems with system performance and power consumption late in the development cycle can be catastrophic to project
schedules and product competitiveness, causing failure in the market. Accurate architecture analysis must be done earlier
in the design cycle:

• While spreadsheets are good for aggregating data, static spreadsheet calculations are not accurate enough to estimate
performance and power and make design decisions. Dynamic simulation is needed
• Traditional RTL simulation is too slow and lacks the configurability and visibility to analyze performance. In addition,
the RTL may simply not be available
• Risks including overdesign, underdesign, cost increases, schedule delays, and re-spins

Solution: Dynamic System-Level Simulation and Analysis

Synopsys Platform Architect provides system designers with the dynamic transaction-level simulation of performance and power,
rapid turnaround time, and powerful system-level visibility they need to greatly improve the analysis and decision making process.

Hardware-Software Partitioning and Optimization of Multicore Systems

Platform Architect with Multicore Optimization (MCO) technology enables architects to create task-driven workload models of their
end-product application for early architecture analysis.

Product trends requiring analysis Results with platform architect

 Multiple initiators and software stacks  Measurable improvement in

 Dynamic workloads product performance and power
 Complex arbitration  Reduce schedule risk by 50% vs.
traditional methods
 Advanced QoS capabilities

Figure 2: SoC performance analysis challenges and the benefits of using system-level
methods for performance and power analysis in Synopsys Platform Architect

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 • Generic task models are easily configured to create a SystemC performance model of the application, called a task-graph
• Using the task-graph, the performance workload of parallel application tasks are mapped onto Virtual Processing Unit (VPU)
task-driven traffic generators
• Simulation and task analysis enables hardware/software partitioning to be optimized for best system performance
and power well before the application software is available
• Task graphs are fully reusable as task-driven traffic generators for Interconnect and memory subsystem performance
optimization in combination with trace-driven traffic generation

Figure 3: Application task analysis for early optimization of multicore systems

Interconnect and Memory Subsystem Performance Optimization Using Trace-Driven

Traffic Generation
Platform Architect focuses on the architecture design challenges associated with the optimization and performance validation of the
backbone SoC interconnect and global memory subsystem:

• Dynamic application workloads are modeled using traffic generation, enabling early measurement of system performance and
power before software is available
• Simulation sweeping enables analysis data to be collected parametrically, exploring all traffic scenarios against the complete of
range architecture configurations
• Powerful tools for analysis visualization provide graphical transaction tracing and statistical analysis views that enable you to
identify performance and power bottlenecks, determine their root-cause, and examine the sensitivity that system performance
may have to individual or combined parameter settings

• The result is an executable specification used to carefully dimension the SoC interconnect and memory subsystem to support
the latency, bandwidth, and power requirements of all SoC components, under all operating conditions

Hardware/Software Performance Validation Using Processors Models

and Critical Software
After exploration the model of the candidate architecture can be refined to replace the trace-driven and task-driven traffic generators
with cycle- accurate processor models.

• This enables architects to validate the candidate architecture using the available performance critical software
• Software and hardware analysis views can be visualized together to provide unique system-level visibility to measure
performance and power and confirm goals are met

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Complete IEEE 1666-2011 SystemC TLM-2.0 Standards-Based Environment
Synopsys Platform Architect is a native SystemC environment fully compatible with the IEEE 1666-2011 SystemC TLM-2.0
Language Reference Manual (LRM). It supports the assembly, simulation and analysis of models containing mixed levels of
abstraction including:

• Standards-based SystemC transaction-level models using IEEE 1666-2011 TLM-2.0 and Accellera Systems Initiative (ASI) TLM
industry standards, and the open Synopsys SystemC Modeling Library (SCML) API library for highly reusable TLM-2.0 based
peripheral modeling
• Mixed SystemC/HDL co-simulation with Synopsys VCS and other third party HDL simulation environments enabling reuse of RTL
memory controllers and other IP components
• Plus, models used in Platform Architect for architecture analysis can be reused as appropriate to accelerate the creation of
Synopsys virtual prototypes for software development and software-driven verification

Model debugging using TLM Sensitivity analysis using pivot charts

port transaction tracing and analysis to aggregate and explore results

Root cause analysis using bus path Combining hardware and software analysis
and resource utilization statistics for architecture validation

Figure 4: Powerful performance analysis visualization for root-cause and sensitivity analysis in Platform Architect

Getting Started with Available Architecture IP Models

Platform Architect supports the broadest commercially available portfolio of pre-instrumented SystemC TLM IP models for
architecture exploration and validation.

Traffic Generators
• Generic File Reader Bus Master (GFRBM) for trace-driven traffic generation
• Generic Virtual Processing Unit (VPU) for application task-mapping and task-driven traffic generation

Interconnect Models
• Cycle-accurate SystemC TLM bus libraries for ARM AMBA® 2 AHB™/ APB™, AMBA 3 AXI™, and AMBA 4 AXI™ protocols, including
models for ARM CoreLink™ Network Interconnect and Synopsys DesignWare IP solutions for AMBA

• Generic approximately-timed SystemC TLM bus libraries for industry- standard IEEE 1666-2011 SystemC TLM-2.0 protocols, plus
support for the approximately-timed models available from Arteris® for the Arteris FlexNoC™ Network on Chip (NoC) interconnect,
which provide on-chip connectivity for AMBA® AXI™, AHB™, AHB-Lite, APB™, and PIF protocols

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Memory Controller Models
• Generic approximately-timed SystemC TLM memory subsystem models for ARM AXI, and IEEE-1666 2011 SystemC TLM-2.0
interfaces, including the Synopsys DesignWare Enhanced Universal DDR Memory Controller (uMCTL2)
• Cycle-accurate memory subsystem models are available for Platform Architect through HDL co-simulation with user-provided,
third-party, and Synopsys RTL memory controller IP including the Synopsys DesignWare Enhanced Universal DDR Memory
Controller (uMCTL2)

Processor Models
• Cycle-accurate SystemC TLM processor support packages (PSPs) are available for Tensilica and MIPS processor families, and
through HDL co-simulation with user-provided RTL for ARM processor families

CoStart Methodology Guidelines and Examples

More than tool-clicks, Synopsys CoStart methodology guidelines and examples for Platform Architect help educate users on
Synopsys’ state-of-the-art architecture design flow.

• Deployed exclusively through Synopsys CoStart Enablement Services

• Ensures end-user value at each step, accelerating results
• Minimizes modeling effort to get started and achieve initial value
• Maximizes ROI through exploration (not just checking)

CoStart Enablement Services

Synopsys CoStart is a packaged service that shortens the ramp-up cycle for architecture design methodologies so that users
become productive in the shortest time.

The Synopsys CoStart program contains an intense knowledge transfer, while assisting in architecture study project planning, use
case traffic capture, architecture model creation, simulation, and analysis of results.

• Tool, IP model, and methodology training

• Exclusive access to CoStart Methodology Guidelines and Examples
• Modeling services for the development and integration of custom interconnect and memory subsystem models
• Expert consulting and support

About Synopsys Virtual Prototyping Solutions

Platform Architect is part of Synopsys’ comprehensive Virtual Prototyping solution offering that:

• Provides the broadest portfolio of system-level IP models from a single supplier

• Accelerates the creation and optimization of common SoC blocks
• Facilitates SoC architecture exploration and optimization
• Provides the most complete prototyping solutions to accelerate embedded software development and system validation
• And enables value throughout the semiconductor supply chain

For more information on Platform Architect visit: synopsys.com/platformarchitect

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