1

DIGITAL ARITHMETIC
Miloš D. Ercegovac and Tomás Lang
c
Morgan Kaufmann Publishers, an imprint of Elsevier, 2004

Chapter 3: Solutions to Selected Exercises

– with contributions by Elisardo Antelo –

Exercise 3.1
As explained in the text, for two’s complement representation the most-
significant bit of each operand is inverted and −m is added, with its least-
significant bit aligned with the most-significant bit of the operands. For m = 7
we add -7 = 1001. Moreover, to avoid an extra row, we evaluate 1001 + g00 =
10g00 g0 . The resulting matrix is
a00 . a1 a2 ... an
b00 . b1 b2 ... bn
c00 . c1 c2 ... cn
d00 . d1 d2 ... dn
e00 . e1 e2 ... en
f00 . f1 f2 ... fn
0
10g0 g0 . g1 g2 ... gn

Exercise 3.3
A [5:2] module is shown in Figure E3.3a. and an array of these modules to
reduce five 8-bit operands in Figure E3.3b.
To determine the critical path we use the following delay model, simplified
from the model given in Table 2.2:

FA HA
from/to cout s cout s
(x, y) 2 0.7 1.2
x 2
y 1.5
c 1 1.2 - -

where the delay is normalized to the delay tc−c .

Figure E3.3a indicates the module delays using this model. Consequently,
the critical path delay is 5tc−c . The implementation uses 22 FAs and 2 HAs.
For comparison, an array of [3:2] modules to reduce 5 8-bit operands is
shown in Figure 3.3c.As shown, the critical path has a delay of 5.5tc−c . The
network cost is cost 22 FAs and 3 HAs. We conclude that both networks have
the same cost and that the network using [5:2] modules is somewhat faster than
the network using [3:2] modules.

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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x y c

FA
2 2
2

x y c

FA
3.2
3 3

x y c

FA 4.5
4.5

5 4.5

Figure E3.3a: The [5:2] module for Exercise 3.3.

Exercise 3.5
To determine the critical path we use the following delay model, simplified
from the model given in Table 2.2:

FA
from/to cout s
(x, y) 2
x 2
y 1.5
c 1 1.2

where the delay is normalized to the delay tc−c .

A [9:2] module is shown in Figure E3.5. The delay in the critical path is
T = 8tc−c .

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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bit position: 7 6 5 4 3 2 1 0

5 5 5 5 5 5

FA FA
2 2 2 2 2 2
2 2 2 2

[5:2] [5:2] [5:2] [5:2] [5:2] [5:2] FA FA

3 3 3 3 3 3 3 3.2 3 3.2

HA
HA
3.9 4.2
3.7 4.2 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5 4.5 5

(b)

bit position: 7 6 5 4 3 2 1 0

FA FA FA FA FA FA FA FA
2 2 2 2 2 2 2 2 2 2

FA FA FA FA FA FA FA HA
3.5 4 3.5 4 3.5 4 3.5 4 2.7 3.2
x c y x c y x c y x c y x c y x c y x c y

HA FA FA FA FA FA FA FA HA
4.2 4.7 5 5.5 5 5.5 5 5.5 5 5.5 5 5.5 5 5.5 5 5.2 3.9 4.4

(c)

Figure E3.3: (b) Network of [5:2] modules to reduce 5 8-bit operands. (c)
Network of [3:2] modules to reduce 5 8-bit operands.

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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FA FA FA
2
2
2

FA FA
4
4 4

FA
6
6 6

FA
7.5 8
7.5

Figure E3.5: The network of FAs for Exercise 3.5.

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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Exercise 3.8
A network of full-adders implementing a (15:4] counter is shown in Figure
E3.8.

FA FA FA FA FA
2 1 2 1 2 1 2 1 2 1

FA FA
4 2 2 1

FA FA
4 2 2 1

FA
(numbers indicate weights) 4 2

FA
8 4

Figure E3.8: A network of FAs implementing (15:4] counter in Exercise 3.8.

Exercise 3.10
The maximum value of the sum is S = 32 × 127. Since 211 < S = 212 − 25 <
12
2 , 12 bits are necessary.
1. The logic diagram of a bit-slice showing only CSA and registers is given
in Figure E3.10(a).
2. The block diagram at the word level is shown in Figure E3.10(b).
3. The critical path delay: ts + treg where ts is the delay of the sum output
of a FA.
4. The latency: 32 × (ts + treg ) + tCP A = 32 × (ts + treg ) + 11tc + ts where
tc is the delay of the carry output of a FA.
5. Use a CRA instead of the CSA. In this case the adder has 11 bits plus the
carry-out. The critical path is 10tc + ts + treg . Assume that ts = 2tc and
treg = ts . Then the ratio of cycle times in the two alternatives is:

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Xj [i]
Bit-slice j

FA

Cj+1 [i] PSj [i]

Cj [i]

clk
FF C FF PS

Cj [i-1] PSj [i-1]

To CPA to get S
(a)

7 X[i]

[3:2] Adder
C[i] 12 12 PS[i]
clk
Reg. C Reg. PS
C[i-1] 12 PS[i-1]
12

12 12

CPA
12
S
(b)

Figure E3.10: (a) Bit-slice of multi-operand adder. (b) Multi-operand adder of

Exercise 3.10.

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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(10tc + ts + treg )/(ts + treg ) = 7ts /2ts = 3.5

The latency of the alternative with CRA is 32 × (10tc + ts + treg ) and the
ratio of latencies is

(32 × (10tc + ts + treg )/(32 × (ts + treg ) + 12tc + ts )

= (32 × 7ts )/(32 × 2ts + 6.5ts ) = 224/70.5 = 3.2

In terms of hardware, the alterantive with CRA uses only one register
and an 11-bit adder. The alternative with CSA uses two registers and two
adders. This is roughly twice as much hardware.

Exercise 3.13
To determine the critical path we use the following delay model, simplified
from the model given in Table 2.2:

FA HA
from/to cout s cout s
(x, y) 2 0.7 1.2
x 2
y 1.5
c 1 1.2 - -

where the delay is normalized to the delay tc−c .

The [5:2] module shown in Fig. E3.13a has a critical path of 5tc−c .

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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x y c

FA
2 2
2

x y c

FA
3.2
3 3

x y c

FA 4.5
4.5

5 4.5

Figure E3.13a: [5:2] module.

To reduce the ten 4-bit operands we use an array of [5:2] modules (forming
two adders of 5 inputs each) followed by a [4:2] adder, as shown in Figure E3.13b.
The critical path delay is 8tc−c . The implementation uses 28 FAs and 6 HAs.
For comparison, Figure E3.13c shows an array of [3:2] adders to reduce 10
4-bit operands. At the full-adder level, this array is implemented as shown in
Figure E3.13d. The corresponding critical path delay is 9.2tc−c .

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bit position: 3 2 1 0

5 5

[5:2] adder FA FA
Level 2
2 2 2 2 2 2

[5:2] [5:2] FA FA
3 3 3 3.2 3 3.2

HA
HA
3.9 4.2
3.7 4.2 4.5 5 4.5 5
j i h g f e d c b a

5 5

[5:2] adder FA FA
Level 2

[5:2] [5:2] FA FA

HA
HA

3.7 4.2 4.5 5 4.5 5 3.9 4.2

i f d b
4.2 4.5 3.9
j e c
h g a
3.7 4.2 4.5 4.5 5 3.9 5 3 3 4.2 3.2 3.2

[4:2] adder FA FA FA FA HA
Level 1
6.2 5.7 6.5 6.2 6 6.2 5.2 5.4

x c y x c y

FA FA FA FA HA

7.2 7.4 7.5 7.7 7.5 8 7.2 7.4 6.1 6.6 3.9 4.4

Figure E3.13b: Network of [5:2] and [4:2] modules to reduce 10 4-bit operands.

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Level 5 [3:2] [3:2] [3:2]

Level 4 [3:2] [3:2]

Level 3 [3:2]

Level 2 [3:2]

Level 1 [3:2]

Figure E3.13c: Network of [3:2] adders to reduce 10 4-bit operands.

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FA FA FA
2
FA Level 5
2

FA FA FA FA Level 5

FA FA FA FA Level 5

FA FA FA FA FA FA FA FA Level 4
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

FA FA FA FA Level 3
6 6 6 6 6 6 6 6

FA FA Level 2
7.5 8 7.5 8

HA FA HA
Level 1

6.7 7.2 8.5 8.7 8.7 9.2

Figure E3.13d: Network of FAs and HAs to reduce 10 4-bit operands.

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Exercise 3.18
We use two [4:2] adders in the first level. Assuming that the range of each
operand is -128,127 we get a range of the output of each [4:2] adder of -512,508
requiring a width of 10 bits. Note that the sign extension could be simplified,
as done Section 3.1, reducing the width of the adders.
Performing the [4:2] addition using the modules of Figure 2.41, described by

ti+1 = M AJORIT Y (xi , yi , wi )


ti if (xi + yi + wi + zi )mod 2 = 1
ci+1 =
zi otherwise

si = (xi + yi + wi + zi + ti )mod 2
we get

73 0001001001 - 31 1111100001
- 52 1111001100 17 0000010001
22 0000010110 47 0000101111
-127 1110000001 -80 1110110000
--------- ---------
t 0010011000 t 0001000010
----------- ----------
s 0010001010 s 0000101101
c 1100100010 c 1110100100

Now one second-level[4:2] adder. The range of the result is -1024,1016, re-
quiring a width of 11 bits.

00010001010
11100100010
00000101101
11110100100
-----------
t 00001010100
-----------
s 00001110101
c 11100001000
-----------
11101111101 = -131

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Exercise 3.22
a) From the Figures we see that the reduction by columns (Figure 3.21) has
a CPA of 7 bits whereas the reduction by rows (Figure 3.27) has only 5 bits.
b) From the Figures, the critical path for reduction by columns is 4ts +
5tc + ts = 5tc + 5ts and that for reduction by rows is 5ts + 4tc .

c) Including the CPA, reduction by columns has 32 FA and 4 HA and re-

duction by rows has 32 FA and 3 HA.

Exercise 3.26
A pipelined linear array of adders is shown in Figure E3.26. For the final
adder we use a CRA with four pipelined stages, each stage having a delay similar
to a [4:2] adder.

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises

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m=8, n=6, [0,63]x8 = [0,504] --- 9 bits

Bit-matrix:

xxxxxx
xxxxxx Stage 1
xxxxxx
xxxxxx
----------
ooooooo
oooooo
xxxxxx Stage 2
xxxxxx
----------
ooooooo
oooooo
oxxxxxx Stage 3
oxxxxxx
----------
oooooooo
ooooooo (CPA with 4 pipelined stages)
----------
sssssssss

X[8,j] X[1,j]
6 6 6 6 6 6 6 6

[4:2] ADDER
Stage 1

X[1,j-1]
Stage 2 [4:2] ADDER

X[1,j-2]
Stage 3 [4:2] ADDER

- latches

Prefix Adder - 1: "gap" modules

Stage 4 Prefix Adder - 1
+2 levels of "ga" modules
S[j-3]

Stage 5 Prefix Adder - 2 Prefix Adder - 2: 2 levels of

"ga" modules + XORs
S[j-4]
(see Figure 2.20)

S[j-5]

Figure E3.26: Pipelined linear array of [4:2] adders.

Digital Arithmetic - Ercegovac & Lang 2004 Chapter 3: Solutions to Exercises