SOC Testing Methodology and Practice

Cheng-Wen Wu

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Cheng-Wen Wu. SOC Testing Methodology and Practice. DATE’05, Mar 2005, Munich, Germany.
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 SOC Testing Methodology and Practice
Cheng-Wen Wu
Department of Electrical Engineering
National Tsing Hua University
Hsinchu, Taiwan 30013, ROC

Abstract—On a commercial digital still camera (DSC) con- 2 SOC Test Aid Console (STEAC)
troller chip we practice a novel SOC test integration plat-
form, solving real problems in test scheduling, test IO reduc-
tion, timing of functional test, scan IO sharing, embedded Figure 1 shows the SOC test integration system called
memory built-in self-test (BIST), etc. The chip has been fab- STEAC—SOC Test Aid Console [4], which consists of four
ricated and tested successfully by our approach. Test results modules: the STIL Parser, Core Test Scheduler, Test Inser-
justify that short test integration cost, short test time, and tion Tool, and Pattern Translator. The STIL Parser parses the
small area overhead can be achieved. To support SOC test- test information of each IP. The test information is written in
ing, a memory BIST compiler and an SOC testing integration STIL and is generated by commercial ATPG tools. There-
system have been developed. fore, STEAC can be integrated into a typical design flow
easily. The test information includes the IO ports, scan struc-
ture (number of scan chains, length of each scan chain, etc.),
and test vectors. With these core test information, Core Test
1 Introduction Scheduler will schedule the core tests to reduce the overall
test time. The Scheduler partitions core tests into several test
It is generally agreed that, for an SOC, the design and sessions, and assigns the TAM wires to each core to meet the
test engineers usually have to test the cores with very lim- power and IO resource constraints. If the IP is a soft core,
ited knowledge of the core test information. The issues of the scan chains can be reconfigured. The Core Test Sched-
core access and isolation are being addressed by the IEEE uler will then rebalance scan chains for each assigned TAM
P1500 standard [1]. Although the standard provides unified width. The results can be fed back to the SOC integrator to
core test access methods, the test controller, test architec- reconfigure the scan chains to balance the chain length. The
ture, test access mechanism (TAM), and test integration are scheduling results are also used to generate the Test Con-
left to the SOC integrator. In [2], we stress two major is- troller, TAM bus, and Test Wrapper. Finally, the generated
sues in practical SOC test integration: 1) session-based test test circuitry is inserted into the original SOC netlist auto-
scheduling considering not only the realistic test control ar- matically. A new SOC design with DFT will be ready in
chitecture and TAM bus, but also test IO limit; and 2) the minutes. The core test patterns are generated at the core
coexistence of scan test and functional test for logic cores. A level. After the cores are wrapped, the test patterns must
commercial digital still camera (DSC) controller SOC has be translated to the wrapper level and then to the chip level.
been developed using our test integration platform—SOC The test patterns are cycle based, which can be applied by
Test Aid Console (STEAC). Results from the DSC controller external ATE easily.
chip show that our approach is more effective than others that
use non-session-based test scheduling. Also, both the scan External Tester
and functional tests are supported. All the tens of embedded
memories are tested by the built-in self-test (BIST) circuits
generated by our memory BIST compiler, BRAINS [3].
MBS MSI MBO MRD MSO MBC MBR MCK
Controller
HDL Design with DFT Information Memory
BIST

IP Test STIL Parser Sequencer Sequencer Sequencer

Info
Core Test Information

Core Test Scheduler

Scheduling Results TPG TPG TPG TPG TPG TPG

TACS TAM Wrapper

Generator Generator Generator
Test Insertion RAM RAM RAM RAM RAM RAM
DFT Ready Netlist

Wrapper Pat. Trans.

Figure 2: BIST architecture for multiple memory cores [5].
System Pat. Trans.
System Test Pattern In Fig. 2 [5] we show our memory BIST architecture,
Testable HDL Design
which supports testing of plural heterogeneous memory
cores. The tester can access all the on-chip memories via
a single shared BIST Controller, while one or more Se-
Figure 1: Test integration flow of STEAC [4]. quencers can be used to generate March-based test algo-
rithms. Each Test Pattern Generator (TPG) attached to the

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 memory will translate the March-based test commands to non-session-based approach. The total test IOs of the three
the respective RAM signals. With our automatic memory large cores are 19, including 6 clock signals, 4 reset signals,
BIST generation system, BRAINS [3], one can generate the 7 test enable signals, and 2 SE signals. With shared test IOs,
BIST circuit using the GUI or command shell, and evaluate the test control IO counts are reduced. With STEAC, the Test
the memory test efficiency among different designs easily. Wrappers, TAM, and Test Controller have been automati-
Moreover, BRAINS can be integrated with a memory com- cally generated and inserted into the original test chip design
piler to deliver BISTed memory cores. in 5 minutes, using a SUN Blade 1000 workstation with dual
750MHz processors and 2GB RAM. The area of the WBR
cell is equivalent to 26 two-input NAND gates. The Test
3 Experimental Results Controller and TAM multiplexer require about 371 and 132
gates, respectively—their hardware overhead is only about
0.3%. Again, all the embedded memories are tested with the
A DSC test chip has been implemented and fabricated to BIST circuits generated by BRAINS, which has been inte-
verify the proposed approach. This test chip is implemented grated into STEAC, as shown in Fig. 4.
with a standard 0.25µm CMOS technology. The major dig-
ital part of the chip includes a processor, JPEG codec, TV
encoder, USB, external memory interface, and tens of single-
port and two-port synchronous SRAMs with different sizes.
Figure 3 [2] gives the block diagram of this test chip. The
details are given in a companion paper [6].

Micro TV
JPEG
Processor Encoder

External Glue
Memory Memory USB
Logic
Interface

Figure 4: Integration of BRAINS into STEAC.

Figure 3: Block diagram of the test chip [2].

The IPs to be wrapped in this test chip include the USB, 4 Conclusions
TV encoder, and JPEG cores. The USB core has 4 clock
domains, 3 reset signals, 1 scan enable (SE) signal, and 6
test signals. There are 4 scan chains with dedicated scan We have presented an SOC test integration platform, with
input and output for each clock domain. The TV encoder complete solutions for real problems in test scheduling, test
has both scan and functional tests. The test pins include one IO reduction, functional test, scan IO sharing, embedded
clock, reset, SE, and test enable signals. There are two scan memory BIST, etc. The fabricated test chip has been veri-
chains in the TV encoder, where one scan chain shares the fied, and the test design has been successfully implemented
output with a functional output. The legacy JPEG core has on a commercial DSC chip. Test results justify that short test
only functional patterns and one clock domain. The clock integration cost, short test time, and small area overhead can
signals for the IPs are generated by an internal PLL. The be achieved.
detailed test information of the IPs are shown in Table 1 [2]. This work has been the result of the effort of many people,
In the scan-test mode, the USB core has 2 scan vectors that including my students who have coauthored the papers with
are enabled by SE during Pulse-Clock, while the TV encoder me, as listed in the references.
has only one.

References
Table 1: Test information of the cores [2].
[1] E. Marinissen, R. Kapur, and Y. Zorian, “On using IEEE P1500 SECT
Core TI TO PI PO Scan chains (Lengths) Patterns for test plug-n-play”, in Proc. Int. Test Conf. (ITC), 2000, pp. 770–777.
(Type) [2] K.-L. Cheng, J.-R. Huang, C.-W. Wang, C.-Y. Lo, L.-M. Denq, C.-T.
Huang, C.-W. Wu, S.-W. Hung, and J.-Y. Lee, “An SOC test integration
USB 18 4 221 104 4 (1,629, 78, 293, 45) 716 (Scan) platform and its industrial realization”, in Proc. Int. Test Conf. (ITC),
229 (Scan) Charlotte, Oct. 2004.
TV 6 1 25 40 2 (577, 576)
202,673 (Func.) [3] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C.
JPEG 1 0 165 104 No scan 235,696 (Func.) Tsai, “BRAINS: A BIST complier for embedded memories”, in Proc.
IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT),
Yamanashi, Oct. 2000, pp. 299–307.
[4] C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W.
When the test IO resource constraint is considered, par- Wu, and Y.-L. Lin, “A test access control and test integration system
allel testing may not be better than serial testing. This is for system-on-chip”, in Sixth IEEE Int. Workshop on Testing Embedded
because more test control IOs are needed for parallel testing, Core-Based System-Chips (TECS), Monterey, California, May 2002,
so fewer IO pins can be used as the test data IOs (i.e., TAM pp. P2.1–P2.8.
IOs). Since there are also cases when parallel testing leads [5] K.-L. Cheng, C.-M. Hsueh, J.-R. Huang, J.-C. Yeh, C.-T. Huang, and
to shorter test time than serial testing, it is important to take C.-W. Wu, “Automatic generation of memory built-in self-test cores for
chip IO pins into consideration so far as test time evaluation system-on-chip”, in Proc. Tenth IEEE Asian Test Symp. (ATS), Kyoto,
is concerned. In the DSC case, we tried several schedul- Nov. 2001, pp. 91–96.
ing approaches, and found that the session-based approach [6] C.-L. Chen, J.-Y. Lin, and Y.-L. Lin, “Integration, verification and lay-
(with three test sessions) has the shortest total test time— out of a complex multimedia SOC”, in Proc. Design, Automation and
Test in Europe (DATE), Munich, Mar. 2005 (to appear).
4,371,194 clock cycles as opposed to 4,713,935 cycles by

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