Scribd
Upload
37 views

Project Assignment

This document outlines Project Assignment #1, which involves developing a 4-bit Arithmetic Logic Unit (ALU) module. Students are asked to: 1. Design the ALU circuit at the transistor level and provide the schematic. 2. Simulate the design using LTspice and Electric to verify correct operation and obtain timing diagrams. 3. Layout the circuit using IcStation and report the area size. 4. Submit a project report with the design discussion, schematics, simulation results, layout, and conclusions. The report is due on May 21, 2020 and should be submitted as a single PDF file through the elearning dropbox. Teams must demonstrate their working project to

Uploaded by

batool
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
37 views

Project Assignment

This document outlines Project Assignment #1, which involves developing a 4-bit Arithmetic Logic Unit (ALU) module. Students are asked to: 1. Design the ALU circuit at the transistor level and provide the schematic. 2. Simulate the design using LTspice and Electric to verify correct operation and obtain timing diagrams. 3. Layout the circuit using IcStation and report the area size. 4. Submit a project report with the design discussion, schematics, simulation results, layout, and conclusions. The report is due on May 21, 2020 and should be submitted as a single PDF file through the elearning dropbox. Teams must demonstrate their working project to

Uploaded by

batool
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Project Assignment #1

(Team Project)
Due 5:30pm, Thursday, May 21, 2020

Specifications:
You should develop a concise layout of a module that implements a simple 4-bit Arithmetic Logic Unit
(ALU). The function chart of the ALU is given below. Assume signed (two's complement) number
representation for the two operands A and B for the add and subtract operations. The data inputs are as
follows A3-A0, B3-B0 (A3 and B3 being the most significant bits, respectively), CIN (Carry In), and
CC2-CC0 (Command Code bits, CC2 being the most significant). The outputs are as follows: F
(Function) outputs F3-F0 (F3 being the most significant bit), COUT (Carry Out), S (Sign), Z (Zero), and
OVF (Overflow). You can study various complex combinational logic architectures by reading a few
sections of Chapter 11 of the Text. In addition, you can review an ALU and Function Generator chip by
Texas Instruments under part number SN74AS181.
Command Code CC Function F
CC2 CC1 CC0
0 0 0 A
0 0 1 NOT(A)
0 1 0 A AND B
0 1 1 A OR B
1 0 0 A XOR B
1 0 1 A PLUS B w/o Carry (CIN = 0)
1 1 0 A MINUS B w/o Borrow (no initial Borrow)
1 1 1 B
The two arithmetic operations affect all flag outputs (you don't need to implement any flag register
bits at this time, though). For the four logic operations OVF must be set to 0, S and Z must evaluate
with respect to the two operands and the status of COUT is irrelevant. The two move operations must
have the same effects on the flags than that of the logic operations. You can choose any design style for
CMOS logic. Only non-complemented input signals are available. The terminal configuration of the
layout should allow access to all input signals from the top, and all output signals from the bottom of the
cell. The power lines should be on first-layer metal rails that pass completely through the cell in a
horizontal direction.
Be as generous as you can with the widths of the power lines so that their current-carrying capabilities
will be reasonably high. Use W/L ratios for your transistors such that the circuit outputs will exhibit near
minimum average propagation delays. You are going to work with a 0.25-micron CMOS technology,
however, the minimum feature size (LMIN) should not be less than 1.2 um and WMIN is 2.0 um.
Tasks:
1. Give a discussion of the main points of your design.
2. Develop a transistor-level schematics for each symbol using Design Architect. Turn in an
electronic copy of the symbol-level schematic diagram of your circuit. In addition, give the
total transistor count.
3. Verify the correct operation of your circuit using LTspice and Electric. You should also obtain
the VTC for one F output bit of your choice, as well as the worst case tPLH and tPHL delay
times for the whole circuit, and the average delay tP. Provide an electronic copy of your
simulation results and comment on them.
4. Design a layout for your circuit using IcStation. Give the size of area of a rectangle that
confines your design. Turn in an electronic copy of the layout diagram.
5. Give the product of the area, tPLH, and tPHL.
6. Demonstrate the working project to the course instructor.
Submissions:
Project Report (electronic copy) that includes:
a) Introduction
b) Discussion of your design
c) Transistor-level schematic diagrams and symbol-level schematics for the whole module
d) Simulation timing diagrams along with comments
e) Final specs of your circuit (size of area, and area-delays product included)
f) Mentor layout
g) Conclusions
Each Team must submit a joint Project Report as a single .pdf file though the appropriate
Drop Box in Elearning. Please note that the project will NOT be complete without a
suitable Project Report.

You might also like