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Advanced Digital Electronics Laboratory Exp.5

This document describes an experiment to design a 1-line-to-8-line demultiplexer using VHDL. It involves: 1) Writing VHDL code using data conversion functions to convert between data types 2) Implementing the demultiplexer design in Xilinx ISE and simulating it to verify correct outputs 3) Developing a User Constraint File (UCF) and testing the design on a Spartan 3E FPGA board. Students are asked to write an additional VHDL code using a different method and discuss how decoders can be used as demultiplexers and applications of multiplexing and demultiplexing data transmission.

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31 views

Advanced Digital Electronics Laboratory Exp.5

This document describes an experiment to design a 1-line-to-8-line demultiplexer using VHDL. It involves: 1) Writing VHDL code using data conversion functions to convert between data types 2) Implementing the demultiplexer design in Xilinx ISE and simulating it to verify correct outputs 3) Developing a User Constraint File (UCF) and testing the design on a Spartan 3E FPGA board. Students are asked to write an additional VHDL code using a different method and discuss how decoders can be used as demultiplexers and applications of multiplexing and demultiplexing data transmission.

Uploaded by

Mohamd barca
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Advanced Digital Electronics Laboratory Exp.

5
Experiment 5
Data Types in VHDL language part2
Design Example De Multiplexer
Learning Objectives
1. To convert data from one type to another using data conversion functions.
2. To design, synthesize, and simulate the operation of a 1-line-to-8-line DEmultiplexer circuit
with VHDL language.
3. Develop a User Constraint File “UCF” that maps the input and output signals to Spartan 3E
FPGA.
4. Test the Results.
Equipment and Materials:
1- Full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
2- Xilinx Spartan-3E Starter Kit, including download cable and power supply cable.
Introduction:
In order to write VHDL code efficiently, As we seen in previous experiment it is essential to
know what data types are allowed, and how to specify and use them. In this experiment,
Discussions on data compatibility and data conversion will included.
VHDL does not allow direct operations (arithmetic, logical, etc.) between data of different
types. Therefore, it is often necessary to convert data from one type to another. This can be
done in basically two ways: or we write a piece of VHDL code for that, or we invoke a
FUNCTION from a pre-defined PACKAGE. The std_logic_1164 of the ieee library provides
straightforward conversion functions. Several data conversion functions can be found in the
std_logic_arith package of the ieee library. They are:
 conv_integer(p) : Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or
STD_ULOGIC to an INTEGER value. Notice that STD_LOGIC_VECTOR is not included.
 conv_unsigned(p, b): Converts a parameter p of type INTEGER, UNSIGNED, SIGNED, or
STD_ULOGIC to an UNSIGNED value with size b bits.
 conv_signed(p, b): Converts a parameter p of type INTEGER, UNSIGNED,SIGNED, or
STD_ULOGIC to a SIGNED value with size b bits.
 conv_std_logic_vector(p, b): Converts a parameter p of type INTEGER, UNSIGNED,SIGNED,
or STD_LOGIC to a STD_LOGIC_VECTOR value with size b bits.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
...
SIGNAL a: IN UNSIGNED (7 DOWNTO 0);
SIGNAL b: IN UNSIGNED (7 DOWNTO 0);
SIGNAL y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
...
y <= CONV_STD_LOGIC_VECTOR ((a+b), 8);

1
Advanced Digital Electronics Laboratory Exp.5

Procedures:
1. Write a VHDL code including a data conversion function described in the introduction to
Design a 1-line-to-8-line DEmultiplexer.
2. Implement the 1-line-to-8-line DEmultiplexer using Xilinx ISE 9.2i tools for Spartan 3E FPGA
board. Follow the same steps in previous in Experiments to synthesize and obtain a timing
diagram after simulation to verify correct outputs.:

3. Develop a User Constraint File “UCF” file.


4. Test it by sliding the programmed switches up and down for ON and OFF.
5. Record your results (VHDL code, RTL, Timing diagram)
Report :
1- Write another VHDL code to design 1-line-to-8-line DEmultiplexer with different method.
2- Generally, can a decoder be used as a DEmultiplexer? How?
3- Multiplexing and DEmultiplexing are used when data from several sources are to be
transmitted over one line to a distant location and redistributed to several destinations.
Figure below illustrates this type of application where digital data from three sources are
sent out along a single line to three terminals at another location. Transmitted and
received signals were omitted try to complete them.

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