FPGA PROJECT

I. Playing Card Recognition

Our project uses the FPGA and the HPS on the DE1-SoC board to implement a character
recognition algorithm for playing cards. Apart from the board, our hardware consisted of an
NTSC bullet camera facing downwards onto a black background, and a wooden platform
onto which the camera was mounted. The cards we used were larger print playing cards,
since the camera resolution was low, and we needed larger characters to implement accurate
character recognition.
The video stream from the camera was input into the FPGA and then stored in memory in
the form of image captures. This memory was accessed by the VGA subsystem for display
on a VGA screen, and also by the FPGA and the HPS for analysis of the image captured.
The FPGA performs contour traversal on the image to find the outline of the card, and
detects its corners. This data is sent over to the HPS along with the image itself. The HPS
uses this data to rotate the image, extract the symbol on the top left corner, and perform
symbol recognition on it. The user interface was implemented on the console using the HPS

http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2018/ac2369_de229_vg25
4/ac2369_de229_vg254/ac2369_de229_vg254/index.html

https://www.youtube.com/watch?v=DPKz4nK2bHc&feature=youtu.be
II. Sign Language Reader
Real-time translation of American Sign Language into voice. Our approach is unique in that,
instead of translating finger spelling alphabet, we focus on a small set of common words to
translate simple conversations. We take advantage of a CNN-LSTM network to capture
temporal information, and a language model bridges the gap in grammar and styles between
English and ASL, and helps to reduce errors.
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS038
III. Hardware Ethernet Implementation
Developed an implementation of Ethernet packet tx/rx fully on hardware. Currently, there
are several projects that make use of the FPGA Ethernet port. However, none of these
projects focused on creating a modular platform to allow for easy integrate with higher
layer protocols. Other projects make use of the NIOS II for Ethernet initialization and
lower level control. A major deficiency is the lack of a full hardware implementation that
can allow for the easy implementation of higher layer protocols.

http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2014/aab85_jmv87/Fin
al/Final/index.html
IV. FPGA Speech Vocoder
Advanced Microcontroller Design and System-on-Chip is a highly parallel hardware vocoder
for real-time
speech synthesis and visualization on a monitor through a VGA interface. We designed and
implemented the vocoder for a DE1-SoC Development Kit. The entire system was built on
the board’s Cyclone V FPGA. That is, audio input, analysis, synthesis, output, and
visualization was done on the FPGA.

http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2019/jc2697_jaj263_tk455
/jc2697_jaj263_tk455/jc2697_jaj263_tk455/index.html

https://www.youtube.com/watch?v=iNSBS0w0rd4&feature=youtu.be
 V. FPGA_BASED TCAM ( Ternary Content Addressable Memory)
Wildcard or bitmask or “*” or ternary is a type of flow or rule in memory that indicates a
value that the computer does not care about. In binary, “*” could be either 1’s or 0’s. The
problem rises because on computers working with binaries electronic devices don’t a have a
blatant method to present “*”. So we hake to think of algorithms or specific hardware to
overcomes this drawback.
https://sci-hub.tw/https://ieeexplore.ieee.org/document/6665177/]
VI. Real time extraction of text from image using deep learning
The power of deep learning has given the ability to extract meaningful information from
image analysis.The real time extraction of text from images is useful for visually impaired
people to read instructions on sign boards ,get information of items during shopping and
various other applications.
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS023
VII. FPGA-Based Realtime Optical Flow Alogrithm Design and Implementation

https://pdfs.semanticscholar.org/a9bd/18fea94a8b2653eeaffb0486dc8ae8a96581.pdf

VIII. FPGA Convolution Neural Network Accelerator

Artificial intelligence starts to show its greater and greater potential at serving people’s life,
however, its massive computation requirement makes it hard to be implemented within less
strong computational tools. Compared to CPU, FPGA is much faster due to its parallel
mechanism; Compared to GPU, FPGA consumes way less energy. In this project, we want
to use FPGA as an accelerator at calculating CNN structures and in particularly, we will use
VGG16 model.
In this design, FPGA is used only to solve convolution computation, and HPS will be used to
handle the command and the rest part of layer computation including RELU and max
pooling. Due to the limitation of the memory on board, we load input and filters to registers
on FPGA line by line in a splitted manner. FPGA behaves like a huge state machine
following the command and taking data from and to HPS, and in the meanwhile, HPS will be
responsible of handling the data to and from FPGA.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2018/yr233_pq32/yr233_p
q32/yr233_pq32/index.html
IX. Wav Player
The idea is to create a music player using programmable logic and analyze the various
processes involved in the system. We designed a music player that plays music files from SD
card in real time, while providing user interaction, such as pause music, fast forward and
more. Though the initial idea was to implement a music player to play (.mp3) files from the
memory, we revised the goal to implement a music player that is capable of playing .wav
files (media files). This was performed due to various constraints involved in the design of an
mp3 decoder.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/f2010/vs327_rw363/WAV_
player/ECE%205760.htm

X. Realtime speech recognition engine

The project aimed at developing a Real Time Speech Recognition Engine on an FPGA
using Altera DE2 board. The system was designed so as to recognize the word being spoken
into the microphone. Both industry and academia have spent a considerable effort in this
field for developing software and hardware to come up with a robust solution. However, it is
because of large number of accents spoken around the world that this conundrum still
remains an active area of research. Speech Recognition finds numerous applications
including health care, artificial intelligence, human computer interaction, Interactive Voice
Response Systems, military, avionics etc. Another most important application resides in
helping the physically challenged people to interact with the world in a better way.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/f2010/np276_ksp55_aj355/
np276_ksp55_aj355/index.html
XI. Sdh Mapping And Multiplexing

http://en.cnki.com.cn/Article_en/CJFDTotal-GTXS200711018.htm
XII. Dermoscopic Image Processing For Cancer Detection

When the skin cancer is not detected in early stage can cause metastasis, consequently, the
cancer scatters to overall body. Based in this fact, the proposal consists in image processing
and machine learning approach to make a computer assists in cancer detection in acquired
images according to existent patterns
Video demo : https://www.youtube.com/watch?v=8nXnuF2HrqI&feature=youtu.be
Link : http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AS014

XIII. FPGA Implementation of Face Recofinition System Based On Convolutin

Neural Network
This paper presents a FPGA implementation of face recognition system based on
convolution neural network. The hardware architectures for convolution layers, pooling
layers, full-connected layer and softmax layer are designed. In each convolution layer, the
parallelisms among convolution kernels and among feature maps are explored, and the
convolution operations are carried out in parallel. The pooling operations for different feature
maps are also computed in parallel. The Verilog HDL modules for the architectures are
designed, simulated and synthesized to FPGA. The result shows that the architectures
designed in this paper are correct and effective.

https://www.researchgate.net/publication/331426335_FPGA_Implementation_of_Face_Rec
ognition_System_Based_on_Convolution_Neural_Network
XIV. FPGA Knn Recognition
The purpose of this project was to design an image recognition and classification system
using a kNN algorithm. Utilizing hardware acceleration, we can take a typically slow
problem such as classifying an image and turn it into a problem that takes an exponential
number of cycles to a linear number of cycles.
https://www.youtube.com/watch?v=hYRiWG278oo&feature=youtu.be

http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2018/es876_aw528_bac23
9/es876_aw528_bac239/es876_aw528_bac239/index.html

XV. FPGA_BASED Robotic Rubik’s Cube Solver

We tasked ourselves with designing a mechanical Rubik’s cube solver. The mechanical arms
rotate the cube to show each cube face of the cube to the camera. After each face is scanned,
the cube faces are passed into the Rubik’s cube solving algorithm. The algorithm computes
the moves that will be needed to solve the cube using a Nios II processor. The instructions
are then fed to the FPGA, which in turn sends PWM signals to the servos to rotate the cube
accordingly in order to solve the cube.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2015/akw62_rq35_sp2283
/akw62_rq35_sp2283/index.html
 https://www.youtube.com/watch?v=o-id_F1htPc&list=PL2E0D05BEC0140F13&index=1

XVI. Vision Based Trafic Control With Custom CNN Accelerator For Object
Detection
A unique aspect of our project is, we design and implement a brand-new highly parallelized
CNN accelerator whose single core at 100 Mhz can run a 384 x 384 RGB image through
YOLOv2: (a 23-layer state-of-the-art object detection CNN with 2 billion floating point
multiplications, 6 million comparisons, 8 billion additions) within 0.2 seconds. Multiple such
cores can be implemented in parallel / series inside an FPGA to further improve throughput.
The architecture can also be used to accelerate several other neural networks with slight
modifications.
http://www.innovatefpga.com/cgi-bin/innovate/teams.pl?Id=AP002
XVII. Binarized Neural Network for Digit Recognition on FPGA

In our project, we implemented a Binarized Neural Network (BNN) - a Convolutional

Neural Network (CNN) with binarized feature maps and weights- to perform digit
recognition on an FPGA. CNNs have extensive uses in image classification applications and
BNNs have the potential to provide the same functionality while using fewer memory and
logic resources. The project presented an interesting means by which to learn more about
machine learning from a hardware perspective.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2018/vr236_xz522/vr236_
xz522/vr236_xz522/index.html

https://www.youtube.com/watch?v=OIkAZBkXz3U&feature=youtu.be
XVIII. Oscilloscope that uses Altera 

We built the SillyScope, a 4 channel oscilloscope using DE1 SoC. Users can control the
oscilloscope using HPS. They can control the voltage scale, time scale, offsets, and the
channel to trigger. Users can also perform math operations such as addition and subtraction
with two channels. The project uses the HPS to allow user interaction and the FPGA to
sample signals and display it on VGA screen.
http://people.ece.cornell.edu/land/courses/ece5760/FinalProjects/s2017/ijt5_jgf82_jls
633/ijt5_jgf82_jls63 https://www.youtube.com/watch?v=-

_ALmpx59SQ&feature=youtu.be&list=PL2E0D05BEC0140F133/sillyscope/index.h
tml