Computer Architecture and Organization BSCS-4 Notes: Topic: Memory Organization.

Basic memory cell.

Constructing Memory using basic memory cell.

1. Memory size is expressed as NxM where N is the number of locations in the memory and M is
size of each location.
For example: 16x8 ; means there are 16 locations or slots and it can store 8 bits data in each
location.
Example: 64kx32 ; means there are 64k memory locations or slots with 32 bits or 4 byte data
in each location.

2. Accessing data.
When you want to store data in memory you access memory for memory write operation.
When you want to read data from memory you access memory for memory read operation.

Whether you want to access memory to write data or to read data , you first select the memory
location that you want to access by specifying/placing an address on the address lines.

To write data , you select a memory location by specifying address of the location where you
want to write data and , then you place data on data lines/bus and apply the memory write
control signal.

To read data ; you select a memory location by specifying address of the location whose data
you want to read and apply memory read control signal.

In both of the read or write operations there a slight delay between the moment you apply
address and the moment the data is written / read , this delay is called memory access time.

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 3. Construction of ROM using memory cells.

Fig-- Internal linear organization of an 8 x 2 ROM chip

The above schematic is an 8x2 ROM. CE is chip select input, and OE is output enable.
There are three address lines A2,A1,A0 – these are used to select one of 8 locations.
These address lines are going to inputs of a 3x8 decoder.
Each output of the decoder Enables output tri-states of the selected row of the ROM.
There are two memory cells in each row. If CE and OE inputs are active and an address is applied
to the inputs a row (a location) is selected and the data of that row appears on the two data
outputs , D1 and D0.

The same ROM can be constructed by arranging the cells in two dimensions, as shown below.

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 Fig.—Internal structure of two dimensional organization of an 8 x 2 ROM chip

4. Construction of RAM using D-type flip-flops.

Memory Design with D Flip Flops

• An example
 4X3 memory design
 Uses 12 D flip flops in a 2D array
 Uses a 2-to-4 decoder to select a row (i.e. a word or a location)
 Multiplexers are used to gate the appropriate output
 A single WRITE (WR) is used to serve as a write and read signal
– zero is used to indicate write operation
– one is used for read operation
 Two address lines are needed to select one of four words of 3 bits each

• Problems with the design

 Requires separate data in and out lines
» Cannot use the bidirectional data bus
 Cannot use this design as a building block to design larger memories
» To do this, we need a chip select input
• We need techniques to connect multiple devices to a bus

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 Techniques to Connect to a Bus.

Three techniques
 Use multiplexers
» Example
– We used multiplexers in the last memory design
» We cannot use MUXs to support bidirectional buses
 Use open collector outputs
» Special devices that facilitate connection of several outputs together
 Use tri-state buffers

A 4 X 3 memory design using D flip-flops and tri-state buffers.

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 Fig – A Block diagram representation of a 8x2 ROM

Fig -- A Block diagram representation of a 4x3 memory

Designing Larger Memories

• Issues involved
• Increasing Data size.
 To construct an 8x4 Memory using 8x2 Chips (as shown in the block
diagram above) which has 8 locations with 2 bits per location.
We can combine two of 8x2 chips so that resulting memory has 8
locations with 4 bits per location.

It is shown in the following diagram.

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 Address lines are common , data lines are separate.

If we wanted to have 8x8 memory ( 8 locations with 8 bits per

location) we will have to connect four of 8x2 chips in parallel.

 Increasing the Number of locations.

Example-1:

A 16 x 2 memory subsystem constructed from two 8 x 2 ROM chip with a)

high order interleaving. (Data Lines connected in parallel)

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  Two chips of 8x2 are used , each chip has 8 locations in it , so it needs 3
address lines to select a location of the chip.
 The total memory is 16x2 , so it has 16 locations needing 4 address lines.
 Three of the four address lines connect to the chips in parallel, the fourth
address line is used to select one out of two chips.
 8 location out of 16 are in first chip and the other 8 locations are in the
second chip.
 We need only one line to select one out of two chips. When that line is
zero , one chip is selected/enabled , and when that line is one , the other
chip is selected/enabled .
 When most significant address bit is used to select/enable chips – this is
technique is known as High Order Interleaving.
 When least significant address bit is used to select/enable chips – this is
technique is known as Low Order Interleaving.
 When High order interleaving is used , data for a block of consecutive
Addresses comes from one chip. And data for the next consecutive
addresses come from other chips.

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  When low order interleaving is used , for a block of consecutive
addresses each chip is selected alternatively.
 Banks : when more than one memory chips are used to construct larger
memory then interleaving is used. And If memory unit is selected using
n address lines then 2n = number of memory banks.

If one line is used = there are 2 banks. If 2 address lines are used then there
are 4 banks … and so on.

Example-2: Construct a 32x2 Memory using 8x2 memory.

 How many 8x2 chips are required:

Since we want to increase number of memory locations in the resulting
memory we need 4 , 8x2 chips.
 32x2 memory needs 5 address lines and 2 data output lines.
 Since we are using 8x2 chips , 3 address lines will be connected to each
chip in parallel. Remaining 2 address lines will be used two select
/enable one out of 4 chips.
 If high order interleaving is to be implemented , two most significant
address lines will be used, if low order interleaving is to be used , two
least significant address lines will be used for selection.
 A 2x4 decoder can be used to generate select lines.

Example-3: Construct 32x4 Memory using 8x2 memory.

 In this problem , both the number of locations and the data size are to
be increased.
 First of all we combine two 8x2 chips to get 8x4 unit.
 Then we combine 4 of these 8x4 units to construct 32x4 memory.
 Three address lines will be connected to each chip in parallel.
 The remaining 2 lines will be used to select one unit at a time.

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Example-4: Design a 8kx16 memory using 2kx8 memory chips.

1. Number of Banks required: 8k / 2k = 213 / 211 = 22 = 4

2. Number of chips / bank = 2 ( since chips data size is 8 and , we want to
memory with 16 bits of data.
3. Total memory chips = 2 x 4 = 8.

Example-5: To design a 64M X 32 memory, we could use

• Eight 64M X 4 in 1 X 8 array (i.e., single row)

• Eight 32M X 8 in 2 X 4 array
• Eight 16M X 16 in 4 X 2 array

In general Designing M X N memory with D X W chips

 Number of chips = M.N/D.W

 Number of rows = M/D
 Number of columns = N/W

Example-6: To design 64M X 32 memory using 16M X 16 chips

How many memory chips are required.

• Number of memory banks = 64M / 16M = 26 x 220 / 24 x 220 = 22 = 4

• Since data size is to be doubled , Number of chips = 4 x 2 = 8
• Number of address lines for 64M memory = 26
• Number of address lines connected to each chip = 24
• Number of address lines used to generate bank select = 26 – 24 = 2
• Number of lines used to select banks = 22 = 4.

Designing Larger Memories

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Assignment Questions: Submit next week.
Q1. how many bits would you need to address a 16Mx32 memory. And what is the data size.

Q2. suppose that a 16Kx8 main memory is built using 512x8 RAM chips and memory is byte
addressable.

i. how many RAM chips are needed.

Ii. How many address bits are needed for each RAM chip.

iii. How many address bits are needed for all of memory.

iv. Show connections for high-order interleaving. Use module block diagrams

v. show connections for low-order interleaving. Use module block diagram

vi. What is the size of decoder used.

Q3. suppose that a 8kx16 main memory is built using 256x8 , RAM chips and memory is word
addressable.

i. how many RAM chips are needed.

Ii. How many address bits are needed for each RAM chip.

iii. How many address bits are needed for all of memory.

iv. How many RAM chips are there per memory word.

v. How many banks will this memory have.

vi. What is the size of decoder used.

vii. Show connections for high-order interleaving.

viii. show connections for low-order interleaving.

Q4. Given a memory of 2048 bytes consisting of several 64x8 RAM chips, and assuming byte–
addressable memory, which of the following seven possibilities indicates the correct way to use the
address bits ? Explain your answer.

A. 2 bits chip select , 8 bits for address on chip.

B. 16 bits chip select , 48 bits for address on chip.

C. 6 bits chip select , 5 bits for address on chip.

D. 1 bits chip select , 5 bits for address on chip.

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 E. 5 bits chip select , 6 bits for address on chip.

F. 4 bits chip select , 6 bits for address on chip.

G. 8 bits chip select , 56 bits for address on chip.

Q5. Suppose that a 2Mx16 memory is built using 256kx8 RAM chips and memory is word addressable.

a) How many RAM chips are necessary ?

b) How many RAM chips are there per memory word ?
c) How many address bits are needed for each RAM chip ?
d) How many address bits are needed for all of memory ?
e) If High order interleaving is used which of the address bits will select memory chips.
f) What will be the size of decoder.

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