Scribd
Upload
215 views4 pages

ECE 124 Digital Circuits and Systems Assignment #6

This document contains 7 questions related to digital circuits and systems as part of an assignment. Question 1 asks to implement a JK flip-flop using a T flip-flop. Question 2 asks to derive a circuit to generate 50MHz and 25MHz clock signals from a 100MHz clock. Question 3 describes a gated SR latch and asks to design a set-dominated version. Question 4 asks to construct an SR flip-flop using a D flip-flop. Question 5 provides a timing diagram and asks about the outputs of different flip-flops. Question 6 illustrates improper SR latch operation and asks to complete a timing chart. Question 7 asks to complete a timing diagram for a JK flip-flop.

Uploaded by

jahnavi thota
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
215 views4 pages

ECE 124 Digital Circuits and Systems Assignment #6

This document contains 7 questions related to digital circuits and systems as part of an assignment. Question 1 asks to implement a JK flip-flop using a T flip-flop. Question 2 asks to derive a circuit to generate 50MHz and 25MHz clock signals from a 100MHz clock. Question 3 describes a gated SR latch and asks to design a set-dominated version. Question 4 asks to construct an SR flip-flop using a D flip-flop. Question 5 provides a timing diagram and asks about the outputs of different flip-flops. Question 6 illustrates improper SR latch operation and asks to complete a timing chart. Question 7 asks to complete a timing diagram for a JK flip-flop.

Uploaded by

jahnavi thota
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

ECE 124 digital circuits and systems

Assignment #6

Q1: Show how a JK flip-flop can be implemented with a T flip-flop and other logic gates.

Q2: Assume that you have a 100-MHz clock signal. Derive a circuit using D flip-flops to generate a 50-MHz
and 25-MHz clock signal. Draw a timing diagram for all three clock signals.

Q3: Shown below is a gated SR latch and a table explaining its operation.

R Q

G
G S R Q(t + 1)
0 X X Q(t) (no change)
S Q 1 0 0 Q(t) (no change)
1 0 1 0
1 1 0 1
1 1 1 X

Figure 1: Gated SR latch for Problem 3.

This latch has undefined behaviour when S = 1 and R = 1 and G changes from 1 to 0. This problem
can be solved by making a set dominated gated SR latch in which S = 1 and R = 1 causes the latch to
be set to 1. Design a set dominated gated SR latch and draw its circuit.

Q4: An SR flip flop is a flip-flop that has set and reset inputs like a gated SR latch. Show how to construct
an SR flip-flop using a D flip-flop and other logic gates.

1
ECE 124 digital circuits and systems Page 2

Q5: Consider the timing diagram below which shows a clock signal and a data input signal connected to the
inputs of a gated D-latch, a positive edge triggered DFF and a negative edge triggered DFF. Draw the
outputs Qa , Qb and Qc for each of the elements.

CLK
D
D Q QA
D
G Q
CLK

D Q QB
Q

D Q QC
Q
ECE 124 digital circuits and systems Page 3

Q6: Consider the SR latch shown below and the accompanying timing diagram — this problem is intended
to illustrate the improper operation of the latch if both inputs of the latch are 1 and then changed to 0
at the same time.

R P

S Q

Complete the following timing chart. Assume that P = 1 and Q = 0 initially. Assume that each NOR
gate has a delay of 10ns. Note that when t = 100ns, S and R are both changed to 0. Then, 10ns later,
both P and Q will change to 1. Because the 1’s are fed back to the gate inputs, what will happen after
another 10ns?

S
R

P
Q
0 50 100 150 200
140ns
ECE 124 digital circuits and systems Page 4

Q7: Complete the following timing diagram for a JK flip-flop.

CLK

J
K

You might also like