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Serial Adder: First Clock Pulse - Second Clock Pulse - Third Clock Pulse

The 4-bit serial adder consists of two shift registers A and B to store the numbers to be added serially and a full adder that adds one pair of bits from the registers along with a carry input at each clock pulse. A D flip-flop stores the carry output from the full adder to be used as the carry input in the next clock pulse. The serial adder adds the 4-bit numbers 0111 and 0010 stored in registers A and B respectively over 4 clock pulses, outputting the sum 0101 and a final carry of 0.

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99 views2 pages

Serial Adder: First Clock Pulse - Second Clock Pulse - Third Clock Pulse

The 4-bit serial adder consists of two shift registers A and B to store the numbers to be added serially and a full adder that adds one pair of bits from the registers along with a carry input at each clock pulse. A D flip-flop stores the carry output from the full adder to be used as the carry input in the next clock pulse. The serial adder adds the 4-bit numbers 0111 and 0010 stored in registers A and B respectively over 4 clock pulses, outputting the sum 0101 and a final carry of 0.

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SPURGEN
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SERIAL ADDER

The 4-bit serial adder consists of two shift right registers A and B, which stores the
number to be added serially. Full Adder adds the one pair of bits[(x) and(y)] and carry(z)
input at a time. A D-flip flop is used to store the carry output of the full adder (D) and output
of the D-flip flop is(Q) connected to the carry input of the full adder.

Consider the following example. Let the number (A₃A₂A₁A₀)  be 0111 and
number(B₃B₂B₁B₀) be 0010, stored in shift registers A and B respectively. Also the carry
flip-flop has been initially cleared i.e, z = 0. 

First Clock Pulse -  A₀=1 and B₀ = 0 and z=0. Output of the full adder are S = 1 and C = 0.

Second Clock Pulse -  A₁ = 1 and B₁ = 1 and z = 0, output of full adder are S=0 and Cout=1.

Third Clock Pulse -  A₂ = 1 and B₂ = 0 and z= 1, (because the output of D flip flop during
second clock pulse is 1) output of full adder are S=0 and Cout=1. 

Fourth Clock Pulse -  A₃ = 0 and B₃ = 0 and z = 1, (because the output of D flip flop during
first clock pulse is 1) output of full adder are S=1 and Cout=0.

UNIVERSAL SHIFT REGISTER

A register capable of shifting in one direction only is a unidirectional shift register.


One that can shift in both directions is a bidirectional shift register. If the register has both
shifts and parallel‐load capabilities, it is referred to as a universal shift register.
A 4-bit universal shift register consists of 4 flip-flops and four 4×1 multiplexers. All the 4
multiplexers share the same select lines(S1 and S0)to select the mode in which the shift
register operates. The select inputs select the suitable input for the flip-flops.

1. The first input (zeroth pin of multiplexer) is connected to the output pin of the
corresponding flip-flop.
2. The second input (first pin of multiplexer) is connected to the output of the very-
previous flip flop which facilitates the right shift.
3. The third input (second pin of multiplexer) is connected to the output of the very-next
flip-flop which facilitates the left shift.
4. The fourth input (third pin of multiplexer) is connected to the individual bits of the
input data which facilitates parallel loading.
The register operations performed for the various inputs of select lines are as follows:

REGISTER
S1 S0 OPERATION

0 0 No changes

0 1 Shift right

1 0 Shift left

1 1 Parallel load

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