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Systemc As An Elaborating Language With VHDL, Comparison As Well

SystemC is an object-oriented C++ library used for hardware design and modeling. It allows describing systems at different levels of abstraction from algorithmic models down to RTL. SystemC aims to close the gap between concept design and architecture design. The document compares SystemC and VHDL, finding that SystemC simulations are faster than equivalent VHDL simulations. While SystemC and VHDL use different approaches, it is possible to translate SystemC models to synthesizable VHDL with some restrictions on SystemC features.

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36 views

Systemc As An Elaborating Language With VHDL, Comparison As Well

SystemC is an object-oriented C++ library used for hardware design and modeling. It allows describing systems at different levels of abstraction from algorithmic models down to RTL. SystemC aims to close the gap between concept design and architecture design. The document compares SystemC and VHDL, finding that SystemC simulations are faster than equivalent VHDL simulations. While SystemC and VHDL use different approaches, it is possible to translate SystemC models to synthesizable VHDL with some restrictions on SystemC features.

Uploaded by

maherjas
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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SystemC as an elaborating language with VHDL, comparison

as well

Abstract

SystemC has been used since five years ago, which took the form of C++
class libraries. This language is using the form of C++, how to program
and how to set the hierarchy of the code. This methodology got from the
way of VHDL programming and Verilog as well. SystemC is using right now
to program hardware and try to reduce the gap in the high level design and
design flow, the discussion of this point is coming later with more details.
SystemC could be mentioned as a common language which catch the whole
system hierarchy and do it more robust. Everything, from the algorithmic
model to synthesizable RTL (Register Transfer Language) architecture, can
be described without having a switch in design language. SystemC really
enables refinement of a design while going to a lower level of abstraction. It
is not necessary to recode all hierarchies and interfaces anymore. SystemC
is able to reduce or may close the gap between concept and architecture
design.
as discussed SystemC is an open C++ class library used for hardware
system design and validation. The SystemC class libraries add hardware
attribute to the C++ language. One of the major advantages of SystemC is
that it can be used to describe a system at several levels of abstraction,
starting from a very high level of functional description and down to
synthesizable RTL style.
Introduction

Efficient hardware/software co-design environments cater to the need to test


entire systems early in the design cycle. These design environments allow
hardware to be modeled at a higher level of abstraction than is possible with
more traditional hardware design languages.
SystemC is such a hardware/software co-design environment that allows
hardware models to be written in C++. Consequently, the SystemC models
need to be translated to a description (usually in traditional HDLs) to be
synthesized to an actual hardware implementation. However, these
translations can be quite complex and error-prone leading to various
unwanted delays in the development process. In this thesis, we present a
software tool that provides an automated translation from SystemC models
to synthesizable VHDL models. In detail, the tool translates SystemC and
C++ (with certain restrictions) to synthesizable VHDL. Besides performing
obvious translation of many SystemC elements, the tool focuses on the
automated translation of control structures and expressions. Finally, five
real-world SystemC models (ranging from simple to complex) were
translated using the tool. Simulation of both the SystemC models and the
translated VHDL models yielded the same or expected results.
SystemC
SystemC is a not a formal language like VHDL is. It is a library of classes
and templates for C++ that provides the needed constructs for hardware
simulation. It provides a simulation kernel with which digital hardware can
be simulated using an event based simulation approach. This method is
similar to the simulation mechanisms used in most VHDL simulation
environments. SystemC defines four main constructs that can be used
in hardware modeling. These are listed below:
_ Module: This represents a single hardware entity.
_ Port: Hardware entities are interfaced through the use of ports.
_ Channels: Channels provide an event driven communications mechanism.
_ Data types: Various data types are provided that are useful in hardware
design.
SystemC was designed to be highly extensible so that all of the classes that
are defined can be extended and new ones can be defined. As an example, a
new channel could be declared to model the behavior of a specific type of
real-world communications channel.
The same applies to data types. As long as a new data type derives from the
data type interface it can be used as the type for all SystemC ports and
channels. Allowing for widespread extension of the SystemC classes for use
within a specific domain.

VHDL

VHDL is a hardware description language; the acronym stands for Very high
speed integrated circuit Hardware Description Language. It was originally
developed at the behest of the US department of Defense. They needed a
more efficient manner to document the behavior of ASIC designs that
supplier companies were presenting. It was developed as an alternative to
the huge, highly complex manuals that were the norm.
The idea to simulate such a description was immediately an attractive
prospect and logic simulators were developed the could take a VHDL
description as input. From here synthesis to the hardware level became a
focus of study and still is. Current state-ofthe-art synthesis tools can create
hardware for a large subset of the VHDL language and should at least
support the synthesizable subset in IEEE1076.6-1999[16].
The syntax of VHDL was derived from Ada, with constructs added to handle
the parallelism that appears in hardware designs. The language is strongly
typed and case insensitive. The first version of the language that was
presented in the IEEE standard 1076-1987 [14] was somewhat limited and a
new version appeared in 1993 in IEEE standard 1079-1993 [15], which
improved the consistency of the language. There have been various reviews
and updates to the standard of the languages since, but the 1993 version is
the most prominent and widely used. Both versions of the language ignored
the need for a multi-valued logic type which is where the IEEE standard
1164 comes in. This standard defines a 9-valued logic type called std logic.
This has become the standard type to use for multi-valued logic in VHDL
descriptions. The language has 1.3. BACKGROUND AND RELATED
WORK 3 been further extended in a series of libraries. One such library is
the numeric std library which implements a signed and unsigned type. These
types allow for arithmetic to be performed on arbitrarily sized logic vectors.
Methods

System C is showing fast simulation procedures comparing with VHDL, and


the following graph showing us the results:

comparison

4,5

3,5

3
Simulation

vhdl
2,5
system c
2

1,5

0,5

0
1 2 3 4 5 6 7 8 9
Time

The numbers shown are just for illustration purposes, this comparison has
been done and the result is shown as in the graph but with other real
numbers.

The next graph is taken from Alessandro Fin, universitb di Verona


DST Informatica, Verona, ITALY.
Is just to show the possibilities that System C can take under consideration
within the design level and how each one has its own diagram.

as we can see, the first possibility which is in Register Transfer Level – as


other – use a totally distinguished design generate a gate level circuit. From
other hand, other two designs are using other gate level, that just to show
you how system c is applicable to behave with the design.

So it must be at least more than one design to upgrade or develop a new


CPU relating to PC or Mobile or any other digital device.

So In general any research that should be developed or new created must


have systematic procedures to build it, those are: System requirements,
parameters, first design, implementation design, verification, and testing.
System C and VHDL both are using those procedures, may with extra steps.
Results and conclusion

In this papers, shown the definition for each VHDL and System C, and the
difference between them , with some graph only for illustration purposes.
But we saw how system C can behave and with the design to be optimized
one, moreover, to proof that System C is more efficient regarding the
simulation and need less time than time needed from VHDL.
All of this will not keep us away from the idea that we can translate system
C to VHDL, but mapping system C to VHDL can be accomplished with
restrictions to the system C inputs.

Literature

- Translation of SystemC to Synthesizable VHDL, E.P.M. van Diggele.


- Internet resources.

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