Interrupcions

Dpt. Enginyeria de Sistemes, Automàtica i Informàtica Industrial

Dpt. Enginyeria de Sistemes, Automàtica i Informàtica Industrial

Processor - I/O speed mismatch

• 1GHz microprocessor can execute 1 billion load or store

instructions per second, or 4,000,000 KB/s data rate
– I/O devices data rates range from 0.01 KB/s to 30,000 KB/s

• Input: device may not be ready to send data as fast as the processor
loads it
– Also, might be waiting for human to act

• Output: device may not be ready to accept data as fast as processor

stores it

• What to do?

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 Synchronization: Mechanisms
 Blind Cycle: Software simply waits for a fixed amount of time and assumes the I/O
will complete after that fixed delay.
Usage?
Where I/O speed is short and predictable
 Gadfly (busy waiting, polling): is a software loop that checks the I/O status waiting
for done status.
Usage?
When real time response is not important (CPU can wait)
 Interrupts: uses hardware to cause special software execution i.e. input device will
cause interrupt when it has new data!
Usage?
When real time response is crucial
 Periodic Polling: Uses a clock interrupt to periodically check the I/O Status (i.e. The
MCU or CPU will check the status)
Usage?
In situations that require interrupts but the I/O device does not support requests
 DMA: Transfer data directly to/from memory or I/O without CPU intervention.
Usage?
In situations where Bandwidth and latency are important.

Blind Cycle Synchronization: Example

 Printer can put 10 characters per second
 With Blind Cycle there is no printer status signal from printer!
 A simple software interface would be to output a character then
wait 100 ms for it to finish.
 Advantage?
 Simple
 Disadvantage?
 If output rate is variable, then time delay is wasted.

MCU Pulse Out Go Printer

8-bit
Data Out Port DATA

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 Gadfly (Busy Waiting)

Software checks a status bit in

the I/O device and loops back until
device is ready.
The Gadfly loop must precede
the data transfer for an input
device.

Interrupts
Event
main ( )
Triggers
interrupt {
signal
• Several steps have to be
completed by the processor to
}
return to the instruction
following the instruction that was
interrupted.

Handle
Interrupt

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 Support for interrupts

• Save the PC for return

– But where?
• Save other special registers (Status…)
– But where?
• Where to go when interrupt occurs?
– MCU defines location. Ex: 0x08

• Determine cause of interrupt?

– MCU has Cause Register, some bit field gives cause of
exception

Questions

• Which I/O device caused exception?

– Needs to convey the identity of the device generating the interrupt

• Can avoid interrupts during the interrupt routine?

– What if more important interrupt occurs while servicing this
interrupt?
– Allow interrupt routine to be entered again?

• Who keeps track of status of all the devices, handle errors, know
where to put/supply the I/O data?

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 Some parameters

- Priority: Which interrupt will be attended first ?

- Masking: Can an interrupt be ignored ?

- Latency: How long does it take to attend the interrupt ?

- Service time: How long takes the interrupt to be served ?

Interrupts
• An I/O interrupt is like overflow exceptions except:
– An I/O interrupt is “asynchronous”
– More information needs to be conveyed

• An I/O interrupt is asynchronous with respect to instruction

execution:
– I/O interrupt is not associated with any instruction, but it can
happen in the middle of any given instruction
– I/O interrupt does not prevent any instruction from completion

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 Interrupts, traps & exceptions

• Exception: signal marking that something “out of the ordinary”

has happened and needs to be handled

• Interrupt: asynchronous exception

• Trap: synchronous exception

Interrupts: sources
Interrupts from on-chip resources.
examples: Serial Interface Module, timer overflow, ADC, …

External Interrupts.
Examples: Input ports, IRQ line…

Software Interrupts.

Exceptions.
Examples: Opcode Trap, stack overflow, divide by zero…

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 PIC18 interrupt logic

PIC18 registers related to interrupts

These registers enable/disable the interrupts, set the priority of the interrupts, and
record the status of each interrupt source.

- RCON  Reset Control Register

- INTCON  Interruption Control Registers
- INTCON2
- INTCON3

- PIR1, PIR2, PIR3, PIR4 and PIR5  Peripheral IF’s

- PIE1, PIE2, PIE3, PIE4 and PIE5  Peripheral IE’s
- IPR1, IPR2, IPR3, IPR4 and IPR5  Peripheral IP’s

Each interrupt source has three bits to control its operation:

- An Interruption flag (IF) bit
- An Interruption enable (IE) bit
- An Interruption priority (IP) bit

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INTCON

INTCON2

8
INTCON3

RCON

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PIR1

IPR1

10
PIE1

Resum

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 PIC18 Interrupt Operation
- All interrupts are divided into core group and peripheral group.
The following interrupts are in the core group:
1. INT0…INT2 pin interrupts
2. TMR0 overflow interrupt
3. PORTB input pin (RB7…RB4) change interrupts
- The interrupt sources in the core group can be enabled by setting the GIE bit and the
corresponding enable bit of the interrupt source.
Ex: To enable TMR0 interrupt, one must set both the GIE and the TMR0IE bits to 1.
- The interrupts in the peripheral group can be enabled by setting the GIE, PEIE, and the
associated interrupt enable bits.
Ex: To enable A/D interrupt, one needs to set the GIE, PEIE, and the ADIE bits
- In order to identify the cause of interrupt, one need to check each individual interrupt
flag bit.
- When an interrupt is responded to, the GIE bit is cleared to disable further interrupt,
the return address is pushed onto return address stack and the PC is loaded with the
interrupt vector.
- Interrupt flags must be cleared in the interrupt service routine to avoid reiterative
interrupts.

Interrupt sources. Examples

INT0…INT2 Pin Interrupts
- All INT pins interrupt are edge-triggered.
- The edge-select bits are contained in the INTCON2 register.
- When an edge-select bit is set to 1, the corresponding INT pin interrupts on the
rising edge.

Port B Pins Input Change Interrupt

- An input change on pins RB7…RB4 sets the flag bit RBIF (INTCON<0>).
- If the RBIE bit is set, then the setting of the RBIF bit causes an interrupt.
- In order to use this interrupt, the RB7…RB4 pins must be configured for input.

TMR0 Overflow Interrupt

- The Timer0 module contains a 16-bit timer TMR0.
- Timer0 can operate in either 8-bit or 16-bit mode.
- When TMR0 rolls over from 0xFF to 0x00 or from 0xFFFF to 0x0000, it may
trigger an interrupt.

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 Interrupt Programming

Step 1. Write the interrupt service routine and place it in the predefined program memory.

org ox08
… ; interrupt service for high priority interrupts
retfie
org 0x18
… ; interrupt service for low priority interrupts
retfie

Step 2. Initialize the interrupt vector table

(not needed for PIC18)

Step 3. Set the appropriate interrupt enable bits to enable the desired interrupt.

Low-priority interrupt structure

- The interrupt priority scheme can be enabled or disabled using IPEN bit
- IPEN = 1 ==> enable priority levels
IPEN = 0 ==> single interrupt level (all interrupts are high priority)

- GIEL is automatically cleared when a low-priority interrupt occurs

- retfie sets again the GIEL bit, and pops the PC from stack
- Each interrupt source has associated with it a priority bit
- The default state of all priority bits is 'high' at power-on reset

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 High-priority interrupt structure
- High-priority interrupts are able to suspend the execution of low-priority ones
- When a high-priority interrupt occurs, STATUS, WREG and BSR registers are
automatically copied to shadow registers
- retfie FAST restores the shadow registers, the PC, and sets GIEH bit
- Never use retfie FAST with low-priority interrupts

Example

- By enabling the INT0 interrupt, the INT0 pin will generate an interrupt to the CPU
once every second.
- The interrupt service routine simply increments a memory counter, outputs it to the Port
D pins, and returns.
- A LED is turned on when its driving Port D pin outputs a low.

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 example
#include <p18F45K22.inc>
count equ 0x00
org 0x00
goto start
org 0x08
goto ISR_hi
org 0x18
retfie
start setf count ; count down from 255
clrf TRISD ; configure port D for output
movff count,PORTD ; output count to LEDs
bsf RCON,IPEN ; enable priority interrupt
movlw 0x90 ; enable INT0 interrupt
movwf INTCON ; and clear INT0IF flag
forever nop
bra forever

ISR_hi btfss INTCON,INT0IF ; check interrupt source

retfie ; not caused by INT0, return
decf count,F
movff count,PORTD ; output count to LEDs
bcf INTCON,INT0IF
retfie

Interrupt Programming Template in C

void interrupt low_priority tc_clr(void)
{
if (TMR1IE && TMR1IF)
{
TMR1IF=0;
tick_count = 0;
return;
void interrupt tc_int(void) }
{ // process any other low priority sources here, if required
if (TMR0IE && TMR0IF)
{ }
TMR0IF=0;
tick_count++;
return;
}
// process other interrupt sources here, if required
}

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 Example -C language version-
#include <xc.h>

unsigned char count;

void interrupt service_routine_HP (void)

{
if (INTCONbits.INT0IF && INTCONbits.TMR0IE)
{
INTCONbits.INT0IF=0;
count--;
PORTD = count; void main(void)
} {
// process other interrupt sources here, if required // Init PIC
} TRISD = 0x00; // Configure PORTD for output
count = 0xFF; // turn off all LEDs initially
void interrupt low_priority service_routine_LP(void) PORTD = count; // “
{ RCONbits.IPEN = 1; // enable priority interrupt
// Nothing to do for LP INT's in this example INTCON = 0x90; // enable GIEH and INT0 interrupt
}
while (1); // Main loop, is an idle loop
// that waits for interruptions
}

Context Saving During Interrupts

When an interrupt occurs, the PIC18 MCU saves WREG, BSR, and STATUS in the
fast register stack.

- The user can use the retfie fast instruction to retrieve these registers before returning
from the interrupt service routine.

- One can save additional registers in the stack if the interrupt service needs to modify
these registers. These registers must be restored before returning from the service
routine.

- In C language, one can add a save clause to the #pragma statement to inform the C
compiler to generate appropriate instructions for saving additional registers.
#pragma interrupt high_ISR save = reg1,…, regn
#pragma interrupt low_ISR save = reg1,…, regn

- A whole section of data can be saved by the following statements:

#pragma interrupt high_ISR save = section(“section name”)
#pragma interrupt low_ISR save = section(“section name”)

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 Saving context in RAM
If retfie fast is not used

Resets
- Resets can establish the initial values for the CPU registers, flip-flops, and control
registers of the interface chips so that the computer can function properly.
- The reset service routine will be executed after the CPU leaves the reset state.
- The reset service routine has a fixed starting address and is stored in the read only
memory.
- The PIC18 can differentiate the following types of reset:
1. Power-on reset (POR)
2. MCLR pin reset during normal operation
3. MCLR pin reset during sleep mode
4. Watchdog timer (WDT) reset (during normal operation)
5. Programmable brown-out reset (BOR)
6. RESET instruction
7. Stack full reset
8. Stack underflow reset

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 Resets vs. Interrupts
Reset/interrupts: What are the similarities and differences?

 Similarities:
1. Both are extraordinary events that cause the MPU to deviate from fetch &
decode (i.e., asynchronous)
2. Both cause the MPU to copy a special address to its Program Counter and
execute a different program (ISR).

 Differences:
1. Resets cause MPU to abort its normal fetch and execute then prepares it to start
from scratch
2. Interrupts cause MPU to abort its normal fetch and execute but returns the MPU
to the instruction following the one that was interrupted.

Interrupt latency
The 8-bit PIC-16/PIC-18 MCUs take 12 to 20 clock cycles to get to the ISR — depending
on the type of instruction that was in progress at interrupt time.
Then, in the ISR, the compiler will add instructions to determine where the interrupt
originated and to push some registers.

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