PIC18XXX Tools Quick Chart

MPLAB® C18 Compiler Software Installation Literal Instructions

To install the MPLAB C18 Compiler, run the setup program Mnemonic Description Function
from the CD-ROM. A series of dialogs will step through the
ADDLW kk ADD literal to WREG W+kk → W
setup process. When installing MPLAB C18 for the first
time, the default installation directory is C:\mcc18. ANDLW kk AND literal with W .AND. kk → W
WREG
Environment Variables CLRWDT Clear Watchdog Timer 0 → WDT, 0 → WDT
postscaler,
Use these settings either through the AUTOEXEC.BAT file 1 → TO,1 → PD
or your DOS properties so that when using MPLAB C18 DAW Decimal Adjust WREG if W<3:0> >9 or DC=1,
from the command line, the path to the executables and W<3:0>+6→W<3:0>,
header files will not have to be specified. else W<3:0> → W<3:0>;
if W<7:4> >9 or C=1,
W<7:4>+6→W<7:4>,
PATH=C:\MCC18\BIN;<additional paths for other apps> else W<7:4> → W<7:4>
Allows MPLAB C18 and the MPLINK™ linker to be IORLW kk Inclusive OR literal W .OR. kk → W
executed at the command shell prompt from any directory. with WREG
PATH=C:\MCC18\MPASM;C:\MCC18\BIN;C:\Program LFSR r,kc Load 12-bit Literal to kc → FSRr
FSR (second word)
Files\MPLAB IDE\MCHIP_Tools;%PATH%
MOVLB kb Set BSR bank kb → BSR
Allows the MPASM™ assembler to be executed at the
command shell prompt from any directory. MOVLW kk Move literal to WREG kk → W
MULLW kk Multiply lit with WREG W * kk → PRODH:PRODL
SET MCC_INCLUDE=c:\mcc18\h
SUBLW kk Subtract W from literal kk–W → W
Specifies the default search path for include files.
XORLW kk Excl OR lit with WREG W .XOR. kk → W
Help Resources
Refer to the Troubleshooting section of MPLAB IDE Help Core Memory Instructions
and the Microchip web site (www.microchip.com) for: Mnemonic Description Function
• On-line support
TBLRD* Table Read Prog Mem
• Latest development tool downloads and updates, data (no change to TBLPTR) (TBLPTR) → TABLAT
sheets, application notes, user's guides, articles and TBLRD*+ Table Read Prog Mem
sample programs (post-increment (TBLPTR) → TABLAT
TBLPTR) TBLPTR +1 → TBLPTR
• Web Conference, Design Tips, Device Errata
TBLRD*- Table Read Prog Mem
• Microchip Change Notification System (post-decrement (TBLPTR) → TABLAT
Development Systems Information Line and Technical TBLPTR) TBLPTR -1 → TBLPTR
Support: TBLRD+* Table Read TBLPTR +1 → TBLPTR
(pre-increment Prog Mem (TBLPTR) →
1-800-755-2345 for U.S. and most of Canada TBLPTR) TABLAT
1-480-792-7302 for the rest of the world. TBLWT* Table Write TABLAT → Prog
(no change to TBLPTR) Mem(TBLPTR)
Key to PIC18XXX Instruction Set TBLWT*+ Table Write TABLAT → Prog
Field Description (post-increment Mem(TBLPTR)
TBLPTR) TBLPTR +1 → TBLPTR
f, fs, fd 8-bit file register address TBLWT*- Table Write TABLAT → Prog
r 0, 1 or 2 for FSR0, FSR1, FSR2 register (post-decrement Mem(TBLPTR)
TBLPTR) TBLPTR -1 → TBLPTR
b 3-bit value representing bit position 0-7
TBLWT+* Table Write TBLPTR +1 → TBLPTR
a Access bit, 0=Access reg, 1=Use BSR (pre-increment TABLAT → Prog
d Destination bit, 0=WREG, 1=f TBLPTR) Mem(TBLPTR)

kb, kk, kc 4-, 8- and 12-bit literal value, respectively

nn 8-bit relative offset (signed, 2’s complement)
nd 11-bit relative offset (signed, 2’s complement)
mm 20-bit program memory address
Control Instructions File Register Instructions
Mnemonic Description Function Mnemonic Description Function
BC nn Relative Branch if if C=1, PC+2+2*nn→PC ADDWF f,d,a ADD WREG to f W+f → dest
Carry
ADDWFC f,d,a ADD WREG and W+f+C → dest
BN nn Relative Branch if if N=1, PC+2+2*nn→PC Carry bit to f
Negative ANDWF f,d,a AND WREG with f W .AND. f → dest
BNC nn Relative Branch if if C=0, PC+2+2*nn→PC CLRF f,a Clear f 0→f
Not Carry
COMF f,d,a Complement f ~f → dest
BNN nn Relative Branch if if N=0, PC+2+2*nn→PC
Not Negative CPFSEQ f,a Compare f with f–W, if f=W, PC+4 → PC
WREG, else PC+2 → PC
BNOV nn Relative Branch if if OV=0, PC+2+2*nn→PC skip if f=WREG
Not Overflow
CPFSGT f,a Compare f with f–W, if f > W, PC+4 → PC
BNZ nn Relative Branch if if Z=0, PC+2+2*nn→PC WREG, else PC+2 → PC
Not Zero skip if f > WREG
BOV nn Relative Branch if if OV=1, PC+2+2*nn→PC CPFSLT f,a Compare f with f–W, if f < W, PC+4 → PC
Overflow WREG, else PC+2 → PC
skip if f < WREG
BRA nd Unconditional PC+2+2*nd→PC
Relative Branch DECF f,d,a Decrement f f–1 → dest
BZ nn Relative Branch if if Z=1, PC+2+2*nn→PC DECFSZ f,d,a Decrement f, f–1 → dest, if dest=0,
Zero skip if 0 PC+4 → PC else PC+2 → PC
CALL mm,s Absolute PC+4 → TOS, DCFSNZ f,d,a Decrement f, f–1 → dest, if dest ≠ 0,
Subroutine Call mm → PC<20:1>, skip if not 0 PC+4 → PC else PC+2 → PC
(second word) if s=1, INCF f,d,a Increment f f+1 → dest
W → WS,
STATUS → STATUSS, INCFSZ f,d,a Increment f, f+1 → dest, if dest=0,
BSR → BSRS skip if 0 PC+4 → PC else PC+2 → PC
GOTO mm Absolute Branch mm → PC<20:1> INFSNZ f,d,a Increment f, f+1 → dest, if dest ≠ 0,
(second word) skip if not 0 PC+4 → PC else PC+2 → PC
NOP No Operation No operation IORWF f,d,a Inclusive OR W .OR. f → dest
WREG with f
POP Pop Top/stack TOS-1 → TOS
MOVF f,d,a Move f f → dest
PUSH Push Top/stack PC +2 → TOS
MOVFF fs,fd Move fs fs → fd
RCALL nd Relative PC+2 → TOS, (first word) to
Subroutine Call PC+2+2*nd→PC fd (second word)
RESET Generate a Reset same as MCLR reset MOVWF f,a Move WREG to f W→f
(same as MCLR MULWF f,a Multiply WREG W * f → PRODH:PRODL
reset) with f
RETFIE s Return from TOS → PC, 1 → GIE/GIEH NEGF f,a Negate f ~f + 1 → f
interrupt (and or PEIE/GIEL,
enable interrupts) if s=1, WS → W, RLCF f,d,a Rotate f left register f
STATUSS → STATUS, through Carry C 7......0
BSRS → BSR
RLNCF f,d,a Rotate f left register f
RETLW kk Return from TOS → PC, kk → W (no carry)
subroutine, store 7......0
literal in W
RRCF f,d,a Rotate f right register f
RETURN s Return from TOS → PC, through Carry C 7......0
subroutine if s=1,
WS → W, RRNCF f,d,a Rotate f right
STATUSS → STATUS, register f
(no carry)
BSRS → BSR 7......0
SLEEP Enter Sleep Mode 0 → WDT, 0 → SETF f,a Set f 0xFF → f
WDT postscaler,
1 → TO, 0 → PD SUBFWB f,d,a Subtract f from
WREG with W - f - C → dest
Borrow
Bit Instructions SUBWF f,d,a Subtract WREG f - W → dest
from f
Mnemonic Description Function
SUBWFB f,d,a Subtract WREG
BCF f,b,a Bit Clear f 0 → f<b> from f with f - W - C → dest
Borrow
BSF f,b,a Bit Set f 1 → f<b>
SWAPF f,d,a Swap nibbbles of f f<3:0> → dest<7:4>,
BTFSC f,b,a Bit test f, skip if clear if f<b>=0, PC+4→PC f<7:4> → dest<3:0>
BTFSS f,b,a Bit test f, skip if set if f<b>=1, PC+4→PC TSTFSZ f,a Test f, skip if 0 if f=0, PC+4 → PC
else PC+2 → PC
BTG f,b,a Bit Toggle f ~f<b> → f<b>
XORWF f,d,a Exclusive OR W .XOR. f → dest
WREG with f
Two Word Instructions MPLAB C18 Floating-Point Format
The PIC18XXX instruction set consists of mainly single The MPLAB C18 format for floating-point numbers is a
word (two byte) and a few double word (four byte) modified form of the IEEE 754 format. The difference
instructions. The second word of every two word between the MPLAB C18 format and the IEEE 754
instruction always has a value of 0xFn for the first byte. format consists of a rotation of the top nine bits of the
Such instructions always execute as a NOP. This allows a representation. A left rotate will convert from the IEEE 754
“skip” instruction, such as BTFSC to be used before any format to the MPLAB C18 format. A right rotate will convert
two word instruction. If the skip is taken, it will skip over the from the MPLAB C18 format to the IEEE 754 format.
first word of a two word instruction to the second word,
execute a NOP and continue on with the next instruction. Floating-
Point Byte 3 Byte 0 Byte 1 Byte 2
FAST Interrupts and FAST CALLs Standard
Bit 8 in the CALL instruction determines whether the WREG, IEEE 754 seeeeeee1 e0ddd dddd16 dddd dddd8 dddd dddd0
STATUS and BSR registers are automatically saved on the MPLAB C18 eeeeeeee0 sddd dddd16 dddd dddd8 dddd dddd0
FAST hardware stack (fast=1). Use:
Legend: s = sign bit, d = mantissa, e = exponent
call mysub,FAST
then use: Common Variable Modifiers
return FAST
Modifier Use
to let the CPU automatically save and restore WREG,
STATUS and BSR. Bit 1 in the RETURN instruction is set to const Variable will not be modified
one for FAST returns. Note that this special stack is only far Variable is paged/banked regardless of
one level deep, and FAST CALLs and FAST Interrupts memory model selected
cannot be nested. If FAST interrupts are used, FAST extern Variable is allocated in another module
CALLs must be avoided.
near Variable is not paged/banked regardless of
memory model selected
MPLAB C18 Data Types
ram Locate object in data memory
Type Bit Width Range rom Locate object in program memory
void – none static Variable is retained unchanged between
char 8 -128 to 127 executions of the defining block.
unsigned char 8 0 to 255 volatile Variable may change from other sources
(e.g., input port)
int 16 -32,768 to 32,767
unsigned int 16 0 to 65,535 Data Storage Format
short 16 -32,768 to 32,767 Endian refers to the ordering of bytes in a multi-byte value.
unsigned short 16 0 to 65,535 MPLAB C18 stores data in little-endian format. Bytes at
short long 24 -8,388,608 to 8,388,607 lower addresses have lower significance (the value is
stored “little-end-first”). For example:
unsigned short 24 0 to 16,777,215
long #pragma idata test = 0x0200
long 32 -2,147,483,648 to long ltemp = 0xAABBCCDD;
2,147,483,647
results in a memory layout as follows:
unsigned long 32 0 to 4,294,967,295
float 32 1.7549435E-38 to ltemp Address 0x0200 0x0201 0x0202 0x0203
6.80564693E+38
ltemp Contents 0xDD 0xCC 0xBB 0xAA
double 32 1.7549435E-38 to
6.80564693E+38
Pointer Sizes
Note: A plain char is signed by default.
A plain char may be unsigned by default via the Pointer Type Example Size
-k command-line option. Data memory char * dmp; 16 bits
near char * npmp;
Near pgm memory rom near char * npmp; 16 bits
Far pgm memory rom far char * fpmp; 24 bits
Instruction Macros Compiler Managed Resources at Interrupts
These macros are provided for efficient use of some of the MPLAB C18 will save some registers automatically when
PIC18XXX instructions directly from C code: an interrupt occurs. In order to make sure that other
registers are saved and restored properly use the save=
Instruction1 Macro Action construct in the #pragma interrupt declaration.
Nop() Execute a no Compiler-
operation. Managed Primary Use(s) Auto
Resource Saved
ClrWdt() Clear the watchdog
timer. PC execution control x
Sleep() Execute a SLEEP WREG intermediate calculations x
instruction. STATUS calculation results x
Reset() Execute a device BSR bank selection x
reset.
PROD multiplication results,
Rlcf(var, dest, access)2,3 Rotate var to the left return values, intermediate
through the carry bit. calculations
Rlncf(var, dest, access)2,3 Rotate var to the left section.tmpdata intermediate calculations
without affecting the
carry bit. FSR0 pointers to RAM x
FSR1 stack pointer x
Rrcf(var, dest, access)2,3 Rotate var to the right
through carry bit. FSR2 frame pointer x
accessing values in
Rrncf(var, dest, access)2,3 Rotate var to the right
TBLPTR
without affecting the program memory
carry bit. TABLAT accessing values in
program memory
Swapf(var, dest, access)2,3 Swap the upper and
lower nibble of var. PCLATH function pointer invocation
Note 1: Using any of these macros in a function affects PCLATU function pointer invocation
the ability of the MPLAB C18 compiler to perform section arguments, return values
optimizations on that function. MATH_DATA and temporary locations for
2: var must be an 8-bit quantity (i.e., char) and not math library functions
located on the stack.
3: If dest is 0, the result is stored in WREG, and if Note: Compiler temporary variables for non-ISR functions
dest is 1, the result is stored in var. If access is are placed in an access qualified udata section
0, the access area will be selected, overriding the named .tmpdata. Interrupt service routines each
BSR value. If access is 1, then the bank will be create a separate section for temporary data storage,
selected according to the BSR value. so, section .tmpdata doesn’t need to be saved if the
ISR makes no function calls.

MPLAB C18 Interrupts 18F452i Linker Script

To create an interrupt service routine no additional libraries Linker scripts tell MPLINK which areas of memory are
are required. Follow these steps: available for data and program code. Here is a linker script
• Create a code section at the interrupt vector that for debugging a PIC18F452 application with MPLAB ICD 2.
contains a goto isr statement, either using inline CODEPAGE NAME=vectors START=0x0 END=0x29 PROTECTED
assembly or a separate assembly file. CODEPAGE NAME=page START=0x2A END=0x7DBF
CODEPAGE NAME=debug START=0x7DC0 END=0x7FFF PROTECTED
• Declare the interrupt routine in the source code using
CODEPAGE NAME=idlocs START=0x200000 END=0x200007 PROTECTED
one of the following statements: CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED
High-priority interrupts – W, BSR and STATUS are saved in CODEPAGE NAME=devid START=0x3FFFFE END=0x3FFFFF PROTECTED
shadow registers. CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED

#pragma interrupt <isr> [save=symbol-list] ACCESSBANK NAME=accessram START=0x0 END=0x7F

DATABANK NAME=gpr0 START=0x80 END=0xFF
Low-priority interrupts – W, BSR and STATUS are saved on DATABANK NAME=gpr1 START=0x100 END=0x1FF
the software stack. DATABANK NAME=gpr2 START=0x200 END=0x2FF
DATABANK NAME=gpr3 START=0x300 END=0x3FF
#pragma interruptlow <isr> [save=sym-list] DATABANK NAME=gpr4 START=0x400 END=0x4FF
DATABANK NAME=gpr5 START=0x500 END=0x5F3
If your ISR calls non-ISR functions, the temporary data DATABANK NAME=dbgspr START=0x5F4 END=0x5FF PROTECTED
section must be saved. This is done using the section ACCESSBANK NAME=accesssfr START=0xF80 END=0xFFF PROTECTED
qualifier on the save= keyword. SECTION NAME=CONFIG ROM=config
#pragma interruptlow <isr> This linker script is for use with MPLAB ICD 2, so the area
|save=section(".tmpdata"| in program memory assigned to the CODEPAGE area
debug and the area in RAM noted by the DATABANK area
dbgspr are marked PROTECTED.
Locating Code Configuration Bits
Following a #pragma code directive, all generated code The #pragma romdata CONFIG directive is used to set
will be assigned to the specified code section until another the current romdata section to the section named CONFIG.
#pragma code directive is encountered. An absolute The configuration for the device can be specified using the
code section allows the location of code to a specific _CONFIG_DECL macro and the #defines located in the
address. For example: processor-specific header file.
#pragma code my_code=0x2000 #include <p18c452.h>
will locate the code section my_code at program memory #pragma romdata CONFIG
address 0x2000. If the address is left blank, the linker will _CONFIG_DECL
choose from available free blocks of code space. (_CP_ON_1L,
_OSCS_ON_1H & _OSC_LP_1H,
Locating Data _PWRT_ON_2L & _BOR_OFF_2L &
_BORV_42_2L,
Data can be placed in either data or program memory with
_WDT_OFF_2H & _WDTPS_1_2H,
the MPLAB C18 compiler. To locate data in RAM, it can
_CCP2MUX_OFF_3H,
either be uninitialized data (udata) or initialized data
_CONFIG4L_DEFAULT);
(idata). When using intialized data, all the data is stored
#pragma romdata
in program memory and then moved to RAM before the
void main (void)
main application function at main is executed (this is done
{
in the object file c018i.o). The following declares a
...
section for statically allocated uninitialized data (udata) at
}
absolute address 0x120:
#pragma udata my_new_data_section=0x120 Return Values
Data that is placed in on-chip program memory can be Functions that return values will return them in different
read but not written without additional user-supplied code. registers depending upon the return value size:
The rom keyword tells the compiler that the data should be
placed in program memory. The compiler will allocate this Return Return Value Location
Value Size
data into the current romdata type section. For example:
8 bits WREG
#pragma romdata const_table
const rom char my_const_array[10]= 16 bits PRODH:PRODL
{0,1,2,3,4,5,6,7,8,9}; 24 bits (AARGB2+2):(AARGB2+1):AARGB2
/* Resume allocation of romdata 32 bits (AARGB3+3):(AARGB3+2):(AARGB3+1):
into the default section */ ARGB3
#pragma romdata
> 32 bits On the stack, FSR0 points to the return value
MPLAB C18 In-line Assembly
MPLAB C18 has an internal assembler with a syntax PIC18XXX Library Files
similar to the MPASM assembler, except that comments File Use
must be in the C (/* */) or C++ (//) style. The block of
assembly code must begin with _asm and end with clib.lib Standard C routines, math routines.
_endasm. For example: c018i.o Startup code with initialized data support.
_asm c018iz.o Startup code with initialized data support
/* User assembly code */ that clears unused RAM.
MOVLW 10 // Move decimal 10 to count c018.o Startup code without initialized data support.
MOVWF count, 0
p18xxxx.lib Peripheral library routines and SFR
/* Loop until count is 0 */ definitions.
start:
DECFSZ count, 1, 0 xxxx = Processor type (e.g., C452 for PIC18C452)
GOTO done
BRA start
done:
_endasm
Note that with in-line assembly, the access bit and the
destination bit must be explicitly entered for each
instruction.
MPLAB ICD 2 Alerts MCLR While Single Stepping
PLL Initiating a master clear on the MCLR pin will not reset the
processor when in step mode.
Care should be taken when programming the Phase
Locked Loop oscillator (PLL). The PLL only changes when Emulator Unimplemented GPRs
power is first applied to the chip. When programming the Some unimplemented General Purpose Registers in the
PLL for the first time, remove power from the PIC18FXXX emulator can be written. Therefore, their read values are
part after programming and reapply for the PLL to be not guaranteed to be zero (as is the case in the actual
enabled. When reprogramming the device from PLL mode device).
to another mode, first reprogram with PLL off, then remove
power and reapply. Low Voltage Emulation
In-circuit emulation is limited to 2.5 to 5.5 volts.
Flash Memory Blocks
For a range of program memory, the Start Address must Table Write Results in MPLAB IDE Windows
be set to the beginning of an 8-byte block. The End If performing table writes, "Upload Program Memory from
Address must be set to the end of an 8-byte block, i.e., a ICE" must be selected before the Program Memory
Start Address of 0x10 and an End Address of 0x1F. window will be modified.
If a programming error is received due to an incorrect End
Address, click the Connect button, correct the End Table Reads of Breakpoint Locations
Address and click the Program button again. If performing table reads, a software breakpoint will be a
TRAP instruction, so these locations will not read correctly
PIC18FXX20 when performing program memory reads. This will affect
All AVDD and AVSS pins must be connected for the device any run-time checksum routines. It is recommended that
to program. run-time checksums be disabled while debugging.

General Alerts Additional Reference Documents

SLEEP PICmicro 18C MCU Family Reference Manual (DS39500)
Do not single step into, set a breakpoint on or break/halt MPLAB C18 C Compiler Getting Started (DS51295)
during execution of a SLEEP instruction. If this happens, MPLAB C18 C Compiler User’s Guide (DS51288)
select Debugger>Reinitialize ICE Hardware in order to
wake up the processor module. In code, use a Watchdog MPLAB C18 C Compiler Libraries (DS51297)
Timer time-out or other suitable method to wake the Embedded Design with the PIC18F452 Microcontroller,
processor from SLEEP mode. by John B. Peatman, Prentice Hall, (c) 2003 Pearson
Edication, Inc., ISBN 0-13-046213-6.
Interrupts While Single Stepping
Interrupts will not work when single stepping through code.
Interrupts will work only when running.

Microchip Technology Inc. • 2355 West Chandler Blvd.

Chandler, AZ 85224-6199 • 480-792-7200
www.microchip.com
The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM,
PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of
Microchip Technology Incorporated n the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated
in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A.
All Rights Reserved. DS51426A