MODIFIED BOOTH RECODER FOR EFFICIENT ADD-

MULTIPLY OPERATOR

A PROJECT REPORT

Submitted by

BHARATHI.S (711011106009)

RAMALAKSHMI.V (711011106311)

SUBHASINI.T (711011106314)

ABINAYA.S (711011106313)

In partial fulfillment for the award of the degree

of

BACHELOR OF ENGINEERING

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

INFO INSTITUTE OF ENGINEERING

ANNA UNIVERSITY: CHENNAI 600 025

APRIL 2015
 BONAFIDE CERTIFICATE

Certified that this project report “MODIFIED BOOTH RECODER FOR

EFFICIENT ADD-MULTIPLY OPERATOR.” is the bonafide work of

“BHARATHI.S, RAMALAKSHMI.V, SUBHASINI.T, ABINAYA.S”,

Who carried out the project work under my supervision.

SIGNATURE SIGNATURE

DR.P.RAMANATHAN M.E., Ph.D., Mr.SURESHKUMAR (M.E).,

HEAD OF THE DEPARTMENT SUPERVISOR

Associate Professor Assistant Professor

Department of Electronics and Department of Electronics and

Communication Engineering, Communication Engineering,

Info Institute of Engineering, Info Institute of Engineering,

Kovilpalayam, Kovilpalayam,

Coimbatore-641107. Coimbatore-641107.

Internal Examiner External Examiner

 Abstract

The complex arithmetic operations are widely used in digital signal

processing applications. In this work, we focus on optimizing the design of the

fused add-multiply (FAM) operator for increasing performance. We investigate

techniques to implement the direct recoding of the sum of two numbers in its

modified booth recoding technique and explore three different schemes by

incorporating them in FAM designs.

 TABLE OF CONTENTS

CHAPTER NO TITLE PAGE NO

ABSTRACT I
LIST OF TABLES II
LIST OF FIGURES III
LIST OF ABBREVIATIONS IV
1 INTRODUCTION 1

1.1 BOOTH MULTIPLIER 1

1.1.1 Binary Multiplier 3

1.1.2 Array multiplier 3

1.1.3 An Algorithm 4

1.2 MODIFIED BOOTH MULTIPLIER 4

2 LITERATURE SURVEY 7

2.1 Low Power and Area Optimized Using

Modified Booth Algorithm Radix-2
And Radix-4. [7]. 7
2.2 Modified Booth Multiplier with Carry
Select Adder using 3-stage Pipelining
technique.[6] 7
2.3 Implementation of Modified Booth
Algorithm (Radix 4) and its Comparison
With Booth Algorithm (Radix-2). [8] 8
 2.4 FPGA Realization of Radix-4 Booth
Multiplication Algorithm for High Speed
Arithmetic Logics.[1] 8
2.5 Modified Booth Encoding Radix-4
8-bit Multiplier 9
3 PROJECT DESCRIPTION 10

3.1 OUTLINE OF THE PROJECT 10

3.2 MOTIVATION OF THE PROJECT 11

3.3 OBJECTIVE OF THE PROJECT 12

4 EXISTING METHOD 13

4.1 BOOTH ENCODER 13

4.2 PARTIAL PRODUCT GENERATOR 16

4.2.1 Binary Partial Product Generator

For Booth Multiplier 17

4.3 CORRECTION TERM 17

4.4 LIMITATIONS IN EXISTING METHOD 17

5 PROPOSED METHOD 19

5.1 RADIX -2 19

5.1.1 Drawbacks 20
 5.2 RADIX 4 20

5.2.1 Advantages of Radix 4 over radix 2 23

5.3 BOOTH RECODER 23

5.3.1 Modified Booth form 24

5.3.2 S-MB Recoding Technique 24

6 SIGNED-BIT FULL ADDERS AND HALF ADDERS 27

6.1 ADDERS 27

6.1.1 Types of adders 27

6.1.1.1 Half adder 27

6.1.1.2 Full adder 29

6.2 TWO CASES 31

6.2.1 Even Bit 31

6.2.2 Odd bit 32

6.2.3 Unsigned Input Numbers 33

6.3 CSA ADDER TREE 33

6.3.1 Wallace tree 34

6.3.2 Drawbacks 35

6.4 CLA ADDER 35

6.4.1 Disadvantage 37
7 SYSTEM SPECIFICATION 38

7.1 SOFTWARE SPECIFICATION 38

8 SOFTWARE DETAILS 39

8.1 XILINX ISE OVERVIEW 39

8.1.1 Design Entry 39

8.1.2 Synthesis 39

8.2 IMPLEMENTATION 39

8.3 VERIFICATION 40

8.3.1 Device Configuration 40

8.4 HARDWARE IMPLEMENTATION TOOL –

FPGA (SPARTAN 3E) 40

8.4.1. Technology 41

8.5 ADVANTAGES OF THE XILINX 42

8.6 FEATURES OF XILINX 42

9 SIMULATION & COMPARISION RESULTS 43

9.1 SIMULATION RESULTS 43

10 CONCLUSION 45

REFRENCES 46
 LIST OF TABLES

TABLE NO TITLE PAGE NO

4.1 Booth encoding truth table 14

5.1 Radix-2 Booth Encoding Table 19
5.2 Booth recoding strategy for each of the
Possible block values 21
5.3 Multiplier operation 22
5.4 Modified Booth encoding 25
6.1 The logic table for a half adder 28
6.2 (A) HA* Operation,
(B) HA*Dual Operation,
(C) HA** Operation 29
6.3 The logic table for a full adder 30
6.4 FA* Operation 30
6.5 FA** Operation 31
6.6 Wallace tree 34
 LIST OF FIGURES

FIGURE NO TITLE PAGE NO

1.1 Binary Multiplier 3

1.2 Array Multiplier 4

1.3 The basic Architecture of Modified

Booth Multiplier 5

1.4 Modified Booth Multiplication 6

4.1 Conventional design 13

4.2 Booth encoding structure 14

4.3 Booth encoding Layout 14

4.4 Partial product generator 16

4.5 Partial product gate level structure 16

5.1 Proposed design 19

5.2 Grouping of bits 20

5.3 Booth Recoder and its associated

Inputs and outputs 21
5.4 Proposed high performance low power multiplier 22
5.5 Booth partial product selector logic 23
5.6 (A) Boolean Equations.
(B).Gate level schematic for MB signals 25
6.1 Half adder circuit diagram 27
6.2 Boolean equations and schematics for signed
(a) HA* and (b) HA** 29
6.3 Full adder circuit diagram 29
6.4 Boolean equations and schematics for signed
(a) FA* and (b) FA** 30
6.5 S-MB recoding scheme for even number of bits. 31
6.6 S-MB recoding scheme for odd number of bits. 32
6.7 Implementation of the MSD of the S-MB recoding
Scheme in case of Unsigned input numbers for
(a) Even and (b) odd bit-width 32
6.8 CSA Adder Circuit 33
6.9 (A) Wallace tree grouping, (B) structure 34
6.10 CLA Adder Circuit 35
6.11 4-bit carry look ahead adder 36
8.1 Simulator Layout 43

9.1 Add-Multiplier output waveform 44

9.2 Synthesis report 45

LIST OF ABBERIVIATIONS
MBA Modified Booth Algorithm
PP partial product
CLA Carry-Look-Ahead
FAM Fused Add-Multiply
MB Modified Booth
PPG Partial Product Generator
BD Booth Decoder
BE Booth encoder
CSA Carry-Save Adder
CT Correction Term
HA Half Adders
FA Full Adders
ALU Arithmetic logic unit
MSD Most significant digit
ISE Integrated Software Environment
HDL Hardware Description Language
FPGA Field Programmable Gate Array
CPLD Complex Programmable Logic Device
ASIC Application-specific integrated circuit
IDE Integrated design environment