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Latches, Flip-Flops and Timers 7.1 Latches

This document summarizes latches and flip flops. It describes latches as temporary storage devices that have two stable states and are separate from flip flops. The S-R (set-reset) latch is formed with two cross-coupled NOR or NAND gates and has two inputs (set and reset) and two outputs. It can reside in either the set or reset state depending on the input, with the outputs feeding back to maintain the state.

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87 views2 pages

Latches, Flip-Flops and Timers 7.1 Latches

This document summarizes latches and flip flops. It describes latches as temporary storage devices that have two stable states and are separate from flip flops. The S-R (set-reset) latch is formed with two cross-coupled NOR or NAND gates and has two inputs (set and reset) and two outputs. It can reside in either the set or reset state depending on the input, with the outputs feeding back to maintain the state.

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CHAPTER 7

LATCHES, FLIP-FLOPS AND TIMERS


7.1 Latches
The latch is a type of temporary storage device that has two stable states (bistable) and is
normally placed in a category separate from that of flip flops. Latches are similar to flip
flops because they are bistable devices that can reside in either of two states using a
feedback input, in which the outputs are connected back to the opposite inputs.

7.1.1 The S-R (Set-Reset) Latch


A latch is a type of bistable logic device or multivibrator. An active HIGH input S-R
(SET-RESET) latch is formed with two cross coupled NOR gates, as shown in Figure
7.1.

Figure 7.1
__ __
An actice LOW input S R latch is formed with two cross soupled NAND gates, as
shown in Figure 7.2.

Figure 7.2

The operation of the latch:


__ __
1) Use the NAND gate S R latch in Figure 7.2.
2) Redrawn Figure 7.2 with the negative OR (equivalent to NAND gates)
Figure 7.3

Operation:
__ __ __
Refer Figure 7.3, Two input: S and R , Two output: Q and Q .
Assume both input and Q output are HIGH. Since the output Q is connected back to an
__
input of gate G2, and the R input is HIGH, the output of G2 must be LOW. This LOW
output is coupled back to an input of gate G1, ensuring that its output is HIGH.
When the Q output is HIGH, the latch is in the SET state.

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