MICROPROCESSOR EXIT EXAM REVIEWER

1. Based from order, when the instruction PUSHA is applied, which of the following
register is "PUSHED" last?
A. CX
B. AX
C. SI
D. DI

2. Pushes all registers to the stack

Ans. PUSHA

Note:
PUSH – push data onto stack
PUSHW - push word onto stack
PUSHD - push double word onto stack
PUSHA - push all registers to stack (60)
*Processors pushed the registers in the order: AX, CX, DX, BX, SP, BP, SI and DI. The SP
word pushed is the value before the first register is pushed.
PUSHF - push flags onto stack (9C)

3. The lower byte of the flag register contains 83h. Which flag registers are cleared as
a result of executing LAHF instruction?
A. PF (PARITY, ZERO, AUXILLIARY ARE CLEARED : MICRO BOOK PAGE 87)
B. SF
C. none of the choices
D. CF
4. The lower byte of the flag register contains 83h. Which flag registers are set as a
result of executing LAHF instruction?
A. PF
B. ZF
C. AF
D. SF (SIGN, AND CARRY FLAGS ARE SET: MICRO BOOK PAGE 87)

5. The lower byte of the flag register contains 83h. What is the result of an LAHF
instruction?
A. AH = 83h
B. AX = 83h
C. AL = 83h
D. all the flags are set to 83h

6. Machine code for LAHF

Ans. 9F
Note: 9E for SAHF
7. The higher byte of the flag register contains 83h. Which flag registers are cleared as
a result of executing LAHF instruction?
Ans. AF

8. Prevent changing the location POPA which register is not loaded with data
Ans. SP or ESP
Note: POPA Pop All Registers; Intel 80x86; move memory pointed to by stack pointer
to all 16-bit general purpose registers (except for SP); does not affect flags

9. What segment is used for store destination string?

A. ES
B. Any
C. DS
D. CS
10. Instruction that sets carry flag to 1 Note:
Ans. STC Logical Instructions – NOT, AND, OR,
XOR, TEST, BSF/BSR, BT/BTC/BTS/BTR,
Note: SETcc, SETNZ
PROGRAM CONTROL INSTRUCTIONS
CLC - Sets carry flag to 0 (clear carry flag) 14. It is an instruction used to preserve
CMC - Complement carry flag the contents of the outer loop counter
STD - Sets direction flag to 1 (set A. LOOP
direction flag) B. PUSH
CLD - Sets direction flag to 0 (clear C. PUSH and POP (MICROPROCESSOR
direction flag) PAGE 126)
STI - Set interrupt enable flag D. POP
CLI - Clear interrupt enable flag
15. It is considered as a system signal
11. What does the command IN AL, DX used in troubleshooting techniques for
mean? 8088 hardware architecture.
Ans. IN AL, DX: Input byte from I/O A. DEN
port in DX into AL B. INTR
C. HLDA (MICROPROCESSOR PAGE
12. Which of the ff is a bit manipulation 305)
instruction? D. ALE
A. SHL DL; 2
B. Any (MICROPROCESSOR BOOK Note:
PAGE 32) System signals – CLK, RESET, READY,
C. ROL AX,1 HOLD, HLDA, and MN/MX
D. NOT AL Signals involved with memory and I/O
access – ALE, RD, WR, DEN, DT/R,
Note: Check LECTURE NOTE 7- IO/M
8_MICRO_COMANLISES (Instruction Signals involved with interrupts - NMI,
Set and Programming) INTR, INTA
Bit manipulation instructions - NOT,
AND, OR, XOR, TEST, BT, BTC, BTR, BTS, 16. It is the standard bus connector
SHL/SAL, SHR, SAR, ROL, ROR, RCL, RCR agreed upon by the PC business
comprising of 62 pins found in early PC
13. Which of the following is a logical motherboards that allow expansion
instruction? with the 8088 microprocessor.
A. TEST (MICROPROCESSOR BOOK A. SATA connector
PAGE 113) B. ISA connector (MICRO PROCESSOR
B. ADC BOOK PAGE 304)
C. SHL C. RS232C connector
D. CMP D. SCSI connector
17. The following is true for r/m except
for
A. r/m are used for addressing modes
B. r/m refers to registers enclosed in
brackets
C. when mod = 11, r/m indicates a
register field
D. r/m specifies the addressing mode

18. Which is false for r/m

A. r/m refers to registers enclosed in
brackets
B. r/m are used for addressing modes
C. r/m specifies the addressing mode
D. when mod = 11, r/m indicates a
register field

19. ARM stands for

A. Advance RISC Machines
B. Advance Response Machines
C. Advance RISC Model
D. Advance Reprogrammable Model

Note:
RISC – reduced instruction set computer 22. How many additional control reg
CISC – complex instruction set computer are activated based from Pentium’s
protected mode
20. Signal that has I/O clk Ans. 5
Ans. CLK
PROPOSITION QUESTIONS
21. The 8088's I/O addressing space 23. Which is a valid conclusion?
contains how many possible Choices:
input/output ports? (a) All humming birds are richly
A. 1048576 colored
B. 4096 (b) No large birds live on honey
C. 1024 (c) Birds that do not live on honey are
D.65536 (MICROPROCESSOR BOOK dull in color
PAGE 296) (d) Hummingbirds are small
24. Consider the symbolic logic taken
from Lewis Caroll illustrating how
quantifiers are used in statements.
Which of the following is/are premises?
I. All lions are fierce
II. Some lions dont drink coffee
III. Some fierce creatures do not drink
coffee
Ans. I and II

BIG-O NOTATION QUESTIONS

27. An algorithm that uses Hamiltonian

cycle to solve uses a Big-O notation of
Ans. Logarithmic complexity
25. There exists X not P(x)
there is an x for which P(x) is false 28. An algorithm that uses Eulerian
P(x) is true for every x Path/Bubble Sort to solve uses a Big-O
there is an x for which P(x) is true notation of
every x, P(x) is false Ans. Linear complexity

29. An algorithm that uses Selection to

solve uses a Big-O notation of
Ans. Quadratic

30. 10 – 1000 gates in a single package:

Ans. MSI

26.
 34. If 8088 has frequency of 4MHz, the
time of one T state? [200 ns; 80 ns, 250
ns; 300 ns]
Ans. 250 ns

35. This input is used to force the

Pentium to limit addressable memory
to 1 Mb to emulate the memory space
of the 8086.
Ans. A20M

Note: 36. 13.mm = __ is automatically used

SSI – less than 100 components (about for direct addressing
10 gates) Ans. 00
MSI – less than 500 components or have
more than 10 but less than 100 gates 37. A processor running in this mode
LSI – between 500 and 300000 or have can exploit only the lowest 20 bits of its
more than 100 gates address bus and is therefore limited to
VLSI – more than 300000 components the meager 1MB memory space
per chip Ans. Real mode

31. What is the highest privilege (RPL) 38. This method of storing 16-bit
in protected mode? numbers in memory, wherein the lower
Ans. 00 byte is already read/write to the lower
memory address
Note: Ans. Little Endian
00 – highest
11 – lowest 39. Intel introduced cache memory for
this microprocessor when it was
32. Addressing mode executes its launched. The Western Design Center,
instructions within CPU without the Inc (WDC) introduced this
necessity of reference memory for microprocessor in 1982 and was used
operands? as the CPU in the Apple IIe and IIc
Ans. Register Mode personal computers
Ans. CMOS 8502
33. Which technique does the Pentium
Pro employs where the processor looks Note:
ahead into the instruction stream The Western Design Center, Inc. (WDC)
pipeline can be kept busy? introduced the CMOS 65C02 in 1982
Ans. Speculative execution and licensed the design to several firms.
It became the core of the Apple IIc and
IIe personal computers, medical
implantable grade pacemakers and
defibrilators, automotive, industrial 45. Questions about RAM
and consumer devices. WDC pioneered A. STATIC RAM – fast, easy interface,
the licensing of microprocessor small size (16 bytes per chip)
technology which was later followed by B. DYNAMIC RAM – high density (256K
ARM and other microprocessor per chip), requires numerous refreshing
Intellectual Property (IP) providers in cycles to retain data.
the 1990’s. Note: Both STATIC and DYNAMIC lose
info when turned off
40. The ____ part specifies the C. NVRAM (Non-Volatile Random-
addressing mode for the selected Access Memory) – retains memory even
instruction power is turned off
A. MOD ROM – Read-Only Memory, non-
B. Addr-low volatile memory
C. REG
D. R/M 46. Internal high-speed memory
(*not sure if it is the exact question)
41. Product term wherein which all Ans. CACHE
variables appear once rather
complement or uncomplemented Note:
Ans. Minterm - Advance microprocessor load more
than one instruction into this special
42. Digital integrated circuits are buffer to space time
classified not only by their complexity - While microprocessor is decoding
or logical operation, but also by the other instruction, other memory can be
specific circuit technology to which read from instruction cache.
they belong.
The circuit technology is referred to as 47. Which of the following cannot be
____. found in microprocessor/
Ans. Digital logic family microcontroller/ CPU
Choices: [Memory, ALU, Register]
43. This is the time needed by a gate in Ans. Memory
processing its input signals before the
output signal can be generated 48. Which of the following is BIT
Ans. Propagation delay time MANIPULATION?
Choices: [SHL, OR, AND]
44. Intel’s server and workstation Ans. SHL (pero sa ibang ref. lahat yan
powerhouse. bit manipulation, check lecture note 7
Choices: [Celeron, Xeon] manlises)
Ans. Xeon (Intel Microprocessor by Note:
James Antonakos) BIT MANIPULATION – SHL, SAL, SHR,
SHLD/SHRS, ROL, ROR, RCL/RCR
LOGICAL INSTRUCTIONS - NOT, AND,
OR, XOR, TEST
PROGRAM TRANSFER INSTRUCTION – 57. Where will you know if it is in 16 bit
JMP, RET, INT, BOUND, PROC, ENDP, or 32 bit?
CALL, IRET Choices: [AV, D, G, RPL]
PROCESSOR CONTROL INSTRUCTIONS Ans. D (read COE121 LECTURE NOTE
– CLC/STC, CMC, CLD/STD, CLI/STI, HLT, 5_MICRO_COMANLISES)
NOP, LOCK
58. Memory of 8 bit?
49. First commercial 8-bit processor Choices: [16kB, 8kB, 64kB]
Ans. Intel 8008 (1972) Ans. 64kB

50. Developed a single general-purpose 59. Translation lookaside buffer

chip that could be programmed to carry - a memory cache that is used to reduce
out a calculator’s function. the time taken to access a user memory
Ans. Ted Hoff location. It is a part of the chip’s
memory-management unit (MMU). The
51. Which is used as the medium of TLB stores the recent translations of
communication between the processor virtual memory to physical memory and
and the outside world. can be called an address-translation
Ans. I/O Port cache (Ref. Wikipedia)

52. Who made calculator into computer? 60. Master slave D-flip flop is similar to
Ans. Charles Babbage a synchronous edge triggered flip flop,
therefore it should have the ff behavior
53. … fast retrieval? except?
Choices: [Static RAM, Dynamic RAM, Ans. a change in output is activated by
ROM, NVRAM] a clock pulse.
Ans. STATIC RAM

54. Understand the code

Choices: [Interpreter, Compiler,
Assembler, Debugger]
Ans. Compiler

55. Type of RAM that changes during

regular interval
Choices: [Static RAM, Dynamic RAM,
ROM, NVRAM]
Ans. Dynamic RAM

56. INT AX, DX

Ans. Read from DX, write to AX
61. Race condition in R-S Latch
Ans. R=1 S=1
62. If an ASCII of A is used with odd D. Two adders with the carry output of
parity, the results is one connected to the input of the
Ans. 1100 0001 (C 1) other
63. If an ASCII of A is used with even
parity the results is 67. 2 bit by 2 bit multiplier is simply
Ans. 0100 0001 (4 1) implemented using which of the
following combinational circuit?
64. A parity bit is used in error detecting A. 2 Half Adders and 4 AND gates
codes, if an ASCII of T is used with odd B. 2 Full Adders and an OR gate
parity the result is C. 2 Full Adders and 4 AND gates
Ans. 0101 0100 (5 4) D. One 4 bit binary adder, 2 AND gates
and 1 OR gate
65. Decimal parallel adder that adds 5 Note:
decimal digits requires how many BCD
adder stages?
A. 5
B. 6
C. 3 2X2 = 4 AND
D. 4 2-1 = 1 ADDER = ½ ADDER + ½ ADDER
Note:
parallel adder: n decimal digits need n 68. If the function v(w+x+y)z would be
BCD adder stages implemented using NOR gates?
multiplier: n-1 sa isang OT, yung sinulat Ans. Six NOR gates will be used
ni gelo ndigits(ndigits-1)
69. How many 4-binary adders are
needed to create a single digit binary
adder?
Ans. 4
Note:
n binary adders = single digit binary
adder

66. 74LS83 is an example 4-bit parallel

adder. To expand this device to an 8-bit
adder, you must
A. use four adders with no
interconnections
B. use two adders and connect the sum
outputs of one to the bit inputs of the
other
C. use eight adders with no
interconnections.
70. 4-bit magnitude comparator 74. Refer to the behavior of
combinational circuit A < B what logic synchronous sequential circuit below.
gate? Assume that the states are identified as
Ans. 4-input OR gate the combination ABC. What is the
complement of the next state for an
71. 4-bit magnitude comparator input of 1, if the current state is 001?
combinational circuit A = B what logic
gate?
Ans. 4-input AND gate

72. Exclusive-OR (XOR) logic gates can

be constructed from what other logic
A. 010
gates?
B. 011
Ans. AND gates, OR gates, and NOT
C. 101
gates
D. 110
73. Given a synchronous sequential
75. Given a synchronous sequential
circuit what is the next state with
circuit what is the next state with
input = 1, if the current state is 001?
input = 0, if the current state is 010?
Ans. 010
Ans. 100

76. A 3 x 8 decoder contains output

from D0 to D7. Which output is
activated high if the input expression
x'yz'?
A. D1
B. D2
C. D4
D. D5
77. A 4-input (D0 - D3) priority encoder
circuit contain 3 output functions (x, y)
pertaining to binary values. What is the
function for the least significant bit x?
A. D2 + D3
B. D1 + D2 + D3
C. D3 + D1D2’
D. D2 + D1’D3

79. 2 to 4 line decoder, made of NAND

gates which input would produce an
output of 1011 from D0 to D3
A. 1XX
B. 001
C. 011
D. 010

78. A 4-input (D0 - D3) priority encoder

circuit contain 3 output functions (x, y)
pertaining to binary values. What is the 80. Under precedence of logical
function for the least significant bit y? operators which is performed last?
A. D2 + D3 Ans. Biconditional
B. D1 + D2 + D3
C. D3 + D1D2’ 81. Which of the ff logical operator is
D. D2 + D1’D3 performed first?
Ans. AND (wala daw sa choices yung
NOT)

Note:
precedence of logical operators -
NOT(Negation), AND(Conjunction),
OR(Disjunction),
IMPLICATION,
BICONDITIONAL(Equivalence)
 Note:
3 laws namely; LAW OF UNION,
DISTRIBUTIVE, and INTERSECTION

82. The expression below is regarded as

(p ^ q) -> (p v q)
Ans. TAUTOLOGY 85. Which of the ff relation from Set A
{integer numbers} is considered as
p q p^q pvq (p ^ q) -> (p v q)
equivalence relation?
A. R = {(a,b) | a > b or a = b }
0 0 0 0 1 B. R = {(a,b) | a b (mod m) with m > 1}
0 1 0 1 1
C. R = {(a,b) | a + b = 3}
D. R = {(a,b) | a < b}
1 0 0 1 1

1 1 1 1 1 Note:
Ref:
83. Which of the propositional https://www.cs.odu.edu/~cs381/cs381
expression is contradiction? content/relation/eq_relation/eq_relati
A. (p ^ q)’ -> p on.html
B. (p -> q)’ -> q’
C. (p -> q)’ -> p Definition(equivalence relation): A
D. (p->(p v q))’ binary relation R on a set A is an
equivalence relation if and only if
84. How many basic theorems and (1) R is reflexive
postulates are used to prove the (2) R is symmetric, and
expression x + xy = x (3) R is transitive.
A. 6
B. 4 Example 1: The equality relation (=) on
C. 5 a set of numbers such as {1, 2, 3} is an
D. 3 equivalence relation.
Example 2: The congruent modulo m Note:
relation on the set of integers i.e. {<a, p ^ p = p : Idempotent Law
b>| a b (mod m)}, where m is a positive p ^ 1 = p or p v 0 = p : Identity Law
integer greater than 1, is an p ^ (pvq) = p or p v (p^q) = p : Absorption
equivalence relation. Law

86. Set A = {integer numbers}, which is

antisymmetric
A. R = {(a,b) | a > b}
B. R = {(a,b) | a + b = 3}
C. R = {(a,b) | a - b = -4}
D. R = {(a,b) | a = b or a = -b}

Note:
Definition(antisymmetric relation): A
relation R on a set A is called
antisymmetric if and only if for any a,
and b in A, whenever <a, b> R , and <b,
a> R , a = b must hold. Equivalently, R is
antisymmetric if and only if whenever
<a, b> R , and a b , <b, a> R . Thus in
an antisymmetric relation no pair of
elements are related to each other.

Example 7: The relation < (or >) on any

set of numbers is antisymmetric. So is
the equality relation on any set of
numbers.

87. Which of the following relations

from Set A = [1,2,3,4] to Set A is
considered transitive?
Ans. {(1,1),(1,2),(2,1)}
90. Determine which of the given
88. A U A’ = U
relations on the set of all integers is an
Ans. Complement Law
antisymmetric relation where (x, y) is
an element of R.
89. p v p = p
A. x is not equal to y
Ans. Idempotent Law
B. x is greater than or equal to y2
C. x is a multiple of y
D. xy is greater than or equal to 1
91. Determine which of the given 95. Registers AX, BX and CX contain the
relations on the set of all integers is an following values respectively: 1234h,
equivalence relation where (x, y) is an 5678h and 9ABCh.
element of R. What is the result of the instruction
A. x is a multiple of y SHRD BX, CX, 8
B. x greater than or equal to y2 A. 9A78h
C. x = y2 B. 9A56h
D. x and y are both negative or both C. 2345h
nonnegative D. BC56h (MICROPROCESSOR BOOK
PAGE 118)
92. Machine code: 0FAC CB08

93.

96. SETNZ AL
If the zero flag indicates an NZ condition
(zero flag is clear), register AL is set to
01H.
94. SHLD AX, BX, 4
Otherwise, AL is set to 00H.
AX= 1234H BX= 5678H
Ans. 2345H Machine Code: 0FA4 D804
97. What is the result of NEG AX if AX
contains FFECh?
Ans. 0014h Machine Code: F7D8h

98. Result of executing RCR AX, CL if CL

contains 2 and AX contains ABCDh
Ans. AAF3 Machine Code: D3D8
99. Result of executing RCL DL, 1; Solution:
cleared flags; DL contains 93h
Ans. 26h Machine Code: D0D2 +7 -> 0 0111
-7 -> 1 1000
100. Machine code ROL BYTE PTR[SI], 1 + 1
Ans. final value = 82H → D004 (1101 1 1001
0000 0000 0100)

101. ROR AX, 1

Ans. 4FA5H Machine Code: D1C8

102. Machine code XOR AX, CX

Ans. 31C8 or 0011 0001 1100 1000

BASE N OPERATIONS

103. 10110 - 01101 using 1’s 106. The 2’s complement representing
complement the value -12 is
Ans. 1001 A. 1110
1’s complement of subtrahend: B. 10100
01101 -> 10010 C. 10011
11 D. 10101
10110
+ 10010 Sign magnitude +12: 0 1100
1 01000 (overflow, add 1 to result) 11
+ 1 1 0011
01001 + 1
If no carry, 1’s complement the ans. and 1 0100 (-12)
place a negative sign to the result
104. Perform the binary division 107. 1st Complement subtraction
1111 0011 ÷ 1001 to obtain the
quotient.
A. 10101
B. 10111
C. 11011
D. 11101

105. Using 2’s complement, what is

the binary equivalent of -7?
A. 1111
B. 1001
C. 1100
D. 1000
108. The binary value 0111 represent a 111. Which of the ff correctly describes
decimal value of 1 in this decimal code the graph
Ans. 8 4 -2 -1 Matrix: abc
a101
Note: b001
For other coding, we replace the 8 4 2 1 c111
with other values. A. Simple directed graph with 3
We know that 0111 in decimal is 7 vertices
because of the common 8 4 2 1 coding. B. Pseudograph with 3 vertices
C. Directed multigraph with 3 vertices
8(0) + 4(1) + 2(1) + 1(1) = 7 D. Simple multigraph with 3 vertices

In this case, we replace it by 8 4 -2 -1.

8(0) + 4(1) - 2(1) - 1(1) = 1

109. The 2-4-2-1 code of 7 is:

Ans. 1101

Note: 112. The adjacency matrix of the graph

We can see that 2 + 4 + 1 will make 7 so is seen below, determine how many
we multiply them by 1. The 2 in the most edges are in the graph.
significant bit has more priority than
the other.

2(1) + 4(1) + 2(0) + 1(1) = 7 Ans. 10

Note: count all the non-zeros to get the
Therefore 7 is 1101 in 2-4-2-1 code.
no. of edges
GRAPH / MATRIX QUESTIONS 113. Give the adjacency matrix of the
graph G {a,b,c,d}, How many number of
110. Determine in-degree in vertex b? paths from a to d has a length exactly
Ans. 5 equal to 4?
0 1 1 0
Matrix: abcd
a0230 1 0 0 1
b1221 1 0 0 1
c2110
d1002 0 1 1 0
Ans. 8
in-degree: add vertically, 5
out-degree: add horizontally, 6
 117. Which of the ff vertex is called a
pendant?

114. The graph is represented by the

Ans. f-1 degree
adjacency matrix below. Determine the
out-degree in vertex d
118. How many pass will it take in order
to sort the single digit array 3 5 4 1 2
using selection sort?
A. 5
B. 4
Ans. 3 C. 6
D. 10
115.
V = {a,b,c,d,e}, Note: For Bubble Sort
E = {(a,b),(a,c),(b,c),(c,d),(c,e),(d,e)} is
classified as?
A. Hamiltonian but not Eulerian
B. neither H or E
C. H and E
D. E but not H (Eulerian cycle but not
Hamiltonian)

116. Given the undirected graph V =

{a,b,c,d,e} with
E = {(a,b).(a,d),(b,c),(c,d),(d,e)} is
classified as?
Ans. Eulerian Path

Note:
Eulerian circuit - visits every edge
exactly once and starts and ends on
the same vertex
Hamiltonian path - visit every vertex
only once
119. Given the following points below, 120. What kind of graph?
what is the longest/shortest route? Ans. eulerian cycle

Gr to SW 113 mi Gr to Kal 56 mi
Gr to Det 147 mi Gr to Tol 167 mi
Kal to SW 137 mi Kal to Det 135 mi
Kal to Tol 133 mi Tol to Det 58 mi
Tol to SW 142 mi Det to SW 98 mi

A. Det- Tol- Kal- GR-Sw – Det -

SHORTEST
B. Det – Tol-Gr-Kal-Sw-Det
C. Det-GR-Sw-Tol-Kal-Det - LONGEST
D. Det-Sw-Tol-GR-Kal-Det

121. What kind of graph? EULERIAN

PATH - 2 ODD VERTICES
122. 125. Simplify the Boolean function to a
minimum number of literals
A B C T1
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

A'(B' + C')
A + BC
A'B + C
ABC + A'B'C'

126. Simplify F(v, w, x, y, z) = Σm (0, 1,

2, 4, 5, 8, 9, 10, 12, 16, 17, 18, 20, 21,
24, 26, 29) using Karnaugh map.
A. v’w’y’ + v’x’z’ + vxz + v’y’z’ + v’x’y’ +
vxy’z
Ans. 8 x 8 B. w’y’ + x’z’ + v’y’z’ + v’x’y’ + vxy’z
C. none of the choices
K-MAP QUESTIONS D. vw’y’+ v’x’z’ + vxz + v’y’z’ + v’x’y’ +
v’xy’z
123. F = xy + x’z express as product of
maxterms 127. 5.What is the canonical form of
Ans. M(0,2,4,5) the simplified function
F = C ‘D + ABC ‘+ ABD ‘+ A ‘B ‘D
124. A. M (0,1,2,3,5,9,11,12,14)
The complement of F = [x(y’z’ + yz)] B. M (1,3,4,5,6,7,9,10,12,14,15)
C. M (0,2,4,6,7,8,10,11,15)
D. M (1,3,5,9,12,13,14)

128. Determine the canonical form of

the simplified Boolean expression
F = x‘y‘z + xy
A. m (0,5,7)
B. m (2,4,7)
C. m (2,3,7)
D. m (1,6,7)
129. Determine the canonical form of 133. Express the following function as
the simplified Boolean expression a sum of minterms: (xy + z)(y + xz)
F=x‘y‘z‘ + xz A. x’yz + xy’z + xyz’ + xyz
A. m (0,5,7) B. x’y’z + xy’z + xyz
B. m (2,4,7) C. x’yz + x’y’z + xyz’+ xyz
C. m (2,3,7) D. x’y’z + xyz’ + x’y’z’
D. m (1,6,7)

130. Determine the canonical form of

the simplified Boolean expression
F2 = xy‘z‘ + x‘y
A. m (0,5,7)
B. m (2,4,7)
C. m (2,3,4)
D. m (1,6,7)

131. Simplify the Boolean function. 134. Reduce the Boolean expression
A B C T W’X(Z’ + Y’Z) + X(W + W’YZ) to 1 literal
A. X
0 0 0 1
B. W
0 0 1 1 C. Z
D. Y
0 1 0 1

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 1 0

Ans. T=A’B’C’+A’B’C+A’BC’

132. Express the function below as a

standard form product of maxterms.
F = xy + x'z
A. (x + y + z)(x + y' + z)(x' + y + z')
B. (x + y + z)(x + y' + z)(x' + y + z)
C. (x' + y)(x + z)(y + z)
D. (x + y + z)(x + y' + z)(x' + y + z)(x' + y
+ z'
135. Simplify the Boolean function to a 139. Which flag is set when the result of
minimum number of literals. an unsigned arithmetic operation is too
A B C T2 large to fit into the destination?
0 0 0 0 Ans. Carry Flag
0 0 1 0
0 1 0 0 140. What circuit technology is
0 1 1 1 preferable in systems requiring low
1 0 0 1 power consumption?
1 0 1 1 Ans. CMOS
1 1 0 1
1 1 1 1 141. This specifies the number of loads
A + BC that output of a gate can drive without
ABC + A'B'C' compromising its performance?
A'(B' + C') Ans. Fan-out
AB + C
142.
Solution:

A\BC 00 01 11 10
0 0 0 1 0
1 1 1 1 1

136. Simplify the Boolean function

F(A,B,C,D) = m(0,2,3,5,7,8,10,11,13,15)

B'C + CD + BD
B'D' + BD + B'C
143. 2.Simulate the given instructions
B'D' + BD + A'C'D
(below) and determine which among
A'B'D' + AB'D' + CD
the choices is correct.
Initially CF=0; AF=0; ZF=0; SF=0; PF=0.
137. A decoder with an enable input
MOV AL, D6
can function as
MOV BL, E5
Ans. Demultiplexer
ADD AL, BL
a. CF=1; AF=1; ZF=0; SF=1; PF=0
138. If the removal of any literal from
b. CF=1; AF=1; ZF=0; SF=0; PF=1
an implicant P results in a product
c. CF=1; AF=0; ZF=0; SF=0; PF=1
term that is not an implicant of the
d. CF=1; AF=1; ZF=1; SF=1; PF=1
function then P is a/an _______
e. None of the choices
Ans. Prime implicant
f. CF=1; AF=0; ZF=0; SF=1; PF=1
144. It is the most significant of the 32- 149. what is a RISC design?
bit designs done by Motorola, Choices:
introduced in 1979 and was [PowerRISC, PowerPC, PowerLaptop,
widely known, had 32-bit registers in its none]
programming model but used 16-bit Ans. PowerPC
internal data paths.
A. MC68000 150.
B. MC68030 MOV AL, AE
C. MC68010 MOV BL, 9A
D. MC68020 SUB AL,BL
Flags: SF=0 CF=0 ZF=0 IF=0
145. Motorola introduced this Ans.
microprocessor in 1978, an ambitious
and thought-through 8-bit design 151. MOV CX, 7, what machine code?
source compatible with their previous Ans.
design and was implemented using
purely hardwired logic. 152. Not included in microprocessor?
A. MC6800 Choices:[General purpose registers,
B. MC6815 control unit, ALU, memory]
C. MC6808 Ans. memory(?), ‘di ko sure kung may
D. MC6809 none sa choices

146. Pentium Note:

Choices: [parallel…,three floating…, U Study parts of a Microprocessor,
and V pipelines…,ten floating..,] Microcontroller, CPU
Ans. U and V pipelines yata
152. BCD 431 packed
146. a state where the data requested Ans. 0100 0011 0001
for processing by a component or
application is not found in the cache Note:
memory. Study BCD packed and unpacked
Ans. Cache miss
153. How many 4 digit binary adder to
147. Pentium create a 4 bit binary multiplier (not sure
Choices:[pipeline, shutdown, halt, may pero basta parang ganyan)
isa pa] Choices:[1,4,3,2]
Ans. Ans.

148. (AB+C) (B+C’D) to minterm

Ans.
154.

When is it false?
Ans. every x, P(x) is true

155. ENIAC
Ans. Large Brain (Great Brain ‘di ko sure
kung meron sa choices, Large brain lang
naaalala ko)

156. Which is not a program transfer

instruction?
Choices:[ADD, CMPS, SHL]
Ans. ADD (aralin nalang lahat ng
program transfer para masagutan ‘to)
 Mofo
Study online at quizlet.com/_58pdti

1. The 2-4-2-1 code of 7 1101 11. A 4-input (D0 - D3) priority encoder circuit C
contain 3 output functions (x, y) pertaining to
2. 2 bit by 2 bit multiplier can be Answer: 2 Half
binary
constructed by using: Adders and 4
values. What is the function for the least
AND gates
significant bit y?
3. A 2 bit by 2 bit multiplier is simply A A. D2 + D3
implemented using which of the following B. D1 + D2 + D3
combinational C. D3 + D1 D2'
circuit? D. D2 + D1' D3
A. 2 Half Adders and 4 AND gates
12. 4 input (D0-D3) priority encoder circuit contain 3 D3 +
B. 2 Full Adders and an OR gate
output (x,y) pertaining to arbitrary values. What is D1D2'
C. 2 Full Adders and 4 AND gates
the function for least significant bit x?
D. One 4 bit binary adder, 2 AND gates
and 1 OR gate 13. 4 input (D0-D3) priority encoder circuit contain 3 D2 +
output (x,y) pertaining to arbitrary values. What is D3
4. The 2's complement representing the 10100
the function for most significant bit x?
value -12
is 14. 4 input (D0-D3) priority encoder circuit contain 3 Answer:
output (x,y) pertaining to arbitrary values. What is D2 +
5. 2 to 4 line decoder, made of NAND gates B
the function for most significant bit y? D3
which input would produce an output of
1011 from D0 to 15. 4. Perform the binary division 111110011 ÷ 1001 to D
D3 obtain the quotient.
a. 10010
1XX b. 10101
001 c. 10111
011 d. 11011
010 e. None of the choices
f. 11101⁸
6. 3. The adjacency matrix of the graph is 10
seen below, determine how many edges 16. 5. How many clock cycles would it take to finish F
are in the graph. seven instructions in an 8-stage non-pipelined
121 processor?
200 a. 14
022 b. None of the choices
c. 24
7. A 3 x 8 decoder contains output from D0 B
d. 54
to D7. Which output is activated high if the
e. 16
input
f. 56
expression x'yz'?
A. D1 17. 6. Determine the total memory access time for a D
B. D2 series of instructions in a system with RAM
C. D4 access time of 105 ns and cache access time of
D. D5 10ns. Assume hit ratio of 0.75.
a. 42.5ns
8. 3x8 decoder D0 to D7 which output is D2
b. 37.5ns
activated high if input x'yz'
c. 38.75ns
9. 4-bit magnitude comparator 4-input OR gate d. 36.25ns
combinational circuit A < B what logic e. 35.75ns
gate? f. None of the choices
10. 4-bit magnitude comparator 4-input AND
combinational circuit A = B what logic gate
gate?
18. 6. V = {a,b,c,d,e}, D 26. 16. What segment register is accessed by the A
E = {(a,b),(a,c),(b,c),(c,d),(c,e),(d,e)} is classified as? instruction MOV AX, [BP]?
A Hamiltonian but not Eulerian; a. Stack Segment
B neither H or E; b. Data Segment
C H and E; c. Extra Segment
D E but not H d. None of the choices
e. Code Segment
19. 7. The equivalent of 0.1010 base 2 in decimal is B
_________. 27. 17. Which is false for r/m C
a. 0.8756 a. r/m register enclosed in brackets
b. 0.6275 b. r/m used for addressing mode
c. 0.5672 c. r/m specifies addressing mode
d. 0.5786 d. Mode = 11; r/m = register field
e. 0.6758
28. 18. The content of a 4-bit register is initially 0110. The B
20. 10 - 1000 gates in a single package: LSI register is shifted 8 times to the right, with the
sequence 10110111 as the serial input. The leftmost bit
21. 11. This processor introduced streaming extensions, E
of the sequence is applied first. What is the content of
with 128-bit registers designed to move large data.
the register after the 6th shift?
a. Pentium 1
a. 0110
b. 80486
b. 1011
c. None of the choices
c. 1101
d. Pentium 4
d. 1110
e. Pentium 3
e. 1001
f. Pentium 2
f. 1010
22. 12. Determine the least number of NAND gate that F
29. 19. The 74LS83 is an example of a 4-bit parallel adder. B
can be used to implement the expression, (AB +
To expand this device to an 8-bit adder, you must
A'B')'(CD' + C'D)
a. Use eight adders with no interconnections
a. 12
b. Use two adders with the carry output of one
b. 10
connected to the carry input of the other
c. 9
c. Use two adders and connect the sum outputs of one
d. 13
bit to the bit inputs of the other
e. 14
d. Use four adders with no interconnections
f. 11
g. 8 30. 20. In stack memory addressing, whenever the data are A
popped from the stack, which bits are removed from
23. 13. Compute for the number of clock cycles of 9 B
the location addressed by SP?
instructions in a superpipeline system.
a. Low-order 8-bits
a. 28
b. No bits are removed from SP but rather on BP
b. 126
c. None of the choices
c. 180
d. Both low-order and high-order 8-bits
d. 22
e. High-order 8-bits
e. None of the choices
f. 16 bits from BP are removed
f. 18
31. 21. The binary equivalent of decimal 1234 is _____? E
24. 14. Determine the bitwise implication of p = 1101011 C
a. 0001 0000 1110 0001
and q = 1011100
b. 0001 0011 0010 0100
a. 0100011
c. 0001 0010 0011 0100
b. 0010100
d. 0010 0100 0110 1000
c. 1011100
e. 0000 0100 1101 0010
d. 1101011
25. 15. If both inputs of a NOR gate is inverted the AND
resulting gate is like the connective _______.
32. 22. This flag is set when the result of an unsigned C 39. 29. The flip-flop _________ table provides the Excitation
operation is too large to fit into the destination value of the next state when the values of the table
a. Zero Flag inputs and the present state are known
b. Parity Flag
40. 30. The execution time for an alu instruction 5 clock
c. Overflow Flag
going from memory to immediate requires how cycles
d. Sign Flag
many clock cycles?
e. Auxiliary Flag
f. Carry Flag 41. 31. Intel introduced cache memory for this B
microprocessor when it was launched. The
33. 23. A processor running in this mode can exploit only D
Western Design Center, Inc (WDC) introduced
the lowest 20 bits of its address bus and is therefore
this microprocessor in 1982 and was used as the
limited to the meager 1MB memory space.
CPU in the Apple IIe and IIc personal
a. Virtual mode
computers.
b. None of the choices
a. IMP-16
c. Protected mode
b. CMOS 8502
d. Real mode
c. MC 6809
34. 24. What circuit technology is preferable in systems A d. TMS 9980
requiring low power consumption?
42. 32. What flag register is not affected by the A
a. CMOS
arithmetic operation ADD?
b. TTL
a. Trap Flag
c. None of the choices
b. Sign Flag
d. RTL
c. Parity Flag
35. 25. It is an addressing mode in the Z80 that uses C d. Zero Flag
absolute jump, one-byte opcode and a 2 byte address
43. 33. What registers are affected by the A and D
a. Immediate Addressing
arithmetic operation,
b. Relative Addressing
XOR AH, FFH
c. Extended Addressing
a. SF
d. Register Direct Addressing
b. TF
e. Implied Addressing
c. DF
f. Register Indirect Addressing
d. PF
36. 26. What is the result of NEG AX if AX contains FFECh? C
44. 34. Intel marketed this microprocessor in April, D
a. 0020H
1972, and was the basis for the famous "Mark-8"
b. F7D8H
computer kit.
c. 0014H
a. 8085
d. None of the choices
b. 8088
e. 2345H
c. 8086
f. 3579H
d. 8008
37. 27. Exclusive-OR (XOR) logic gates can be constructed A
45. 35. The minimal hypothetical microprocessor B
from what other logic gates?
only includes
a. AND gates, OR gates, and NOT gates
a. ALU and set of main registers
b. AND gates and NOT gates
b. ALU and control logic section
c. OR gates and NOT gates
c. Main registers and control logic section
d. OR gates only
d. ALU and segment registers
e. AND gates and OR gates
46. 36. How many clock cycles would it take to A
38. 28. This specifies the number of loads that output of a B
finish seven instructions in an 8-stage non-
gate can drive without comprising its performance
pipelined processor?
a. Output Line
a. 56
b. Fan-out
b. 54
c. None of the choices
c. None of the choices
d. Fan-in
d. 15
e. Input line
47. 37. Which of the following inputs provide a don't care A 55. 45. The Boolean expression.(X')' is an example of which B
in the output y given by the function F(w, x, y, z) in a Law/Theorem?
BCD to excess-of-3 code converter? a. Consensus theorem
a. 1011 b. Involution law
b. 1001 c. Idempotent law
c. 0000 d. Commutative law
d. 0001
56. 46. The 4-bit magnitude comparator combinational A
48. 38. A 3 input XOR can be implemented using how C circuit generates the final output for A = B at what
many 2 x 1 multiplexers? logic gate?
a. 4 a. 4 input AND logic gate
b. 8 b. 4 input OR logic gate
c. 2 c. 4 input XOR logic gate
d. 3 d. 4 input NOR logic gate
49. 39. Express the following function as a sum of C 57. 47. The content of a 4-bit register is initially 0110. The B
minterms: (xy + z)(y + xz) register is shifted 8 times to the right, with the
a. x'y'z + xy'z + xyz sequence 1011 0111 as the serial input. The leftmost bit
b. x'yz + x'y'z + xyz'+ xyz of the sequence is applied first. What is the content of
c. x'yz + xy'z + xyz' + xyz the register after the 6th shift?
d. x'y'z + xyz' + x'y'z' a. 1010
b. 1011
50. 40. Which of the following inputs provide a don't care B
c. 0110
in the output z given by the function F(w, x, y, z) in a
d. 1101
BCD to excess-of-3 code converter?
a. 0110 58. 48. Design a BCD to Excess-3 Code Converter. D
b. 1010 Designate the four input binary variables by the
c. 0100 symbols A, B, C, D, and the four output variables w, x, y,
d. 0010 and z. What is the Boolean expression of the output z
with respect to inputs A, B, C and D?
51. 41. The Boolean expression.(X+Y+Z)' = X'Y'Z' is an C
a. A + B'C
example of which Law/Theorem?
b. C'D' + CD
a. idempotent law
c. A + B(C+D)
b. consensus theorem
d. D'
c. de morgan's law
d. commutative law 59. 49. Determine the essential prime implicants of the B
function F(w, x, y, z) = ∑(0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
52. 42. Using the signed-2's complement format, the A
a. w'x and w'z'
representation of -7 is __________.
b. xz and x'z'
a. 1001
c. xyz' and wy
b. 1111
d. x'yz and w'y'
c. 1000
d. 1100 60. 50. A 3 x 8 decoder contains output from D0 to D7. B
Which output is activated high if the input expression
53. 43. The 4-bit magnitude comparator combinational B
x'yz'?
circuit generates the final output for A < B at what
a. D1
logic gate?
b. D2
a. 4 input AND logic gate
c. D4
b. 4 input OR logic gate
d. D5
c. 4 input XOR logic gate
d. 4 input NOR logic gate 61. 51. This is the time needed by a gate in processing its C
input signals before the output signal can be
54. 44. A race condition happens in an R-S latch when the B
generated
inputs are ____
a. Threshold time
a. R = 0, S = 0
b. Setup time
b. R = 1, S = 1
c. Propagation delay time
c. R = 0, S = 1
d. Hold time
d. R = 1, S = 0
62. 52. Simplify the Boolean function A 70. An algorithm that uses Eulerian Path/Bubble Linear
F(A, B, C, D, E) = ∑(0, 1, 4, 5, 16, 17, Sort to solve uses a Big-O notation of Complexity
21, 25, 29)
71. An algorithm that uses Hamiltonian cycle to logarithmic
a. A'B'D' + AD'E + B'C'D
solve uses a Big-O notation of complexity
b. B'D'E + CD' + ABC'D
c. B'D + A'BD + ABC'E' 72. An algorithm that uses Selection to solve Quadratic
d. BD + B'DE + A'B'C' uses a Big-O notation of

63. 74LS83 is an example 4-bit Two half adders with 73. ARM stands for Advanced
parallel adder to expand to 8-bit the carry output of one RISC
you must connected to the input Machines
of the other 74. ARM stands for A
64. The 74LS83 is an example of a 4- D A. Advance RISC Machines
bit parallel adder. To expand this B. Advance Response Machines
device to an 8-bit adder, you C. Advance RISC Model
must D. Advance Reprogrammable Model
A. use four adders with no 75. AX, BX, CX = 1234H, 5678H, 9ABCH ; result of Answer:
interconnections SHRD BX, CX, 8? BC56
B. use two adders and connect Machine
the sum outputs of one to the bit Code:
inputs of the other 0FAC CB08
C. use eight adders with no
76. Based from order, when PUSHA is applied AX
interconnections.
which register is PUSHED first?
D. use two adders with the carry
output of one connected to the 77. Based from order, when PUSHA is applied DI
carry input of the other which register is PUSHED last?

65. 8088 I/O ad space, number of I/O 4096 78. Based from order, when the instruction D
ports? PUSHA is applied, which of the following
register is
66. The 8088's I/O addressing space D
"PUSHED" last?
contains how many possible
A. CX
input/output ports?
B. AX
A. 1048576
C. SI
B. 4096
D. DI
C. 1024
D. 65536 79. The binary value 0111 represent a decimal 8 4 -2 -1
value
67. 10110 - 01101 using 1's complement 01001
of 1 in this decimal code
68. Addressing mode executes its Register mode
80. The complement of F = [x(y'z' + yz)] F' = x(y+z')
instructions within CPU without the
(y'+z)
necessity of reference memory
for operands? 81. Consider the symbolic logic taken from Lewis I and II
Caroll illustrating how quantifiers are used in
69. a. _____ - fast, easy interface, small STATIC RAM
statements. Which of the following is/are
size (16 bytes per chip) DYAMIC RAM
premises?
b. _____ - high density (256K per NOTE: Both STATIC
I. All lions are fierce
chip), requires numerous and DYNAMIC lose
II. Some lions dont drink coffee
refreshing cycles to retain data. info when turned off
III. Some fierce creatures do not drink coffee

c._____ - retains memory even NVRAM

power is turned off
82. - convert assembly language into machine Assembler 90. Determine the property or properties of the D
code. It takes basic computer instructions and Compiler relation of the set of integers to the set of
converts them into a pattern of bits that the interpreter integers where (x,y) ∈ R if x is a multiple of y.
computer's processor can use to perform basic
operations. a. Symmetric
- convert high level languages (like C, C++) b. Reflexive, antisymmetric, transitive
into machine code c. Reflexive, antisymmetric, symmetric, transitive
- computer program which executes a d. Antisymmetric, transitive
statement directly (at runtime) e. Reflexive, symmetric, transitive
f. Reflexive, symmetric
83. Decimal parallel adder that adds 5 decimal 5
g. Reflexive, transitive
digits requires how many BCD adder stages?
91. Determine which of the given relations on the set A
84. A decimal parallel adder that adds 5 decimal A
of all integers is an antisymmetric relation where
digits requires how many BCD adder stages.
(x, y) is an element of R.
A. 5
B. 6
x is greater than or equal to y2
C. 3
x is a multiple of y
D. 4
xy is greater than or equal to 1
85. Determine in-degree in vertex b? Matrix: a b c 5 x is not equal to y
da0230b1221
92. Determine which of the given relations on the set D
c2110
of all integers is an equivalence relation where (x,
d1002
y) is an element of R.
86. Determine the canonical form of the simplified D x is a multiple of y
Boolean expression F = x'y'z + xy x greater than or equal to y2
a. m (0,5,7) x = y2
b. m (2,4,7) x and y are both negative or both nonnegative
c. m (2,3,7)
93. Developed a single general-purpose chip that Ted
d. m (1,6,7)
could be programmed to carry out a calculator's Hoff
87. Determine the canonical form of the simplified A function.
Boolean expression F=x'y'z' + xz
94. Digital integrated circuits are classified not only digital
a. m (0,5,7)
by their complexity or logical operation, but also logic
b. m (2,4,7)
by the specific circuit technology to which they family
c. m (0,2,3,7)
belong.
d. m (1,6,7)
The circuit technology is referred to as ____.
88. Determine the canonical form of the simplified C
95. Digital integrated circuits are classified not only D
Boolean expression F2 = xy'z' + x'y
by their complexity or logical operation, but also
a. m (0,5,7)
by the specific circuit technology to which they
b. m (2,4,7)
belong. The circuit technology is referred to as
c. m (2,3,4)
____
d. m (1,6,7)
A. none of the choices
89. Determine the equivalent statement of ¬Ǝx B B. CMOS family
P(x). C. TTL family
¬∀x P(x) D. digital logic family
∀x ¬P(x)
96. Direction flag is set to 0 using this instruction. CLD
¬Ǝx ¬P(x)
Ǝx ¬P(x) 97. The direction flag is set to 0 using this instruction. C
A. CLC - clear carry
B. CMC - complement carry
C. CLD - clear direction flag
D. STC - set carry
98. Exclusive-OR (XOR) logic gates can be AND gates, 109. Given the following points below, what is the Shortest
constructed from what other logic gates? OR gates, longest/shortest route? A
and NOT Gr to SW 113 mi Longest
gates Gr to Kal 56 mi C
Gr to Det 147 mi
99. The expression below is regarded as (p ^ q) Tautology
Gr to Tol 167 mi
-> (p v q)
Kal to SW 137 mi
100. Express the following function as a sum of A Kal to Det 135 mi
minterms: (xy + z)(y + xz) Kal to Tol 133 mi
Tol to Det 58 mi
x'yz + xy'z + xyz' + xyz Tol to SW 142 mi
x'y'z + xy'z + xyz Det to SW 98 mi
x'yz + x'y'z + xyz'+ xyz
x'y'z + xyz' + x'y'z a.) Det- Tol- Kal- GR-Sw - Det
101. Express the function below as a standard C b.) Det - Tol-Gr-Kal-Sw-Det
form product of maxterms. F = xy + x'z c.) Det-GR-Sw-Tol-Kal-Det
d.)Det-Sw-Tol-GR-Kal-Det
(x + y + z)(x + y' + z)(x' + y + z') 110. Given the undirected graph V = {a,b,c,d,e} with E Eulerian
(x + y + z)(x + y' + z)(x' + y + z) = {(a,b).(a,d),(b,c),(c,d),(d,e)} is classified as? Path
(x' + y)(x + z)(y + z)
111. Give the adjacency matrix of the graph G 8
(x + y + z)(x + y' + z)(x' + y + z)(x' + y + z')
{a,b,c,d}, How many number of paths from a to d
102. F = xy + x'z express as product of maxterms M(0,2,4,5) has a length exactly equal to 4?
103. fast retrieval? Choices: A 0110
A Static RAM, 1001
B Dynamic RAM, 1001
C ROM, 0110
D NVRAM 112. The graph is represented by the adjacency 3
104. First Commercial 8 bit Intel 8008 matrix below. Determine the out-degree in
vertex d
105. Flag register contains 10000011 on its lower SF and CF
byte which flag registers are set as a result
0230
of executing LAHF instruction?
1221
106. The following is true for r/m except for A 2110
A. r/m are used for addressing modes 1002
B. r/m refers to registers enclosed in
113. The higher byte of the flag register contains 83h. AF
brackets
Which flag registers are cleared as a result of
C. when mod = 11, r/m indicates a register
executing LAHF instruction?
field
D. r/m specifies the addressing mode 114. How many 4-binary adders are needed to 4
create a single digit binary adder?
107. Given a synchronous sequential circuit what 100
is the next state with input = 0, if the current 115. How many additional control reg are activated 5
state is 010? based from Pentium's protected mode

108. Given a synchronous sequential circuit what 010 116. How many base theorems and postulates to 3
is the next state with input = 1, if the current prove x + xy = x
state is 001? 117. How many basic theorems and postulates are D
used to prove the expression x + xy = x
A. 6
B. 4
C. 5
D. 3
118. How many pass will it take in order to sort the B 131. In the game of tic-tac-toe, every game ends D
single digit array 3 5 4 1 2 using selection sort? with one player winning or with a draw. In a
a.) 5 tic-tac-toe tournament, the player merely
b.) 4 counts the number of times they win or draw.
c.) 6 The winner is the player with the larger count.
d.) 10 If a match between player A and player B
consists of 25 games, player A scored 19 and
119. If 8088 has frequency of 4MHz, the time of one C
player B scored 23, how many draws were
T state? [200 ns; 80 ns, 250 ns; 300 ns]
there?
120. If a 2 to 4 line decoder is made of NAND gates, C
which input would produce an output of 1011 a. 10
from D0 to D3? b. 21
A. 010 c. 29
B. 011 d. 17
C. 001
132. INTR flag
D. 1xx
ground
121. If an ASCII of A is used with even parity the 0100
133. Invert carry flag CMP
results is 0001
134. is a memory cache that stores recent Translation
122. If an ASCII of A is used with odd parity, the 1100
translations of virtual memory to physical Lookaside
results is 0001
addresses for faster retrieval buffer
123. If set A of the universal set U which of the D
135. -is a temporary storage of information inside Register
following expression is true?
the CPU. ALU
¬A ∩ U = A
- is a circuit contained in CPU that is used to Memory
A-U=A
perform arithmetic and logical operations
AᴜU=A
- is part of the computer that is used to store
A ⊕ U = ¬A
information permanently or temporarily.
124. If the function v(w+x+y)z would be implemented Six
136. It is an instruction used to preserve the C
using NOR gates? NOR
contents of the outer loop counter.
gates
A. LOOP
will
B. PUSH
be
C. PUSH and POP
used
D. POP
125. These instructions are used to preserve the PUSH
137. It is considered as a system signal used in C
contents of the outer loop counter and
troubleshooting techniques for 8088
POP
hardware
126. Instruction that sets carry flag to 1 STC architecture.
127. INT AX, DX Read A. DEN
from B. INTR
DX , C. HLDA
write D. ALE
to AX 138. It is the standard bus connector agreed upon B
128. Intel introduced cache memory for this CMOS by the PC business comprising of 62 pins
microprocessor when it was launched. The 8502 found in
Western Design Center, Inc (WDC) introduced this early PC motherboards that allow expansion
microprocessor in 1982 and was used as the CPU with the 8088 microprocessor.
in the Apple IIe and IIc personal computers. A. SATA connector
B. ISA connector
129. Intel's server and workstation powerhouse. B
C. RS232C connector
Choices:
D. SCSI connector
A Celeron
B Xeon
130. Internal high speed memory Cache
139. Lower byte of flag reg = 83H. Which flag SF 151. A parity bit is used in error detecting codes, if C
registers are set as a result of LAHF an ASCII of A is used with even parity the result
instruction? is
A. 1100 0001
140. The lower byte of the flag register A
B. 1101 0100
contains 83h. What is the result of an
C. 0100 0001
LAHF instruction?
D. 0101 0100
A. AH = 83h
B. AX = 83h 152. A parity bit is used in error detecting codes, if A
C. AL = 83h an ASCII of A is used with odd parity the result
D. all the flags are set to 83h is
A. 1100 0001
141. The lower byte of the flag register A
B. 0101 0100
contains 83h. Which flag registers are
C. 0100 0001
cleared as a result of
D. 1101 0100
executing LAHF instruction?
A. PF 153. A parity bit is used in error detecting codes, if 0101
B. SF an 0100
C. none of the choices ASCII of T is used with odd parity the result is
D. CF
154. A parity bit is used in error detecting codes, if B
142. The lower byte of the flag register D an ASCII of T is used with odd parity the result is
contains 83h. Which flag registers are set A. 0100 0001
as a result of B. 0101 0100
executing LAHF instruction? C. 1101 0100
A. PF D. 1100 0001
B. ZF
155. The ____ part specifies the addressing mode for A
C. AF
the selected instruction
D. SF
a. MOD
143. Machine code for LAHF 9F b. Addr-low
c. REG
144. Machine code for SAHF 9E
d. R/M
145. Machine code ROL BYTE PTR[SI], Answer:
156. Perform the binary division 1111 0011 ÷ 1001 to C
final value =
obtain the quotient.
82H → D004 -
A. 10101
1101 0000
B. 10111
0000 0100
C. 11011
146. Machine code XOR AX, CX Answer: 31C8 D. 11101
or 0011 0001
157. Prevent changing the location POPA which SP or
1100 1000
register is not loaded with data ESP
147. Master slave D-flip flop is similar to a a change in
158. A processor running in this mode can exploit Real
synchronous edge triggered flip flop, output is
only the lowest 20 bits of its address bus and is mode
therefore it should have the ff behavior activated by a
therefore limited to the meager 1MB memory
except? clock pulse.
space.
148. Memory of 8 bit? Choices: [A 16kB, B 8kB, A
159. A product term where in which all the variables D
C 64kB]
appear once, rather complemented or
149. mm = __ is automatically used for direct 00 uncomplemented is called __________
addressing A. maxterm
150. P^P = P or PvP = P Idempotent B. POS
law C. SOP
D. minterm
160. Product term wherein which all variables appear minterm
once rather complement or uncomplemented
161. -Pushes all registers to the stack PUSHA 170. SHLD AX, BX, 4 Answer: 2345H
-push data onto stack PUSH Machine Code:
-Push word onto stack PUSHW 0FA4 D804
-Push double word onto stack PUSHD
171. SHLD AX, BX, 4 AX = 1234h BX = 5678h 2345h
-push all registers to stack (60) PUSHA
Order: AX, CX, DX, BX, SP, BP, SI, DI PUSHF 172. Signal that has I/O clk CLK
-Push flags onto stack (9C) 173. Simplify F(v, w, x, y, z) = Σm (0, 1, 2, 4, 5, B
162. Race condition in R-S Latch R =1 S=1 8, 9,
10, 12, 16, 17, 18, 20, 21, 24, 26, 29) using
163. Reduce the Boolean expression W'X(Z' + A
Karnaugh map.
Y'Z) + X(W + W'YZ) to 1 literal
A. X
a. v'w'y' + v'x'z' + vxz + v'y'z' + v'x'y' +
B. W
vxy'z
C. Z
b. w'y' + x'z' + v'y'z' + v'x'y' + vxy'z
D. Y
c. none of the choices
164. Refer to the behavior of synchronous C d. vw'y'+ v'x'z' + vxz + v'y'z' + v'x'y' +
sequential circuit below. Assume that the v'xy'z
states are
174. Simplify F(v, w, x, y, z) = Σm (0, 1, 2, 4, 5, B
identified as the combination ABC. What
8, 9, 10, 12, 16, 17, 18, 20, 21, 24, 26, 29)
is the complement of the next state for
using Karnaugh map.
an input of 1, if
v'w'y' + v'x'z' + vxz + v'y'z' + v'x'y' +
the current state is 001?
vxy'z
A. 010
w'y' + x'z' + v'y'z' + v'x'y' + vxy'z
B. 011
none of the choices
C. 101
vw'y'+ v'x'z' + vxz + v'y'z' + v'x'y' + v'xy'z
D. 110
175. Simplify the Boolean function B
165. Registers AX, BX and CX contain the D
F(A,B,C,D) = m(0,2,3,5,7,8,10,11,13,15)
following values respectively: 1234h,
5678h and 9ABCh.
B'C + CD + BD
What is the result of the instruction SHRD
B'D' + BD + B'C
BX, CX, 8?
B'D' + BD + A'C'D
A. 9A78h
A'B'D' + AB'D' + CD
B. 9A56h
C. 2345h 176. Simplify the Boolean function to a A
D. BC56h minimum
number of literals
166. Result of executing RCL DL, 1; cleared Answer: 26h
A B C T1
flags; DL contains 93h Machine Code:
0001
D0D2
0011
167. Result of executing RCR AX, CL if CL Answer: AAF3 0101
contains 2 and AX contains ABCDh Machine Code: 0110
D3D8 1000
1010
168. ROR AX, 1 Answer:
1100
4FA5H
1110
Machine Code:
D1C8
A'(B' + C)
169. Set A = {integer numbers}, which is A A + BC
antisymmetric A'B + C
a. R = {(a,b) | a > b} ABC + A'B'C'
b. R = {(a,b) | a + b = 3}
c. R = {(a,b) | a - b = -4}
d. R = {(a,b) | a = b or a = -b}
177. Simplify the Boolean function to a minimum A 182. There exists x not P(x) there is an x for
number of literals. which P(x) is
A B C T2 false
0000
183. This input is used to force the Pentium A20M
0010
to limit addressable memory to 1 Mb to
0100
emulate the memory space of the
0111
8086.
1001
1011 184. This is the time needed by a gate in propagation
1101 processing its input signals before the delay time
1111 output signal can be
generated
A + BC 185. This method of storing 16-bit numbers Little Endian
ABC + A'B'C' in memory, wherein the lower byte is
A'(B' + C') already read/write to the lower
AB + C memory address
178. Simulate the given instructions (below) and F 186. Type of RAM that changes during B
determine which among the choices is correct. regular interval
Initially CF=0; AF=0; ZF=0; SF=0; PF=0. Choices: [a Static RAM, b Dynamic
MOV AL, D6 RAM, c ROM, d NVRAM]
MOV BL, E5
187. A U A' = U Complement
ADD AL, BL
Law
188. Under precedence of logical operators Biconditional
a. CF=1; AF=1; ZF=0; SF=1; PF=0 which is performed last?
b. CF=1; AF=1; ZF=0; SF=0; PF=1 189. Understand the code C
c. CF=1; AF=0; ZF=0; SF=0; PF=1 Choices: [A Interpreter,B Compiler, C
d. CF=1; AF=1; ZF=1; SF=1; PF=1 Assembler, D Debugger]
e. None of the choices
f. CF=1; AF=0; ZF=0; SF=1; PF=1 190. Using 2's complement, what is the 1001
binary equivalent of -7?
179. Standard bus connector agreed by PC bus ISA
connector agreed upon by the PC business connector 191. Using the signed-2's complement B
comprising of 62 pins found in early PC format, the representation of -7 is
motherboards that allow expansion with the __________.
8088 A. 1111
microprocessor B. 1001
C. 1100
180. Suppose the universe of discourse of the A D. 1000
propositional function P(x, y) consists of pairs
x and y, where x is (1, 2, 3) and y is (1, 2, 3). 192. Vertex F Pendant
Represent the proposition ∀y P(1, y). 193. -visits every edge exactly once and Eulerian circuit
P(1,1) ˄ P(1,2) ˄ P(1,3) starts and ends on the same vertex Hamiltonian path
P(1,1) v P(1,2) v P(1,3) - visit every vertex only once
P(1,1) ˄ P(1,2) v P(2,3)
194. What does the command IN AL, DX Answer: IN AL,
P(1,1) v P(2,2) v P(3,3)
mean? DX : Input byte
P(1,1) v P(2,1) v P(3,1)
from I/O port in
P(1,1) ˄ P(2,1) ˄ P(3,1)
DX into AL
181. System signal used in troubleshooting INTR
195. What gate comes before/after the A
techniques for 8088 hardware architecture?
decoder in a majority voting circuit?
Choices: [A AND, B OR, C XOR gate]
196. What is the canonical form of the C 206. Which of the ff is a bit manipulation instruction? B
simplified function F = C 'D + ABC '+ ABD a. SHL DL, 2
'+ A 'B 'D a. M (0,1,2,3,5,9,11,12,14) b. Any
b. M (1,3,4,5,6,7,9,10,12,14,15) c. ROL AX,1
c. M (0,2,4,6,7,8,10,11,15) d. NOT AL
d. M (1,3,5,9,12,13,14)
207. Which of the ff logical operator is performed And
197. What is the highest privilege (RPL) in Answer: 00 first?
protected mode? *note: 00 -
208. Which of the ff relation from Set A {integer B
highest
numbers} is considered as equivalence relation?
11- lowest
a. R = {(a,b) | a > b or a = b }
198. What is the result of NEG AX if AX Answer: b. R = {(a,b) | a b (mod m) with m > 1}
contains FFECh? 0014h c. R = {(a,b) | a + b = 3}
Machine d. R = {(a,b) | a < b}
Code: F7D8h
209. Which of the ff vertex is called a pendant? Leaf
199. What law: p^p = p or p v p = p Idempotent
210. Which of the following cannot be found in A
Law
microprocessor/ microcontroller/ CPU
p ^ 1 or p v 0 identity law
Choices:
absorption
A Memory,
p ^ (pvq) = p or p v (p^q) = p law
B ALU,
200. What law? Complement C Register
P U -P = U law
211. Which of the following is a bit manipulation A
201. What segment is used for store destination A instruction?
string? A. any of the choices
a. ES B. NOT AL
b. Any C. SHL DL, 2
c. DS D. ROL AX, 1
d. CS
212. Which of the following is a logical instruction? TEST
202. Where will you know if it is in 16 bit or 32 B
213. Which of the following is a logical instruction? A
bit? Choices: A. AV,
A. TEST
B. D,
B. ADC
C. G,
C. SHL
D. RPL
D. CMP
203. Which is a valid conclusion? Choices: D
214. Which of the following is BIT MANIPULATION? SHL
(a) All hummingbirds are richly colored
Choices:
(b) No large birds live on honey
A SHL
(c) Birds that do not live on honey are dull
B OR
in color
C AND
(d) Hummingbirds are small
215. Which of the following relations from Set A = {(1,1),
204. Which is used as the medium of i/o port
[1,2,3,4] to Set A is considered transitive? (1,2),
communication between the processor
(2,1)}
and the outside world.
216. Which of the propositional expression is D
205. Which of the ff correctly describes the C
contradiction?
graph Matrix: a b c a 1 0 1 b 0 0 1
a. (p ^ q)' -> p
c111
b. (p -> q)' -> q'
a. Simple directed graph with 3 vertices
c. (p -> q)' -> p
b. Pseudograph with 3 vertices
d. (p->(p v q))'
c. Directed multigraph with 3 vertices
d. Simple multigraph with 3 vertices
217. Which technique does the Pentium Pro employs where the processor looks ahead into the instruction stream Speculative
pipeline can be kept busy? execution
218. Who made calculator into computer? Charles
Babbage
COE121X – SET THEORY RED – MULTIPLES OF 2 – 27
In a ward at a teaching hospital, there are 25 doctors, 35 females, and GREEN – MULTIPLES OF 5 - 7
19 supervisors. Amongst the females are 10 doctors and 11 BLUE – MULTIPLES OF 3 - 14
supervisors; three of the supervising females are themselves doctors. CYAN – MULTIPLES OF 5 AND 3 – 3
Of the doctors, 15 are not supervisors. The hospital is considering an MAGENTA – MULTIPLES OF 2 AND 3 – 13
affirmative action program and needs to answer the following YELLOW – MULTIPLES OF 2 AND 5 – 7
questions: WHITE – MULTIPLES OF 2, 3 AND 5 – 3
BLACK (K) – NOT SELECTED – 26

Doctors Of the 130 students who took a discrete mathematics examintation,

8 90 correctly answered the first question, 60 correctly answered the
second question, and 50 correctly answered both questions. How
many students:
7 7 a.) correctly answered either the first or second question?
3
90 + 60 – 50 = 100
17 8 1
Females Supervisors b.) did not answer either of the two questions correctly?
130 – 100 = 30
U
c.) answered either the first or the second question correctly, but not
a.) How many male supervisors are there? 8 both? 40 + 10 = 50
b.) What percentage of the supervisors are female?
(11/19)*100% = 57.89% d.) answered the second question correctly, but not the first? 10
c.) How many people are employed as doctors or supervisors? 34
e.) missed the second question? 30 + 40 = 70
In a university, there are 250 freshmen who study calculus, 100 who
study discrete mathematics and 40 who study both subjects. What is
the total number of students taking calculus or discrete mathematics? FIRST SECOND
310
40 50 10

DISCRETE
CALCULUS
MATHEMATICS 30 U
210 40 60 Table 3.10 gives the number of homicides, by city, in Canada for 2012
and 2013. List the elements of each set.
Table 3.10 Homicides by city, Canada, 2012
and 2013
U Cities 2012 2013
Toronto 81 79
Montreal 47 43
Alice circles in red ink all of the even natural numbers from 1 to 100.
Winnipeg 33 26
Bob circles in blue ink all of the multiples of 3. Eve circles in green ink Vancouver 37 42
all of the multiples of 5. How many of the numbers are circled exactly: Hamilton 6 15
a.) once – 48 Ottawa 7 9
b.) twice – 23 Kingston 0 1

1 2 3 4 5 6 7 8 9 10 a.) The set of cities where the number of homicides increased from
11 12 13 14 15 16 17 18 19 20 2012 to 2013
21 22 23 24 25 26 27 28 29 30 A = {Vancouver, Hamilton, Ottawa, Kingston}
31 32 33 34 35 36 37 38 39 40
41 42 43 44 45 46 47 48 49 50 b.) The set of cities that had more than 30 homicides in 2012 or 2013
51 52 53 54 55 56 57 58 59 60 B = {Toronto, Montreal, Winnipeg, Vancouver}
61 62 63 64 65 66 67 68 69 70
71 72 73 74 75 76 77 78 79 80 c.) The set of cities that had less than 9 homicides in 2012 and 2013
81 82 83 84 85 86 87 88 89 90
C = {Kingston}
91 92 93 94 95 96 97 98 99 100
K – NOT CIRCLED R+G = Y
d.) The set of cities that had a decrease of 3 homicides or more from
RGB – CIRCLED ONCE R+B = M
CMY – CIRCLED TWICE G+B = C 2012 to 2013
W – CIRCLED THRICE R+G+B = W D = {Montreal, Winnipeg}
There are twenty-five dogs at the dog show. Twelve of the dogs are In one day, 100 patients visited an emergency room at a hospital. The
black, eight of the dogs have short tails, and fifteen of the dogs have number of patients that visited the emergency room that resulted in
long hair. There is only one dog that is black with a short tail and long neither an X-rays nor a referral to a specialist is 34. Of those going to
hair. Three of the dogs are black with short tails and do not have long the emergency room, 36 patients were referred to specialist and 40
hair. Two of the dogs have short tails and long hair but are not black. patients required an X-rays. How many patients required both an X-
If all of the dogs in the kennel have at least one of the mentioned rays and a referral to a specialist? 10
characteristics, how many dogs are black with long hair but do not
have short tails?

X-RAY REFERRAL
Black
8-x 30 10 26

x 3 34 U
1
12 - x 2
2
Long Short
Hair Tail
U

25 = (8 – x) + (12 – x) + 2 + x + 2 + 3 + 1
x = 8 + 12 + 2 + 2 + 3 + 1 – 25
x=3

Suppose that 60 customers buy a desktop, 40 buy a laptop, and 30

buy both a desktop and a laptop. How many will buy a desktop or a
laptop but not both?

DESKTOP LAPTOP

30 30 10

30 + 10 = 40

To join a certain student club, members must either be a business

major, or an accounting major or both. Of the 20 members in this
club, 16 are business majors, and 10 are accounting majors. How
many members in this club are both business and accounting majors?
6

Business Accounting
Major Major

10 6 4