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32-Bit Adder: The Object of This Project To Implement 32-Bit Adder in FPGA and Simulate

This document outlines the steps to implement a 32-bit adder in an FPGA and simulate it. It includes creating a new project, defining ports, writing the adder code, synthesizing, analyzing the RTL, implementing in FPGA, simulating, and providing a project schedule. The adder code adds two 32-bit inputs and outputs the sum. The simulation code instantiates the adder component and applies different input values to test it works as expected.

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ahmed
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66 views11 pages

32-Bit Adder: The Object of This Project To Implement 32-Bit Adder in FPGA and Simulate

This document outlines the steps to implement a 32-bit adder in an FPGA and simulate it. It includes creating a new project, defining ports, writing the adder code, synthesizing, analyzing the RTL, implementing in FPGA, simulating, and providing a project schedule. The adder code adds two 32-bit inputs and outputs the sum. The simulation code instantiates the adder component and applies different input values to test it works as expected.

Uploaded by

ahmed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ECE 462 MIPS Project SPRING 2020

32-bit Adder
The object of this project to implement 32-bit adder in FPGA and simulate

1- Implementation

1.1 New Project

1.2 RTL Project

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ECE 462 MIPS Project SPRING 2020

1.3 Choose Device

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ECE 462 MIPS Project SPRING 2020

1.4 Port definition

1.5 Adder code

library IEEE;
use IEEE.std_logic_1164.all;
Ctrl+ C
use IEEE.std_logic_arith.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adder_32 is
port (
x,y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end entity;

architecture beh of adder_32 is


begin
z <= x+y;
end beh;

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ECE 462 MIPS Project SPRING 2020

CTRL+V

1.6 SYNTHESIS

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ECE 462 MIPS Project SPRING 2020

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ECE 462 MIPS Project SPRING 2020

1.7 RTL ANALYSIS

1.8 Adder Implementation in FPGA

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ECE 462 MIPS Project SPRING 2020

1.9 Project summary

1.10 POWER

2. Simulation

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ECE 462 MIPS Project SPRING 2020

2.1 Add Simulation to project

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ECE 462 MIPS Project SPRING 2020

2.2 Simulation Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.Numeric_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity adder_32_tb is
end;
architecture bench of adder_32_tb is
component adder_32 is
port (x,y: in std_logic_vector(31 downto 0);
z: out std_logic_vector(31 downto 0)
);
end component;
signal x : STD_LOGIC_vector(31 downto 0);
signal y : STD_LOGIC_vector(31 downto 0);
signal z : STD_LOGIC_vector(31 downto 0);
begin
uut: adder_32 port map( x => x, y => y, z => z);
stimulus : process
begin
x <= "00000000000000000000000000000000";
y <= "00000000000000000000000000000000";
wait for 10 ns;
x <= "00000000000000000000000011111111";
y <= "00000000000000000000000000000000";
wait for 10 ns;
x <= "00000000000000000000000011101001";
y <= "00000000000000000000000010111011";
wait for 10 ns;
x <= "00000000000000000000000011111110";
y <= "00000000000000000000000011011101";
wait;
end process;
end;

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ECE 462 MIPS Project SPRING 2020

2.3 Run Simulation

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ECE 462 MIPS Project SPRING 2020

code Submission due


Adder.vhd 15-4-2020
Alu.vhd
alu_control.vhd
Control.vhd
instruction_memory.vhd 6-5-2020
Instructions.txt
Main.vhd
memory.vhd 22-4-2020
mux,vhd
pc.vhd
registers.vhd 29-4-2020
Shifter.vhd
sign_extend.vhd

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