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Light load stability improvement for single-phase boost PFC rectifier using
input current self-control technique

Conference Paper · September 2011

DOI: 10.1109/COBEP.2011.6085190

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 LIGHT LOAD STABILITY IMPROVEMENT FOR SINGLE-PHASE BOOST
PFC RECTIFIER USING INPUT CURRENT SELF-CONTROL TECHNIQUE
André De Bastiani Lange and Marcelo Lobo Heldwein
Federal University of Santa Catarina UFSC
Electrical Engineering Department / Power Electronics Institute - INEP
P.O: Box 5119 - 88040-970 - Florianpolis-SC, BRAZIL
Phone: +55(48)3721-9204 / Fax: +55(48)3234-5422
[email protected], [email protected]

Abstract - This work presents a stability evaluation (P-type) compensator with gain KI , which is determined by an
for a single-phase boost PFC converter employing digitally output DC-link voltage controller, is included between the in-
implemented input current self-control to achieve close to put current sensing and the PWM modulator. The relationship
unity power factor. Both analog and digital approaches for between input voltage and input current is then given by
the proportional compensator are studied and the effects
of transport delay found in digital controllers are consid- V̂
iin = · sin (ω g · t + δ) (1)
ered. It is verified that the use of a digital proportional KI · Vo
controller may lead to system instabilities at light loading where:
conditions. The replacement of the proportional compen-
iin - Input current.
sator with an adaptive lag compensator is proposed. This
enables light load stability, while being straightforward to V̂ - Input voltage peak value.
implement. Experimental verification is presented based KI - Compensator gain.
on a 500 W lab-prototype. Vo - Output voltage, assumed to be constant.
ωg - Grid frequency.
t - Time.
Keywords – boost, PFC, current self-control, light load δ - Phase displacement between input voltage and input
stability current.
I. INTRODUCTION
Previous works have shown that the use of a simple propor-
Input current self-control used in single-phase boost-type
tional compensator in this technique yields very good results
PFC converters has been proposed and analysed in [1–4]. This
in terms of harmonic distortion. The implementation with a
technique has been originally implemented through analog
P-type controller is simple and straightforward either through
electronics. Cost reduction by eliminating the input voltage
analog electronics or with microcontrollers (DSPs, DSCs, FP-
sensor and a dynamic model that describes the large signal be-
GAs and the like). However, practical experiments demon-
haviour of the converter are within the advantages of this tech-
strate that the current control loop stability is affected by the
nique in comparison with conventional current mode control
transport delays which are inherent to the digital control pro-
based schemes [5]. Fig. 1 shows a single-phase boost rectifier
cessing. This fact prevents a PFC converter from working re-
using the typical implementation for input current self-control
liably when subjected to light load conditions - an issue that
to perform power factor correction (PFC).
has not been addressed in previous literature.
Input current control is accomplished by making the com-
This work uses linear control frequency domain analysis
plementary duty cycle for the switch directly proportional to
to study the effects of transport delay in the stability of in-
the current sensor output signal. In other words, a proportional
put current digitally self-controlled system as function of the
converter processed power. Furthermore, novel compensator
structure and controller design procedure are proposed to ex-
Lb
tend the load range for stable operation. The analysis and pro-
+ posals are experimentally verified in a 500 W prototype.
iin + S
vin vab a vo
b
− − II. CURRENT CONTROL LOOP STABILITY ANALYSIS
PWM WITH A PROPORTIONAL COMPENSATOR
d0 WITHOUT TRANSPORT DELAY

KI Voltage
The basic current control loop scheme for the current self-
controller control technique in a boost-type PFC converter is shown in
Vo ∗ Fig. 2, where:
Vin - Input voltage.
Fig. 1. Typical single-phase boost PFC rectifier implementation Vab - Local average value of the converter’s switched
employing the input current self-control technique. input voltage over a switching period.
 G (s ) and the argument for L(jω) becomes:
VLb (s) 1
Vin (s) s ·Lb Iin (s)
π 3
arg{L(jω)} = −− · ω · Ta . (6)
2 2
Vab (s)
D 0 ( s)
Expressions (5) and (6) cause the system phase to linearly
Vo C (s ) decay with respect to frequency. Consequently, the phase mar-
gin for the system now depends on its bandwidth (open loop
Fig. 2. Block diagram of self-control strategy assuming a constant zero cross frequency) which is in turn related to the compen-
output voltage Vo . sator gain, as shown in (3). Substituting ω in (6) by ω 0 , from
(3) the value for KI that brings the system to its stability limit
is determined. This occurs when arg{L(jω 0 )} = −π. Con-
VLb - Average of voltage across inductor over a switching sequently, the maximum compensator gain for theoretical sta-
period. bility is given by:
Vo - Output voltage, assumed to be constant.
Lb - Boost inductor value. π Lb
Kmax = · (7)
G(s) - Plant transfer function. 2 Vo · Ta
C(s) - Compensator transfer function. Since there is a close relation between compensator gain
D0 - Complement of the duty-cycle. and input current amplitude as shown by (1), one can easily
Iin - Average of input current over a switching period. determine the minimum processed power Pmin for stable op-
eration, i.e.
Assuming that C(s) is a proportional compensator with
gain KI and no transport delay, the system’s open loop trans- 3 V̂ 2
Pmin = · (8)
fer function is given as 2π Lb · fa

KI · Vo where fa is the sampling frequency.

L(s) = . (2) Indeed it is good practice to leave a reasonable phase mar-
s · Lb
gin for proper operation during disturbances and parameters
The system’s cut-off frequency ω 0 and the argument for variations and, thus, avoiding undesirable high frequency os-
L(jω) are given respectively by (3) and (4). cillations on input current.
KI · Vo A single-phase boost PFC rectifier simulation with the
ω0 = (3) following√parameters: Prat = 500 W, Lb = 500 µH,
Lb
V̂ = 127 2 V, Vo = 250 V, fs = 50 kHz and fa = 100 kHz
π
arg{L(jω)} = − (4)
2 10
This implementation there brings no relationship between vin vo
30 30
arg{L(jω)} and the system’s cut-off frequency, thus making 5
the system stable with a 90◦ phase margin for any loading con-
0 iin
ditions. This would be the case for the self-control technique
hiin iTs
implemented using only analog components and high switch- -5
ing frequency where the time delay in the compensator and
PWM modulator operation are negligible. However, if one -10
0.1 0.11 0.12 0.13 0.14 0.15
chooses to implement the system controller using digital sig- Time (s)
nal processing or other methods that require the input current (a)
to be sampled at discrete time intervals and/or a PWM modu- 10
lator that does not instantaneously update its output, the time vin vo
30 30
delays inserted in the control system must be considered. 5

0
iin
III. CURRENT CONTROL LOOP STABILITY ANALYSIS -5 hiin iTs
WITH DIGITAL IMPLEMENTATION
-10
For a system which samples the input current at twice the 0.1 0.11 0.12 0.13 0.14 0.15
switching frequency and always waits for the beginning of the Time (s)
next half modulation period to update the duty-cycle, the trans- (b)
port delay is equal to the sampling period Ta multiplied by
3/2 [6]. Therefore, the open-loop transfer function for this Fig. 3. Simulation results of a boost PFC rectifier with input current
self-control employing a P-type compensator and considering
system is approximated with
transport delays inherent to a digital control implementation. The
KI · Vo − 3 ·Ta ·s results show that the system is unstable at reduced load levels: (a)
L(s) = ·e 2 (5) 65% load (stable); and, (b) 60% load (unstable).
s · Lb
is considered for validating equation (8). With the given pa- G (s )
Vin (s) VLb (s) 1 Iin (s)
rameters, Pmin is found to be 308 W, which is equivalent to s ·Lb
62% of the converter’s rated power.
Fig. 3 shows simulation results for operation slightly above
and slightly under 62% of full power, where hiin iTs repre- C 1 (s )
Vab (s)
sents the local average of input current over a switching pe- s·Tp ·Krat
s·Tp +1
riod. The system becomes unstable when maintaining output
D 0 ( s)
voltage regulation for a load which drains less than Pmin , thus Vo
C 2 (s )
preventing proper operation at light loads. 1
s·Tp +1 Kreg
IV. PROPOSED COMPENSATOR DESIGN
Fig. 5. Block diagram of the input current self-control strategy
This section proposes the employment of an adaptive lag using the proposed compensator.
compensator in place of the original proportional compen-
sator, with a transfer function given by

s · Krat · Tp + Kreg 0
C(s) = , (9)

Magnitude (dB)
s · Tp + 1 P = 20% · Prat
-5
where 40%
-10
60%
V̂ -15 80%
Krat = . (10) 100%
Iˆin,rat · Vo
-20
This compensator presents a frequency response as shown 30
in Fig. 4, with the high frequency gain equal to Krat and the
Phase (deg)

0 100%
low frequency gain equal to Kreg . The pole frequency fp in 80%
1 60%
Hz is at 2π·T and the zero frequency fz is given by 40%
p -30 20%
Kreg
fz = · fp . (11) -60 2 3 4
Krat 10 10 10
Frequency (Hz)
The output voltage regulation is achieved by varying only
the compensator’s low frequency gain, yielding similar results
Fig. 6. Frequency response for the proposed compensator design
to the variation of KI in the case of a proportional compen- with various loading conditions.
sator. However, being able to vary Kreg from (9) in real time
would mean having to recalculate the compensator’s coeffi-
cients at each instant.
A simpler way of varying this parameter is obtained by de-
composing C(s) into partial-fractions. Thus, This leads to the implementation shown in Fig. 5, where
Krat and Tp are fixed parameters of the compensators and the
s · Tp · Krat Kreg Kreg gain is adaptively varied by the output voltage control
C(s) = + . (12) loop just as it is with the original P-type controller gain KI .
s · Tp + 1 s · Tp + 1
Based on the proposed compensator, Fig. 6 shows a Bode
diagram of C(s) for different loads applied to the former ex-
20 log Kreg ample converter, where Krat is kept fixed and Kreg is com-
puted for various processed powers. For the specific case
Magnitude

where P = Prat there is a complete cancellation between

(dB)

the pole and the zero of the compensator, resulting in a pure

20 log Krat proportional controller. As processed power decreases below
rated power, the zero moves away from the pole, increasing
Frequency (Hz) low frequency gain while causing little change in the open-
0 loop transfer function high frequency behaviour.
Fig. 7 shows the available phase margin at various power
Phase
(deg)

levels for the same converter. It should be noticed that light

load stability has been improved as the phase margin is kept
-90 positive down to 15% of rated power.
Simulation results for the example converter are presented
fp fz Frequency (Hz) in Fig. 8. The results confirm that the converter operates stably
at less than half of the load that makes it unstable with the
Fig. 4. Bode diagram for the lag compensator given by (9) original P-type compensator in a digital implementation.
 40
s1
30
Lb
Phase margin (deg)

+
20 + vo
vin iin vab a b −
−
10
s2
0

-10 Fig. 9. Boost-type PFC rectifier used in experimental results [7].

-20
0 20 40 60 80 100
Load (% of rated power) VI. EXPERIMENTAL RESULTS
Fig. 7. Phase margin as a function of load power for the system
current control loop using the proposed compensator. Experimental results were obtained by implementing the
proposed controller in a 500 W prototype with the topology
4 shown in Fig. 9 [7] supplying a resistive load. A second-order
vin vo differential mode input EMC filter is included in the proto-
2 80 80
type. Boost inductor current waveforms were acquired with
0
an oscilloscope in high resolution mode with sufficient points
iin
to display the local average value of iin . Stability of the input
hiin iTs
-2 current control loop is analyzed as a function of the converter
processed power. Thus, conversion losses were considered to
-4 be part of the load.
0.1 0.11 0.12 0.13 0.14 0.15
Time (s)
Fig. 8. Simulation results of a boost PFC rectifier with input current s1 s2 iin vo
self-control employing the proposed compensator and considering
transport delays inherent to a digital control implementation. The Signal interface
Gate drivers
results show that the system is stable at 20% load. / conditioning

PWM ADC
V. FURTHER IMPROVING SYSTEM STABILITY (a) 1–d(t)
i in
Perfect synchronization between switching and sampling
process removes the need for a low-pass filter to eliminate in- vo
KI
put current ripple and allows an automatic reconstruction of Voltage _
the average value of the input current [6]. Nevertheless, ana- 1/x Vo *
compensator eV +
log low-pass filtering is typically used in current sensing cir-
cuitry to increase noise immunity. This means an additional
phase lag is introduced to the system’s open loop frequency s1 s2 iin vo
response, which reduces phase margin.
Equation (13) shows the transfer function for a digital linear Signal interface
Gate drivers
predictive filter that is used in series with the proposed com- / conditioning
pensator. Numerical computations show that phase margin is
significantly increased for both light and rated load conditions PWM ADC
in the example converter. 1–d(t) i in
(b) Linear
H(z) = 2 − z −1 (13) + prediction

Moreover, if optimisation algorithms are to be employed +

C1(s)
in the compensator’s design, the plant control oriented model
G(s) can include the dynamics of an input EMC filter and the C 2(s)
boost inductor winding resistance. An additional increase in Kreg vo
system’s stability can also be obtained by choosing different Voltage _
1/x Vo *
compensator eV +
values for Krat . A lower value than suggested in (10) de-
creases the system cut-off frequency and enables the proposed
compensator to work as a lag compensator even when process-
ing rated power. The complete analysis including these points Fig. 10. Implemented input current self-control strategies: (a)
will be presented in the final version of this work. original P-type controller; and, (b) proposed compensator.
 It has been verified that the transport delays which are inher-
ent to digital controllers decrease the system phase margin as
vin the processed power decreases. This is a severe problem and
leads to the system being unstable at light loading conditions.
The replacement of the proportional compensator with an
iin
adaptive lag compensator is proposed to increase the stable
load range. Output voltage regulation is achieved by varying
only the compensator’s low frequency gain. Thus, gain vari-
ation strategies for the proportional controller remain applica-
ble as in the original concept.
Experimental results have proved that the use of the pro-
posed compensator extends the load range for stable opera-
tion. In the example converter, stable operation without no-
ticeable oscillations was achieved even when decreasing pro-
cessed power to half of the level that would make it unstable
with a digital proportional compensator. Therefore, this con-
Fig. 11. Experimental results with a digital proportional trol strategy makes the digital implementation of input current
compensator at 65% of rated power. The input current local average self-control more robust and suitable to systems that must at-
value suffers intense oscillations and approaches instability. tend to various load levels.

ACKNOWLEDGEMENT
The authors would like to thank Eng. Marcio S. Ortmann
vin
for his assistance in obtaining the experimental results.

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