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Design and Implementation of a Turbo Code System on FPGA

Conference Paper · November 2011

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 Design and Implementation of a Turbo Code System on FPGA
Nguyen Viet Ha1, Tran Thi Thao Nguyen1, Dang Le Khoa1, Vo Khac Thanh1, and Bui Huu Phu2
1
University of Science, 227 Nguyen Van Cu st., dist. 5, HCMC, Vietnam
2
Post & Telecommunications Institute of Technology, 11 Nguyen Dinh Chieu st., dist. 1, HCMC, Vietnam

Abstract— Error control coding is an important part of Because Turbo code plays an important role in the
communications systems to recover original transmitted data in modern wireless communications, it has recently been studied
fading environments. In 3G and 3G beyond mobile systems, widely over the world [1, 4, 5]. In the paper, we focus on the
Turbo code technology has been used because of its study of the encoder by simulating it on Matlab and then
outperformance compared to the other technologies. The
contributions of the paper are to study the Turbo code, simulate
design and implement on the FPGA board. The results have
its on Matlab, then design and implement the code on FPGA shown the success of our research.
successfully. The remaining of the paper is divided as follows: in the
Keywords: Turbo code, Forward error correction, FPGA. next section, a detailed study on Turbo code is presented. In
section III, the simulation of Turbo code is considered. The
design and implementation of Turbo code on FPGA is
I. INTRODUCTION described in section IV. Finally, the conclusions are drawn in
section V.
In wireless communications, error control coding is a
very important part to recover transmitted data over fading II. DESIGN OF TURBO CODE
environments. Many studies have been focused on increasing The paper carries out the error control coding, Turbo
the ability of error correction of the coding systems. Recently, code based on parallel model and SOVA decoding.
Turbo code has been considered as the best error control
coding technology, thus it has been used in high speed data A- Encoder: Turbo code is a parallel connection of the
rate systems such as 3G mobile networks and beyond 3G [1-5] concatenated convalutional code (Parallel Concatenated
Convolutional Code - PCCC) as shown in Fig. 3. Code rate of
Turbo code is a combination of two or more separate the encoder is r = k/n. Each input information bit becomes a
encoders in order to generate a new and better encoder. The part of output codewords and is added by (1/r - 1) parity bits
first combined coding model made by Dr. Forney was for error correction. If r is small, then the number of parity bits
considered to build an emcoder which has error probility increase, thus the ability of error correction also increases, but
decreasing on the exponential power when data rate is less code rate decreases
than channel capacity, whereas the complexity of decoding
increases linearly [3]. The model includes the serious
combination of an internal encoder and an external one.
Generally, there are two types of combinations as parallel and
serial as shown in Figs. 1 and 2. For serial encoder, total
coding rate is given by
Rnt = k1k2/n1n2 (1)
Fig. 3 : PCCC Turbo Encoder
For parallel one, total coding rate is as follows:
Puncture:
Rss = k/(n1+n2) (2)
Is a technique to increase coding rate of an encoder that
does not change the inside of the encoder. The purpose of the
puncture technique is to decrease input information bits in a
manner way to increase coded output bits, as shown in Fig. 4.

Fig. 1: Serial encoder

Fig. 4: A puncture technique to convert code rate from 1/3 to 1/2

Fig. 2: Parallel encoder Interleaver:
The above models are just general combination models. In Turbo code, there are some interleavers used between
In order to get good result and increase the ability of error encoders to enhance the error correction. The interleaver is
correction at the receiver, the models need to use interleavers used to exchange the positions of input bits in order to
between encoders which use the convolutional coding.
increase the minimum free distance of codewords, as shown in of the ML route and updates the reliability values. It is seen
Fig. 5. There are some common interleaving techniques such that the mothod decreases the computing complexity during
as matrix interleaving, PN interleaving, circular shift the update period. Instead of estimate 2m survivor routes, only
interleaving, parity interleaving. In the paper, our interleaver is one ML route is processed.
designed based on the below rules:
At the first step, interleaving as:

mk = ,

where k = 0,1,2,…,Ncbps-1
At the second step, interleaving as
jk = s . floor + (m + Ncbps – floor )mod(s)

where m = 0,1,…,Ncbps–1

System code
Encoder RCS 2
Low weight code
Fig. 7 : An example of a Trellis diagram

Registers
High weight code
Interleaver Encoder RCS 2

ML states
Pre-
Fig. 5: Position of an Interleaver used in Turbo encoder SOVA
B- Decoder: In Turbo code, the decoder is carried out
iteratively but the complexity just increases linearly according
Registers
to the size of frames. PCCC code has a structure of connection
in parallel but the decoding process is carried out in series
because serial connection can share information between
Fig. 8 : Structure of a SOVA decoder
decoders. There are two decoding techniques: SOVA and
MAP, as shown in Fig. 6. III. SIMULATION RESULTS ON MATLAB
Decoding algorithms In order to evaluate the performance of Turbo code, in
based on Trellis the paper we compared the bit error rate performance of a
wireless system used three different encoders: Convolutional
code – Reed Solomon (CC-RS), Convolutional Code, and
Turbo Code, as shown in Figs. 9, 10, 11, and 12.

Advanced SOVA

Fig. 6 : Decoding algorithms based on Trellis

Though MAP algorithm is better than SOVA but its hardware
structure and decoding computing process are much more
complexity. Therefore, in the paper, the decoder is studied
based on SOVA algorithm. The reliability of the SOVE
decoder is calculated from trellis diagram in Fig. 7.
Block diagram of a SOVA decoder is shown in Fig. 8. a. CC-RS encoder
The decoder has two inputs L(u) and Lcy, which are reliability
value and received value after equalization; two ouputs u’ và
L(u’), which are decided bits and a posteriori information bits.
The implementation of SOVA decoder includes two separate
SOVA decoders. The first one only calculates metrics of the
maximum likelihood routes. The shift registers are used to
buffer for inputs while the first decoders is processing the
metric of ML routes. The second decoder estimates the metric
 Fig. 12: A detailed SOVA decoder in Turbo Code
b. CC-RS decoder
Fig. 13 shows the BER performance of three different
Fig. 9: Block diagram of CC-RS encoder and decoder
encoders in the AWGN fading environment. It is clearly seen
that Turbo code outperforms the CC-CC and CC-RS encoders.

a. CC-CC encoder

b. CC-CC decoder
Fig. 13: Performance comparison of three different encoders
Fig. 10: Block diagram of a two serial combined convolutional (CC –
CC) encoder and decoder IV. DESIGN AND IMPLEMENTATION OF TURBO CODE ON
FPGA
The design and implementation of Turbo code are
carried out based on DSP Builder, which is a tool developed
by Altera to support users quickly design the applications of
digital signal processing.

a. PCCC encoder

Fig. 14: Design model of Turbo code on FPGA

The design model of Turbo code is shown in Fig. 14.
Data generator is done by using data output from a counter as
shown in Fig. 15. Data from the counter after going through
Look Up Table will be XOR with data from PN generator in
b. PCCC decoder
order to provide input data for system. Generate polynomial of
Fig. 11: Block diagram of a PCCC encoder and decoder PN generator is “1 + X3 + X10”. The data generator will
generate frames of fixed length of 258 bits composing 256
information bits and 2 end bits for ending the trellis status.

Fig. 15: Block diagram of data generator Fig. 18: Trellis terminator
Turbo Encoder includes two parallel connected RSC Turbo Decoder is carried out based on the Viterbi
encoders, as shown in Fig. 16. Data before coming to each algorithm including three main parts as follows:
encoder will go through interleaver with fixed length of 256
bit. The first encoder generates two bit sequences: one - Hamming distance estimator is designed to calculate
information bit sequence and one parity bit sequence. The Hamming distance of coded bits with branchs as shown in
second encoder generates the second parity bit sequence. Fig. 19.
Coded data will go to the multiplexer.

Fig. 19: Hamming distance estimator

- Adder is designed to calculate total of Hamming distance

of each state. At each state, there are two adders used for
two routes of one state. The adder has three inputs and
one output. The inputs include:
Fig. 16: Block diagram of Turbo encoder - Counter: takes responsibility for signal
Each encoder uses convolutional code with constrent synchronization.
length of 3 and code rate of ½. The first generate polynomial - HD(6:0): 7 bits used to transmit the values of
is G1= 7OCT for the feed back route, and the second generate Hamming distance.
polynomial is G2= 5OCT for output route, as shown in Fig. 17.
- State_metric(6:0): 7 bits used to transmit state metric
of the previous state.
The output includes:
- path_metric(6:0) is temporary values of state metric
at considering time.

Fig. 17: RSC Encoder

The end of the RCS coding process is not simple by
adding K-1 bits of 0 to remove data inside of registers, but
having designed a trellis terminator, as shown in Fig. 18.
Fig. 20: Adder

Comparator: based on the total estimated Hamming

distance of routes will find the optimal route. The comparator
has five inputs and two outputs. The input includes:
 - Counter takes responsibility for signal implemented the code on FPGA in the AWGN environment.
synchronization. The results have shown the success of our design and
implementation. In future work, we will consider on designing
- Metric_in0 và Metric_in1: use from outputs of adder
and implementing the Turbo code over the real Rayleigh ad
above.
Rician fading environments.
- path_in0 và path_in1 use to transmit decoded bits of
Reference
previous state.
[1] Bernard Sklar, “Fundamentals of Turbo Codes”
The output includes:
[2] Berrou, C., Glavieux, A., and Thitimajshima, P., “Near Shannon
- Metric_out: export real value of state metric at the Limit Error-Correcting Coding and Decoding: Turbo Codes,” IEEE
considering time. Proceedings of the Int. Conf. on Communications, Geneva,
Switzerland, May 1993 (ICC’93), pp. 1064-1070
- path_out: export decoded bit sequence at the
considering time. [3] Forney, G. D., Jr., Concatenated Codes (Cambridge, MA: MIT
Press), 1966.
[4] Berrou, C. and Glavieux, A., “Near Optimum Error Correcting
Coding and Decoding: Turbo-Codes,” IEEE Trans. on
Communications, vol. 44, no. 10, October 1996, pp. 1261-1271.
[5] M. C. Valenti and J. Sun, “The UMTS Turbo Code and an
Efficient Decoder Implementation Suitable for Software-Defined
Radios,” International Journal of Wireless Information Networks,
Vol. 8, No. 4, October 2001 (© 2002)

Fig. 21: The comparator

In addition, in order to increase the system efficiency, an
interleaver is applied before encoder and de-interleaver before
decoder, which are mentioned section II.

Fig. 22: Interleaver and de-interleaver

After design and export data to FPGA board, the results
of the system through the AWGN fading environment have
been shown in Fig. 23. It is clearly seen that out Turbo code is
designed and implemented successfully.

(a) Original transmited data, (b) Coded data

(c) Coded data after adding AWGN noise, (d) Decoded data
Fig. 23: Results of designed and implemented Turbo code
V. CONCLUSIONS
Turbo code is a very important part in the modern high speed
wireless communications systems such as 3G and beyond 3G
mobile networks. In the paper, we first have designed and
simulated the code in Matlab. The results have shown that
Turbo code outperforms the other codes. Then, we have

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