ecrw file ho vate 1) 2-7/2 Period 2. Activity 3.2.1 $81 Asynchronous Counters: Up Counters and Down Counters Introduction Asynchronous counters can be designed to count up or count dawn using Small-Scale Integration (SSI). ‘The small-scale design can utilize almost any flip-flop type. To observe this process, we will simulate and ‘analyze multiple 3-bit counters based on both D and J/X flipflops. For both the D flip-flop and 1/K flip-flop, we will modify circuits so that they will count up or count down. Remember, for up counters, connect the CLK to the Q output of the opposite polarity. For down counters, connect the CLK to the Q output of the same polarity. SI (0 flip-flops) 4 4 4 te ~27R ~1PR ~2eR, {22 39] {20 20l 19 {20 aq} 1c ~10 }2cxx-20)— —prctx-29b— 2eLK~20b— ner | <2cuR wicLR 2CLR Tyas7an Vyaus74n Vyaus74n Vraus7an Opposite Polarity = Up Counter ‘Same Polarity = Down Counter Equipment * Circuit Design Software (CDS) * Digital MiniSystem (OMS) © myDAQ © myDigital Protoboard © Cmod $6 FPGA Module © #22 Gauge solid wireProcedure Simulation (Design Mode) 1. The circuit shown below is a 3-Bit Binary-Up Counter implemented with 741874 D flip-flops. This design will count from 0 to 7 and then repeat. Kao as Ma vec Y GND 20" "tal 2) 100 Hz, = = sv TALSTAN TALS7AN ‘TALS7AN Bit Binary Up Counter with D Flip-Flops 2. Using Design Mode of the CDS, enter the 3-Bit Binary Up Counter. b. With the RESET switch set to SV, start the simulation. Verify that the circuit is working as expected. if the results are not what are expected, review your circuit and make any necessary corrections. You ‘may need to adjust the clock speed to be able to observe the outputs changing. {With the simulation eunning, toggle the RESET switch to GROUND. What effect does this have on the output? Tin. dum, €t tre cele: and cele A te acre 4. Toga the RESET switch back to SV. What effect does this have on the output? TWh, Ae the comles back > is Ve ‘e. Finally, observe that the HEX DISPLAY appears to jump between some count changes. What causes this to occur? Kay < ane, Zo WW he, 3 \ \ i My beave2. Modify the circuit in step (1) to make ita 3-Bit Binary Down Counter. Repeat steps 12) through 1f] for this modified counter. 4. Using Design Mode of the CDS, draw the 3+ it Binary Down Counter. With the RESET switch set to SY, start the simulation. Verify that the circuit is working as expected. If the results are not what are expected, review your circuit and make any necessary corrections. You ‘may need to adjust the clock speed to be able to observe the outputs changing. ©. With the simulation running, toggle the RESET switch to GROUND. ‘What effect does this have on the output? 4d. Toggle the RESET switch back to SV. What effect does this have on the output? \ aed 4 da 3. The circuit shown below isa 3-Bit Binary Down Counter implemented with 741576 J/« flip-flops. This design will count from 7 to 0 and then repeat. co a Oas vec rT Y eno Tie Pee | ian TA 1a LS wa| Sie a0 TALSTEN TALSTEN TALSTEN 3-Bit Binary Down Counter with J/K Flip-Flops ‘a. Using Design Mode of the COS, enter the 3-Bit Binary Down Counter. b. With the RESET switch set to SV, start the simulator. Verify that the circuit is working as expected. if the results are not what are expected, review your circuit and make any necessary corrections. You ‘may need to adjust the simulation speed to be able to observe the outputs changing, ‘With the simulation running, toggle the RESET switch to GROUND. ‘What effect does this have on the output? Ws dim Are comes 4d. Toggle the RESET switch back to SV. What effect does this have on the output? Bdr Ave wh b7, Law id luck LeiXN 4. Mody the circuit tn step (8) to rake Ha bit inary Lip Counter. Noqeat steps 49) throug $d) for this molified couriter 4 Using Design Mode of the CDS, enter the 5-Bit Binary Up Counter 1 With the ESET swith set to, start the ator, Verify that the circuit workig ae enpected. the results are not what ar expected, review your crcult and make any necessary crrections. Yow nay eel 0 adjust the sinulation speed to be able to observe the outputs chaning With the simulation running, toggle the RESET switch to GROUND, What effect doos this have on the output? |. Toggle the RESET switch back to SV, What effect does this have on the output? \ \ \ oi «@ Simulation (PLD Mode) 5. The circuit shown below is the same 3-8it Binary Down Counter implemented with 741576 J/k flip-flops (only its created in PLD Mode), This design will count from 7 to 0 and then repeat, Pes ee 3-BitBinary Down Counter with Fip-lops Using PLD Mode of the CDS;enter the 3-Bit ‘Down Counter. 1. Change te cuit (sin above so that the 3 Bt Binary Down Counter would reset to seven (11), E molsinabaseneatd his document Eeeetenpinieny 4d. Assign the inputs/outputs in PLD mode and wire the circuit using the DLB or DMS. '¢ Assign Reset to (111) to 2 push button, '* Assign (D0-D2) to 3 LEDs of the same color in a row. Verify the design works on your DMS or DLB. E attach a copy of the circuit to this document. Teacher verification of working creutt (YZConclusion 1. Explain why asynchronous counters are also referred to as ripple counters. Mage ceed be cn vane Vrecne Mae Way Nets dime bev iV hing The 6. pins, Cetin e vignle GRR cA cael Ceo] Re Meany adage 2. What changes must be made to a 3-Bit counter to make it a 4-Bit counter? a Rather TALSTE ge wad Ve add and anilhes oped odded, Ae Ane fin Vidked We Same cathe pred: omer 3. The RESET circuit used on the four 3-Bit Counters analyzed in this activity reset the counts to zero (000). tt makes sense for the up-counters to start at zero (000), but the down-counters should start at seven (111). What would you need to change so that the 3-8it Binary Down Counter with J/K Flip-Flops You just created would reset to seven (111)? The chew \dn mot he Wobed Ame pred dap We THES IG che valhes “en “We clea puis,