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Sir Syed CASE Institute of Technology, Islamabad: Digital System Design Lab

The document describes an experiment to implement a finite state machine using Verilog on an FPGA board. The objectives are to learn how to implement an FSM in Verilog and get familiar with designing a sequence detector. It introduces FPGAs and the board used. It describes the push buttons and LEDs on the board. It then explains Mealy and Moore state machines and provides state diagrams for each. The task is to design a combination lock that unlocks when the 101 sequence is input. Verilog code must be written for the state transition diagram and tested on the FPGA board by observing the LED outputs. Steps provided include design, compilation, simulation, constraints file creation, translation, mapping, placement, and generating a bitstream

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Irfan Haider
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80 views

Sir Syed CASE Institute of Technology, Islamabad: Digital System Design Lab

The document describes an experiment to implement a finite state machine using Verilog on an FPGA board. The objectives are to learn how to implement an FSM in Verilog and get familiar with designing a sequence detector. It introduces FPGAs and the board used. It describes the push buttons and LEDs on the board. It then explains Mealy and Moore state machines and provides state diagrams for each. The task is to design a combination lock that unlocks when the 101 sequence is input. Verilog code must be written for the state transition diagram and tested on the FPGA board by observing the LED outputs. Steps provided include design, compilation, simulation, constraints file creation, translation, mapping, placement, and generating a bitstream

Uploaded by

Irfan Haider
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Sir Syed CASE Institute of Technology, Islamabad

Digital System Design Lab

Experiment # 5: Implementation of Finite State Machine in


Verilog using FPGA

Name of Student: …………………………………………………….

Roll No.: ……………………………………………………………….

Date of Experiment: ………………………………………………….

Report submitted on: ………………………………………………..

Marks obtained: ……………………………………

Remarks: ……………………………………………

Instructor’s Signature: ……………………

Digital System Design Lab 1


Experiment # 05
Implementation of Finite State Machine
In Verilog using FPGA

Objectives:
1. Learn how to implement a finite state machine using Verilog.
2. Getting familiarity of steps involve in designing sequence detector and its implementation on
FPGA

Introduction
Field Programmable Gate Array (FPGA):
FPGAs are programmable semiconductor devices that are based around a matrix of Configurable
Logic Blocks (CLBs) connected through programmable interconnects. As opposed to Application
Specific Integrated Circuits (ASICs), where the device is custom built for the particular design,
FPGAs can be programmed to the desired application or functionality requirements. Although
One-Time Programmable (OTP) FPGAs are available, the dominant type are SRAM-based
which can be reprogrammed as the design evolves.
FPGAs allow designers to change their designs very late in the design cycle– even after the end
product has been manufactured and deployed in the field. In addition, Xilinx FPGAs allow for
field upgrades to be completed remotely, eliminating the costs associated with re-designing or
manually updating electronic system

Pinout diagrams

Figure 1: Xilinx Spartan-3 Starter Kit Board (Top Side)

Digital System Design Lab 2


Figure 2: Xilinx Spartan-3 Starter Kit Board (Top Side)

Push Button Switches


The Spartan-3 Starter Kit board has four momentary-contact push button switches, indicated as in
Figure 1. These push buttons are located along the lower edge of the board, toward the right
edge. The switches are labeled BTN3 through BTN0. Push button switch BTN3 is the left-most
switch, BTN0 the right-most switch. The push button switches connect to an associated FPGA pin,
as shown in Table 1. Pressing a push button generates logic High on the associated FPGA pin.

Table -1: Push Button Switch Connection

LEDs
The Spartan-3 Starter Kit board has eight individual surface-mount LEDs located above the push
button switches, indicated by in Figure 1-2. The LEDs are labeled LED7 through LED0. LED7 is the
left-most LED, LED0 the right-most LED. Table 4-3 shows the FPGA connections to the LEDs.

Table-2: LED Connection of Spartan-3 FPGA

Digital System Design Lab 3


Implementation of Finite State Machine (FSM) in Verilog:
• Finite State Machines (FSMs) are a useful abstraction for sequential circuits with centralized
“states” of operation
• At each clock edge, combinational logic computes outputs and next state as a function of inputs
and present state.
• A synchronous sequential circuit is also called as Finite State Machine FSM, if it has finite
number of states. There are two types of FSMs.
1. Mealy State Machine
2. Moore State Machine

Mealy State Machine


A Finite State Machine is said to be Mealy state machine, if outputs depend on both present
inputs & present states. The block diagram of Mealy state machine is shown in the following
figure 3.

Figure-3: Mealy State Machine

Moore State Machine


A Finite State Machine is said to be Moore state machine, if outputs depend only on present
states. The block diagram of Moore state machine is shown in the following figure 4.

Figure-4: Moore State Machine

Digital System Design Lab 4


Mealy and Moore State Machine: Comparison
Moore Machine Mealy Machine

Output is a function of present state only. Output is a function of present state and
input.
Synchronous outputs Asynchronous outputs.

No glitching, one cycle “delay” If input glitches, so does output, output


immediately available
Full cycle of stable output Output may not be stable output may not be
stable long enough to be useful

Lab Task:
Build an electronic combination lock with a reset option, two number inputs (0 and 1), and an
unlock output. The combination should be 101. Whenever a user input this sequence the lock
should be open and a sequence is detected.
You have to write the Verilog code for the following state transition diagram and verify your
design using FPGA.

Figure-5: Sequence Detector

FSM Coding Guidelines


1. Separate the state machine HDL description into two processes one for the combinational into
two processes, one for the combinational logic and one for the sequential logic.
2. Keep FSM logic and non-FSM logic in separate modules.

Figure-6: FSM Logic

Digital System Design Lab 5


State diagram for mealy and moore machine which are two different styles for FSM is given below.

State Diagram for Moore Machine

Figure-7: Moore Machine

State Diagram for Mealy Machine

Figure-8: Mealy Machine

Procedure:
Write a Verilog code and test your state diagram with the help of following steps
Design Steps:
1. Design: it involves the Verilog code for your state machine as well as the module to slow
down the FPGA clock.
Clock Synchronization
To run your code on FPGA you need to slow down the FPGA clock for visualization of results as
it is running on 50 MHz.
1. Compilation
2. Simulation
3. User Constraint: Then create a UCF file to run your code on fpga

Digital System Design Lab 6


Specify Pin Constraints for External Ports
You must often provide a Location (LOC) constraint to define the FPGA pin location for each
external port.
LOC constraints take the following form:
Syntax:
NET<port_name>LOC=<pin_number>;
Example: NET “reset” LOC=L13;
4. Translation
5. Mapping
6. Placement
7. Bit stream: Generate the bit stream (BIT) file that represents the completed hardware
platform
Results:
Prove your results by showing states and outputs on LEDs

Labs Rubrics
Experiment # 5
Implementation of Finite State Machine
In Verilog using FPGA

Name of Student: ……………………………………………… Roll No: ………………

Lab #05: Marks distribution


ER1 ER3 ER7 ER9 RR1
Task

Lab #05: Marks obtained


ER1 ER3 ER7 ER9 RR1 Total
Task

Digital System Design Lab 7


Lab Evaluation Rubrics
# Qualities & Criteria 0 < Poor <=40 40< Satisfactory <= 70 70 < Good <= 90 90< Excellent <=100
No Tasks were Some tasks were Few tasks were left All tasks completed in
completed/ minimal completed. Could not to be completed. due time. All goals
ER1 Task Completion effort shown justify the reasons for Provided achieved.
uncompleted tasks acceptable
and goals. justification for the
uncompleted tasks
and goals.
ER3 Test Bench No test vectors Test vectors applied Test vectors Test vectors
applied/ minimal effort meeting some of the applied fulling appropriately
shown requirements most of the applied
requirements
ER7 Code indentation, No indentation of Computationally Working code and Good structure,
optimization and code, no optimization complex routine good indentation optimized code and
descriptive and no descriptive with improper or structure, but good variable
variable name variable names/ indentation and not optimized names and
minimal effort shown variable names resulting in comments
unnecessary
computations
ER9 Results and Plots Unable to produce any Inaccurate plots and Correct plots Good presentation of
plots or results /minimal results without any the correct plots with
efforts shown necessary proper labels,
identifying features captions & visibility
such as labels,
captions & visibility
Format/Layout & Follows poorly the Follows, for some Follows, for most Closely follows all the
Organization requirement related to part, all the part, all the requirements related
RR1 format and layout. The requirements related requirements to format and layout.
report is disorganized to to format and layout. related to format Written work is well
the extent that it The organization is and layout. The organized and easy to
prevents understanding unclear organization is understand
of he content generally good, but
some parts seem
out of place

Digital System Design Lab 8


Digital System Design Lab 9

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