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Experiment 8: Counting Circuits: (Assignment)

The document describes two experiments on counting circuits using JK flip flops in Proteus: 1) A 4-bit down asynchronous counter that counts from 15 to 0 on negative clock pulses is designed. The output states are recorded in a table. 2) A 4-bit synchronous up counter is designed using external gates to trigger the flip flops based on certain conditions. The counter counts from 0000 to 1111 on each clock pulse. Synchronous counters are faster but more complex than asynchronous counters. The inputs of the first flip flop are fixed at JA=KA=1 so it can toggle its state each clock pulse.

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0% found this document useful (0 votes)
118 views

Experiment 8: Counting Circuits: (Assignment)

The document describes two experiments on counting circuits using JK flip flops in Proteus: 1) A 4-bit down asynchronous counter that counts from 15 to 0 on negative clock pulses is designed. The output states are recorded in a table. 2) A 4-bit synchronous up counter is designed using external gates to trigger the flip flops based on certain conditions. The counter counts from 0000 to 1111 on each clock pulse. Synchronous counters are faster but more complex than asynchronous counters. The inputs of the first flip flop are fixed at JA=KA=1 so it can toggle its state each clock pulse.

Uploaded by

AL Asmr Yamak
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Experiment 8: Counting Circuits (Assignment)

‫ الرجاء اعادة ارسال نفس هذا الملف مع الحلول المطلوبة وارفاق فيديوهين توضيحيين وعدم ارفاق ايه ملفات أخرى‬:‫مالحظة‬.
Q1) 4-bit down binary counter

Using Proteus, design an asynchronous 4-bit down binary counter using JK flip flops as shown
in the circuit below. (Use 74HC76 JK flipflop)

Experiment procedure: ‫طريقة اجراء التجربة‬


a) Start the simulation
b) Set all the flip flops by making S=0. Now all the LEDs are ON.
c) Now, make S = 1. The LEDs still ON.
e) For every Negative clock pulse, the binary output (QDQCQBQA) will decrease by 1
f) Write the binary output, the binary number and the decimal reading in the Table.

Counting Binary Counting


QD QC QB QA
pulse Number reading
1 1 1 1 1111 15
1 1 1 0 1110 14
1 1 0 1 1101 13
1 1 0 0 1100 12
1 0 1 1 1011 11
1 0 1 0 1010 10
1 0 0 1 1001 9
1 0 0 0 1000 8
0 1 1 1 0111 7
0 1 1 0 0110 6
0 1 0 1 0101 5
0 1 0 0 0100 4
0 0 1 1 0011 3
0 0 1 0 0010 2
0 0 0 1 0001 1
0 0 0 0 0000 0
1 1 1 1 1111 15
1 1 0 1 1101 14
‫ ارفاق فيديو من بروتوس لعملية العد كاملة‬: ‫مطلوب اضافي‬

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Q2) 4-bit Synchronous Counter

Using Proteus, design Synchronous 4-bit Up binary counter using JK flip flops (Use 74HC76 JK
flipflop). The circuit count from 0000 to 1111, etc.

Experiment procedure: ‫طريقة اجراء التجربة‬

a) Complete the circuit. You can use external gates based on the following conditions:

o Flipflop A switches every clock.


o Flipflop B switches when the output of flipflop A=1
o Flipflop C switches when the outputs of A=B=1
o Flipflop D switches when the outputs of A=B=C=1

‫ الدائرة المكتملة ترسم هنا‬:

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b) What is the typical feature of Synchronous counter compared to Asynchronous counters?
Answer:
SYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER
In synchronous counter, all flip flops are triggered with same In asynchronous counter, different flip flops are triggered with
clock simultaneously. different clock, not simultaneously.
Synchronous Counter is faster than asynchronous counter in Asynchronous Counter is slower than synchronous counter in
operation. operation.
Synchronous Counter does not produce any decoding errors. Asynchronous Counter produces decoding error.
Synchronous Counter designing as well implementation are Asynchronous Counter designing as well as implementation is
complex due to increasing the number of states. very easy.
Synchronous Counter will operate in any desired count Asynchronous Counter will operate only in fixed count sequence
sequence. (UP/DOWN).

c) In the Circuit, why are the inputs of the first flipflop fixed at JA=KA=1
Answer: When JA=KA=1, it is possible to set or reset the Flip-Flop. If Q is High, AND gate 2 passes on a reset pulse
to the next clock. When Q is low, AND gate 1 passes on a set pulse to the next clock. Eitherway, Q changes to the
complement of the last state toggle. Toggle means to switch to the opposite state.

‫ ارفاق فيديو من بروتوس لعملية العد كاملة‬: ‫مطلوب اضافي‬

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