DIGITAL LOGIC DESIGN

TASK-3
VERILOG SIMULATIO OF
COMBINATIONAL CIRCUITS

NAME : D.HARSHA VARDHAN

SLOT : L41+L42
REG NO : 17BEC0774
BASIC GATES:
1)AND GATE:
An AND gate is a digital logic gate with two or more inputs and one output that performs logical
conjunction. The output of an AND gate is true only when all of the inputs are true. If one or more of
an AND gate's inputs are false, then the output of the AND gate is false.

TRUTH TABLE:

INPUT (A) INPUT (B) OUTPUT (Y)

1 1 1
1 0 0
0 1 0
0 0 0
Verilog code:

Output:
2)NOT GATE:
A NOT gate, often called an inverter, is a nice digital logic gate to start with because it has only a
single input with simple behavior. A NOT gate performs logical negation on its input. In other words,
if the input is true, then the output will be false. Similarly, a false input results in a true output.

TRUTH TABLE:

INPUT (A) OUTPUT(B)

1 0
0 1

Verilog code:
Output:
3)NAND GATE:

A NAND gate (sometimes referred to by its extended name, Negated AND gate) is a digital logic gate
with two or more inputs and one output with behavior that is the opposite of an AND gate. The
output of a NAND gate is true when one or more, but not all, of its inputs are false. If all of a NAND
gate's inputs are true, then the output of the NAND gate is false.

TRUTH TABLE:
4)NOR GATE:
A NOR gate (sometimes referred to by its extended name, Negated OR gate) is a digital logic gate
with two or more inputs and one output with behavior that is the opposite of an OR gate. The
output of a NOR gate is true all of its inputs are false. If one or more of a NOR gate's inputs are true,
then the output of the NOR gate is false

TRUTH TABLE:

INPUT (A) INPUT (B) OUTPUT (Y)

1 1 0
1 0 0
0 1 0
0 0 1

OUTPUT:
5)OR GATE:
The output, Q of a “Logic OR Gate” only returns “LOW” again when ALL of its inputs are at a logic
level “0”. In other words for a logic OR gate, any “HIGH” input will give a “HIGH”, logic level “1”
output.

The logic or Boolean expression given for a digital logic OR gate is that for Logical Addition which is
denoted by a plus sign, ( + ) giving us the Boolean expression of: A+B = Q.

Thus a logic OR gate can be correctly described as an “Inclusive OR gate” because the output is true
when both of its inputs are true (HIGH).

CIRCUIT:

OUTPUT:

Verilog code:
Output:

XOR GATE:
The Exclusive-OR Gate function, or Ex-OR for short, is achieved by combining standard logic gates
together to form more complex gate functions that are used extensively in building arithmetic logic
circuits, computational logic comparators and error detection circuits.

The two-input “Exclusive-OR” gate is basically a modulo two adder, since it gives the sum of two
binary numbers and as a result are more complex in design than other basic types of logic gate.
CIRCUIT:

OUTPUT:
HALF ADDER :
A half adder is a type of adder, an electronic circuit that performs the addition of numbers.
The half adder is able to add two single binary digits and provide the output plus a carry
value. It has two inputs, called A and B, and two outputs S (sum) and C (carry). The common
representation uses a XOR logic gate and an AND logic gate.

Truth Table:

A B C S
(CARRY) (SUM)
0 0 0 0

0 1 0 1

1 1 1 0

1 0 0 1

Circuit Diagram:
Verilog code:

Output:
Full Adder
Circuit Explanation:

The full adder adds 3 one bit numbers, where two can be referred to as operands and one
can be referred to as bit carried in. And produces 2-bit output, and these can be referred to
as output carry and sum.

Truth Table:

Circuit Diagram:

Verilog code:
Output:

Inference:
A full adder is a circuit which consists on two half adder which is essentially a 3-Bit adder.
4:1 MULTIPLEXER
The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational
circuit with more than one input line, one output line and more than one select line. It
allows the binary information from several input lines or sources and depending on the set
of select lines , particular input line , is routed onto a single output line.
Every multiplexer has at least one select line, which is used to select which input signal gets relayed
to the output. In a 2-to-1 multiplexer, there’s just one select line. More inputs means more select
lines: a 4-to-1 multiplexer would have 2 select lines, an 8-to-1 has 3, and so on (2n inputs requires n
select lines).

Truth table :
Verilog code:

Output:
4 BIT ADDER SUBTRACTER:
The operations of both addition and subtraction can be performed by a one common binary adder.
Such binary circuit can be designed by adding an Ex-OR gate with each full adder as shown in below
figure. The figure below shows the 4 bit parallel binary adder/subtractor which has two 4 bit inputs
as A3A2A1A0 and B3B2B1B0.

The mode input control line M is connected with carry input of the least significant bit of the full
adder. This control line decides the type of operation, whether addition or subtraction.

When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder. The Ex-OR gate
consists of two inputs to which one is connected to the B and other to input M. When M = 0, B Ex-OR
of 0 produce B. Then full adders add the B with A with carry input zero and hence an addition
operation is performed.

When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence the
complemented B inputs are added to A and 1 is added through the input carry, nothing but a 2’s
complement operation. Therefore, the subtraction operation is performed.

Truth table:

CIRCUIT:
Verilog code:

Output:
3 TO 8 DECODER:
A decoder is a multiple input, multiple output logic circuit that changes codes i/ps into
coded o/ps, where both the inputs and outputs are dissimilar for instance n-to-2n, and
binary coded decimal decoders. Decoding is essential in applications like data multiplexing,
memory address decoding, and 7 segment display
Truth table:
Circuit Diagram:
Verilog code:

Output:
4 TO 2 PRIORITY ENCODER:
A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller
number of outputs. The output of a priority encoder is the binary representation of the original
number starting from zero of the most significant input bit. They are often used to control interrupt
requests by acting on the highest priority encoder.

If two or more inputs are given at the same time, the input having the highest priority will take
precedence.[1] An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are
to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output
since it is superseded by higher-priority input. The output V indicates if the input is valid.

TRUTH TABLE:

CIRCUIT:
Verilog code:
Output:

Four Bit Binary Magnitude

Comparator
Circuit description:
A magnitude digital comparator is a combinational circuit that compares two digital or
binary numbers (consider A and B) and determines their relative magnitudes in order to find
out whether one number is equal, less than or greater than the other digital number.Three
binary variables are used to indicate the outcome of the comparison as A>B, A<B, or A=B.

The below figure shows the block diagram of a n-bit comparator which compares the two
numbers of n-bit length and generates their relation between themselves.

It can be used to compare two four-bit words. The two 4-bit numbers are A = A3 A2 A1 A0
and B3 B2 B1 B0 where A3 and B3 are the most significant bits.
It compares each of these bits in one number with bits in that of other number and
produces one of the following outputs as A = B, A < B and A>B. The output logic statements
of this converter are

• If A3 = 1 and B3 = 0, then A is greater than B (A>B). Or

• If A3 and B3 are equal, and if A2 = 1 and B2 = 0, then A > B. Or
• If A3 and B3 are equal & A2 and B2 are equal, and if A1 = 1, and B1 = 0, then A>B. Or
• If A3 and B3 are equal, A2 and B2 are equal and A1 and B1 are equal, and if A0 = 1 and
B0 = 0, then A > B.

Truth Table:
Circuit diagram:

Verilog code:
Output: