Chapter 6

6.1 What are the advantages of using a glass substrate for a

magnetic disk?
Ans. Improvement in the uniformity of the magnetic film surface
to increase disk reliability. A significant reduction in overall
surface defects to help reduce read/write errors. Ability to support
lower fly heights (described subsequently). Better stiffness to
reduce disk dynamics. Greater ability to withstand shock and
damage.
6.2 How are data written onto a magnetic disk?
Ans. The write mechanism is based on the fact that electricity
flowing through a coil produces a magnetic field. Pulses are sent
to the write head, and magnetic patterns are recorded on the
surface below, with different patterns for positive and negative
currents. An electric current in the wire induces a magnetic field
across the gap, which in turn magnetizes a small area of the
recording medium. Reversing the direction of the current reverses
the direction of the magnetization on the recording medium.
6.3 How are data read from a magnetic disk?
Ans. The read head consists of a partially shielded magneto-
resistive (MR) sensor. The MR material has an electrical resistance
that depends on the direction of the magnetization of the medium
moving under it. By passing a current through the MR sensor,
6.4 Explain the difference between a simple CAV system and a
multiple zoned recording system.
Ans. A simple CAV system has a disk that is divided into a
number of pie-shaped sectors and into a series of concentric
tracks. With multiple zoned recording, the surface is divided
into a number of concentric zones.
6.5 Define the terms track, cylinder, and sector.
Ans. A disk is divided into tracks, cylinders, and sectors.
A track is that portion of a disk which passes under a single
stationary head during a disk rotation, a ring 1 bit wide.
A cylinder is comprised of the set of tracks described by all the
heads (on separate platters) at a single seek position. Each
cylinder is equidistant from the center of the disk. A track is
divided into segments of sectors, which is the basic unit of
storage.
6.6 What is the typical disk sector size?
Ans. 512 bytes
Each sector stores a fixed amount of user-accessible data,
traditionally 512 bytes for hard disk drives (HDDs) and 2048
bytes for CD-ROMs and DVD-ROMs. Newer HDDs use 4096-byte (4
KiB) sectors, which are known as the Advanced Format (AF).

Chapter 7
7.1 List three broad classifications of external, or peripheral,
devices.
Ans. External or peripheral devices can be broadly classified as:
a. Human Readable (Appropriate for communicating with the
computer user e.g. Keyboard, Printer, Screen etc. )
b. Machine Readable (Appropriate for communicating with the
equipment e.g. monitoring and control)
c. Communication (Appropriate for communicating with remote
devices e.g. Modem, NIC (Network Interface Card) etc.)

7.2 What is the International Reference Alphabet?

Ans. The International Reference Alphabet No. 5 (formerly
International Alphabet No.5, or “IA5”) is an international standard
specified in ITU-T Recommendation T.50 for information
interchange among data processing systems and data
communications systems. Each IRA character is a 7-bit coded
unique character. The letters available in this character set are
restricted to the Latin uppercase A-Z and lowercase a-z letters. In
addition to printing characters, IRA also defines codes for control
characters such as linefeed and non-printing character such as
space and delete, which are the same as ANSI X3.4-1986: ASCII
(American Standard Code for Information Interchange). The ASCII
and ISO 646 are equivalent to the International Reference
Alphabet No. 5. The advantage of IRA encoding is its (almost)
universal acceptance and implementation.
7.4 List and briefly define three techniques for performing I/O.
Ans.

 Programmed I/O: The processor issues an I/O command,

on behalf of a process, to an I/O module; that process then
busy-waits for the operation to be completed before
proceeding. 
 Interrupt-driven I/O: The processor issues an I/O
command on behalf of a process, continues to execute
subsequent instructions, and is interrupted by the I/O module
when the latter has completed its work. The subsequent
instructions may be in the same process, if it is not necessary
for that process to wait for the completion of the I/O. Otherwise,
the process is suspended pending the interrupt and other work
is performed. 
 Direct memory access (DMA): A DMA module controls the
exchange of data between main memory and an I/O module.
The processor sends a request for the transfer of a block of data
to the DMA module and is interrupted only after the entire block
has been transferred.
 7.5 What is the difference between memory-mapped I/O and
isolated I/O?
Ans.
Memory mapped I/O is a way to exchange data and instructions
between a CPU and peripheral devices attached to it.
Memory mapped IO is one where the processor and the IO device
share the same memory location (memory), i.e. the processor and
IO devices are mapped using the memory address while On the
other hand, isolated I/O uses separate instruction classes to
access primary memory and device memory. In this case,
I/O devices have separate address space either by separate
I/O pin on CPU or by entire separate bus. As it separates general
memory addresses with I/O devices.
7.6 When a device interrupt occurs, how does the processor
determine which device issued the interrupt?
Ans. basically for processing i/p device interrupts there is special
dedicated chip called as PIC (Programmable Interrupt Controller).

    When you hit interrupt through keyboard it will be initially sent
to PIC then PIC sends a signal on INT pin of processor (due to
which processor will aware that there is something interrupt due
to some device), when processor will free it will send READY
signal to PIC then PIC sends information regarding interrupt
device and interrupt type to processor via data bus line and finally
interrupt is executed.
7.7 When a DMA module takes control of a bus, and while it
retains control of the bus, what does the processor do?
Ans. When a DMA module takes control of a bus, and while
it retains control of the bus, what does the processor do?
The processor either doesn't need to use the bus at the time, or
it is forced to suspend operation temporarily.
The processor deals with other things, while the bus operation
is left to DMA.

Chapter 8
8.1 What is an operating system?
Ans. the software that supports a computer's basic functions,
such as scheduling tasks, executing applications, and controlling
peripherals.
8.2 List and briefly define the key services provided by an OS.

Ans.

 Program creation: The operating system provides a

variety of facilities and services, such as editors and debuggers,
to assist the programmer in creating programs. 
 Program execution: A number of tasks need to be
performed to execute a program. Instructions and data must be
loaded into main memory, I/O devices and files must be
initialized, and other resources must be prepared. 
 Access to I/O devices: Each I/O device requires its own
peculiar set of instructions or control signals for operation. 
 Controlled access to files: In the case of files, control
must include an understanding of not only the nature of the I/O
device (disk drive, tape drive) but also the file format on the
storage medium. 
 System access: In the case of a shared or public system,
the operating system controls access to the system as a whole
and to specific system resources. 
 Error detection and response: A variety of errors can
occur while a computer system is running. 
 Accounting: A good operating system will collect usage
statistics for various resources and monitor performance
parameters such as response time.

8.3 List and briefly define the major types of OS scheduling.

Ans.

 Long-term scheduling: The decision to add to the pool of

processes to be executed.
 Medium-term scheduling: The decision to add to the
number of processes that are partially or fully in main memory. 
 Short-term scheduling: The decision as to which available
process will be executed by the processor

8.4 What is the difference between a process and a program?

Ans.
A program and a process are related terms. The
major difference between program and process is
that program is a group of instructions to carry out a specified
task whereas the process is a program in execution. While
a process is an active entity, a program is considered to be a
passive one
8.5 What is the purpose of swapping?
Ans. Swapping is a useful technique that enables a computer to
execute programs and manipulate data files larger than main
memory. The operating system copies as much data as possible
into main memory, and leaves the rest on the disk.
8.6 If a process may be dynamically assigned to different
locations in main memory, what is the implication for the
addressing mechanism?
Ans. Assigning process to different memory locations
dynamically in main memory: The implication
of this addressing mechanism is that, the addresses in
the program are dynamic in nature. Addresses are expressed
based on the location of the program.
8.7 Is it necessary for all of the pages of a process to be in main
memory while the process is executing?
Ans. It is not necessary for all of the pages of a process to be in
main memory while the process is executing if a virtual
memory is used.

8.9 Is it necessary for the pages of a process in main memory to

be in sequential order?
Ans. A process is divided into pages, and it is loaded in unused
frames for execution. Multiple programs can be loaded in the
Operating System (OS). ... The pages are not needed to
be sequential order, they are all fixed size, the processor
executes whichever is comes in from the main memory.
8.10 What is the purpose of a translation look aside buffer?
Ans. A translation look aside buffer (TLB) is a memory cache
that is used to reduce the time taken to access a user memory
location. It is a part of the chip's memory-management unit
(MMU). The TLB stores the recent translations of virtual memory
to physical memory and can be called an address-
translation cache.
Chapter 9 Problems 9.1 – 9.16 Exercises –

Chapter 10
10.1 Briefly explain the following representations: sign
magnitude, twos complement, biased.

 Ans. Sign–Magnitude Representation: In an N-bit word,

the left-most bit is the sign (0 = positive, 1 = negative) and the
remaining N – 1 bits comprise the magnitude of the number. 
 Twos Complement Representation: A positive integer is
represented as in sign magnitude. A negative number is
represented by taking the Boolean complement of each bit of
the corresponding positive number, then adding 1 to the
resulting bit pattern viewed as an unsigned integer. 
 Biased representation: A fixed value, called the bias, is
added to the integer

10.2 Explain how to determine if a number is negative in the

following representations: sign magnitude, twos complement,
biased.
Ans. Twos Complement Representation: A positive integer is
represented as in sign magnitude. A negative number is
represented by taking the Boolean complement of each bit of
the corresponding positive number, then adding 1 to the
resulting bit pattern viewed as an unsigned integer.
10.3 What is the sign-extension rule for twos complement
numbers?
Ans. Sign extension rule: Preserve the sign and magnitude,
the number of bits is increased by padding the extra bits. This is
done by appending the most significant bit digit in
the extension position.
10.4 How can you form the negation of an integer in twos
complement representation?
Ans. Negation of an integer in twos
complement is represented as follows: Complement the given
number by changing the binary bit “1” to bit “0” and bit “0” to bit
“1'. Add binary digit “1” to this result. Hence, the twos
complement of the integer is solved.
10.5 In general terms, when does the twos complement operation
on an n-bit integer produce the same integer?
Ans. When the operation is performed on the n-bit integer –2 n–
1
 (one followed by n – 1 zeros).
10.6 What is the difference between the twos complement
representation of a number and the twos complement of a
number?
Ans. the main difference between 1′ s complement and 2′ s
complement is that 1′ s complement has two representations of 0
(zero) – 00000000, which is positive zero (+0) and 11111111,
which is negative zero (-0); whereas in 2′ s complement, there is
only one representation for zero – 00000000 (+0) because if we
add 1 to 11111111 (-1), we get 00000000 (+0) which is the same
as positive zero. This is the reason why 2′ s complement is
generally used.
Another difference is that while adding numbers using 1′ s
complement, we first do binary addition, then add in an end-
around carry value. But, 2′ s complement has only one value for
zero, and doesn’t require carry values.

10.7 If we treat 2 twos complement numbers as unsigned

integers for purposes of addition, the result is correct if
interpreted as a twos complement number. This is not true for
multiplication. Why?
Ans. The algorithm for performing twos complement addition
involves simply adding the two numbers in the same way as for
ordinary addition for unsigned numbers, with a test for overflow.
For multiplication, if we treat the bit patterns as unsigned
numbers, their magnitude is different from the twos complement
versions and so the magnitude of the result will be different.

10.8 What are the four essential elements of a number in floating-

point notation?
Ans. The main elements of a floating point
representation are Sign, significand, exponent, base. A floating
point is represented by a sign followed by the significand and the
base with the exponent.
10.9 What is the benefit of using biased representation for the
exponent portion of a floating-point number?
 Ans. An advantage of biased representation is that non-negative
floating-point numbers can be treated as integers for comparison
purposes.
10.10 What are the differences among positive overflow,
exponent overflow, and significand overflow?
Ans. Positive overflow is when a positive number increases
beyond its bounds, exponent overflow is when a positive
exponent exceeds the maximum exponent value,
and significand overflow is when the addition of
two significands of the same sign result in a carry out of the
most significant bit.

10.11 What are the basic elements of floating-point addition and

subtraction?
 Ans. Check for zeros.
 Align the significands.
 Add or subtract the significands.
 Normalize the result.

10.12 Give a reason for the use of guard bits.

Ans. This is done because length of registers always is greater
than bits in the significand along with the implied bit. The
extra bit to match to the length of register to perform any
operation is known as guard bits. Guard bit is used with
rounding to perform any operation.
10.13 List four alternative methods of rounding the result of a
floating-point operation.
Ans.
1. Round to nearest: The result is rounded to the nearest
representable number.
2. Round toward +∞: The result is rounded up toward plus
infinity. 
3. Round toward – ∞: The result is rounded down toward
negative infinity. 
4. Round toward 0: The result is rounded toward zero

Exercises - Chapter #11 Page 402 Problems 11.1 * 11.2 only

Exercises

Chapter 12

12.1 What are the typical elements of a machine instruction?

Ans. Elements of a machine instructions includes operation code,
source operand reference, result operand reference and next
instruction. These four instructions referred and executes to as
computer instructions and also as machine instructions. Every
instruction will carry the information need by the processor for
execution.
12.2 What types of locations can hold source and destination
operands?
Ans.
• Main or virtual memory: As with next instruction
References, the main or virtual memory address must be
Supplied.
• Processor register: With rare exceptions, a processor contains
One or more registers that may be referenced by machine
Instructions. If only one register exists, reference to it may be
Implicit. If more than one register exists, then each register is
Assigned a unique name or number, and the instruction must
contain the number of the desired register.
• Immediate: The value of the operand is contained in a field in
the instruction being executed.
• I/O device: The instruction must specify the I/O module and
device for the operation. If memory-mapped I/O is used, this is
just
another main or virtual
memory address.

12.3 If an instruction contains four addresses, what might be the

purpose of each address?
Ans. If an instruction contains four addresses, each address
serves to represent the two operands, one result, and the address
of the next instruction respectively.
12.4 List and briefly explain five important instruction set design
issues.
Ans.

1. Operation repertoire: How many and which operations to

provide, and how complex operations should be. 
2. Data types: The various types of data upon which
operations are performed. 
3. Instruction format: Instruction length (in bits), number of
addresses, size of various fields, and so on. 
4. Registers: Number of CPU registers that can be referenced
by instructions, and their use. 
5. Addressing: The mode or modes by which the address of
an operand is specified.
12.5 What types of operands are typical in machine instruction
sets?
Ans. The types of operands used mainly in machine instruction
sets are addresses, numbers, characters, and logical data.

12.6 What is the relationship between the IRA character code and
the packed decimal representation?
Ans. For the IRA bit pattern 011XXXX, the digits 0 through 9 are
represented by their binary equivalents, 0000 through 1001, in
the right-most 4 bits. This is the same code as packed decimal.
12.7 What is the difference between an arithmetic shift and a
logical shift?
Ans. Arithmetic shift preserve sign bit, whereas Logical
shift cannot preserve sign bit. Arithmetic shift perform
multiplication and division operation, whereas Logical
shift perform only multiplication operation. Arithmetic shift is
used for signed interpretation, whereas Logical shift is used for
unsigned interpretation.
12.8 Why are transfer of control instructions needed?
Ans.
1. In the practical use of computers, it is essential to be able to
execute each instruction more than once and perhaps many
thousands of times. It may require thousands or perhaps millions
of instructions to implement an application. This would be
unthinkable if each instruction had to be written out separately. If
a table or a list of items is to be processed, a program loop is
needed. One sequence of instructions is executed repeatedly to
process all the data. 

2. Virtually all programs involve some decision making. We would

like the computer to do one thing if one condition holds, and
another thing if another condition holds. 
3. To compose correctly a large or even medium-size computer
program is an exceedingly difficult task. It helps if there are
mechanisms for breaking the task up into smaller pieces that can
be worked on one at a time.

12.9 List and briefly explain two common ways of generating the
condition to be tested in a conditional branch instruction.
Ans. There are two common ways of generating the condition to
be tested in a conditional branch instruction. First, most machines
provide a 1-bit or multiple-bit condition code that is set as the
result of some operations. Another approach that can be used
with a three-address instruction format is to perform a
comparison and specify a branch in the same instruction.
12.10 What is meant by the term nesting of procedures?
Ans. When the sub routine is declared within the scope
of procedure or function, then the function or sub routine is to
be nested or calling the procedure CALL inside the procedure,
then it is said to be nesting of procedure.

12.11 List three possible places for storing the return address for
a procedure return.
Ans. The return address for a procedure return can be
stored in three places:

 Register
 Start of procedure
 Top of stack.

12.12 What is a reentrant procedure?

Ans. A reentrant procedure is one in which a single copy of the
program code can be shared by multiple users during the same
period of time. Reentrance has two key aspects: The program
code cannot modify itself and the local data for each user must be
stored separately.
12.13 What is reverse Polish notation?
Ans. Reverse Polish notation (RPN), also known
as Polish postfix notation or simply postfix notation, is a
mathematical notation in which operators follow their operands,
in contrast to Polish notation (PN), in which operators precede
their operands.
12.14 What is the difference between big endian and little
endian?
Ans. In little endian machines, the least significant byte is
followed by the most significant byte. –Big endian machines store
the most significant byte first (at the lower address).
Exercises - Chapter #13
13.1 Briefly define immediate addressing.
Ans. Immediate addressing is an addressing form in which
the byte value to be used or retrieved in the instruction, is located
immediately after the opcode for the instruction itself.
13.2 Briefly define direct addressing.
Ans. Direct Address. A direct address is the name of the
person (normally) who is being directly spoken to. It is always a
proper noun. It does not have any grammatical relationship to any
part of the sentence. It is set off by commas.
13.3 Briefly define indirect addressing.
Ans. Indirect Addressing. Indirect addressing is a scheme in
which the address specifies which memory word or register
contains not the operand but the address of the operand.
13.4 Briefly define register addressing.
Ans. In this addressing mode, a register contains the operand.
Depending upon the instruction, the register may be the first
operand, the second operand or both.
13.5 Briefly define register indirect addressing.
Ans. In Register indirect addressing, the address field refers
to a register, which in turn contains the effective address of the
operand.
13.6 Briefly define displacement addressing.
Ans. Displacement addressing: The instruction has
two address fields, at least one of which is explicit. The value
contained in one address field (value = A) is used directly.
13.7 Briefly define relative addressing.
Ans. Relative address means an address specified by
indicating its distance from another address, called the
base address. For example, a relative address might be B+15,
B being the base address and 15 the distance (called the offset).
13.8 What is the advantage of autoindexing?
Ans. Provides efficient mechanism for performing iterative
operations. With Autoindexing, document in websites can be
searched easily and at faster rate. o Revisited when any errors
are noticed. Information resources are shared by information
centers using automated indexing.
13.9 What is the difference between postindexing and
preindexing?
Ans. These are two forms of addressing, both of which involve
indirect addressing and indexing. 

With preindexing, the indexing is performed before the

indirection. With postindexing, the indexing is performed after
the indirection.
13.10 What facts go into determining the use of the addressing
bits of an instruction?
Ans.

Number of addressing modes: Sometimes an addressing

mode can be indicated implicitly. In other cases, the addressing
modes must be explicit, and one or more mode bits will be
needed. 

Number of operands: Typical instructions on today’s machines

provide for two operands. Each operand address in the instruction
might require its own mode indicator, or the use of a mode
indicator could be limited to just one of the address fields. 

Register versus memory: The more that registers can be used

for operand references, the fewer bits are needed.

Number of register sets: One advantage of using multiple

register sets is that, for a fixed number of registers, a functional
split requires fewer bits to be used in the instruction. 

Address range: For addresses that reference memory, the range

of addresses that can be referenced is related to the number of
address bits. Because this imposes a severe limitation, direct
addressing is rarely used. With displacement addressing, the
range is opened up to the length of the address register. 

Address granularity: In a system with 16- or 32-bit words, an

address can reference a word or a byte at the designer’s choice.
Byte addressing is convenient for character manipulation but
requires, for a fixed-size memory, more address bits.

13.11 What are the advantages and disadvantages of using a

variable-length instruction format?
Ans. One of the advantages of using a variable-length instruction
format is that it easy to provide a large repertoire of opcodes,
with different opcode lengths. Addressing can be more flexible,
with various combinations of register and memory references plus
addressing modes. 

A disadvantage however is an increase in the complexity of the

CPU.

Chapter 14

14.1What general roles are performed by processor registers?

Ans. ultimately, the role of processor registers is to connect
the output from one computation to the input(s) of one or more
subsequent computations. Step back from the computation
pipeline for a moment, and think of the computations you would
like to perform.
14.2 What categories of data are commonly supported by user-
visible registers?
Ans. General Purpose; Data; Address; Condition codes

14.3 What is the function of condition codes?

Ans. Condition codes are bits set by the CPU hardware as the
result of operations.
For example, an arithmetic operation may produce a positive,
negative, zero, or overflow result. In addition to the result
itself being stored in a register or memory, a condition code is
also set. The code may subsequently be tested as part of a
conditional branch operation.
14.4 What is a program status word?

Ans. All CPU designs include a register or set of registers,

often known as the program status word(PSW), that contain
status information. The PSW typically contains condition codes
plus other status information.

14.5 Why is a two-stage instruction pipeline unlikely to cut the

instruction cycle time in half, compared with the use of no
pipeline?
Ans.
 The execution time will generally be longer than the fetch
time. Execution will involve reading and storing operands
and the performance of some operation. Thus, the fetch
stage may have to wait for some time before it can
empty its buffer.
 A conditional branch instruction makes the address of
the next instruction to be fetched unknown. Thus, the
fetch stage must wait until it receives the next instruction
 address from the execute stage. The execute stage may
then have to wait while the next instruction is fetched.

14.6 List and briefly explain various ways in which an instruction

pipeline can deal with conditional branch instructions.
Ans. Multiple streams: A brute-force approach is to replicate the
initial portions of the pipeline and allow the pipeline to fetch
both instructions, making use of two streams. Prefetch
branch target: When a conditional branch is recognized, the
target of the branch is prefetched, in addition to the
instruction following the branch. This target is then saved
until the branch instruction is executed. If the branch is
taken, the target has already been prefetched. Loop buffer:
A loop buffer is a small, very-high-speed memory maintained
by the instruction fetch stage of the pipeline and containing
the n most recently fetched instructions, in sequence. If a
branch is to be taken, the hardware first checks whether the
branch target is within the buffer. If so, the next instruction
is fetched from the buffer. Branch prediction: A prediction is
made whether a conditional branch will be taken when
executed, and subsequent instructions are fetched
accordingly. Delayed branch: It is possible to improve pipeline
performance by automatically rearranging instructions within
a program, so that branch instructions occur later than
actually desired
14.7 How are history bits used for branch prediction?
Ans. One or more bits that reflect the recent history of the
instruction (history bits) can be associated with each conditional
branch instruction. These bits are referred to as a taken/not taken
switch that directs the processor to make a particular decision the
next time the instruction is encountered.
Chapter 15

15.1 What are some typical distinguishing characteristics of RISC

organization?
Ans. Typical distinguishing characteristics of RISC
organization are, fewer number of instructions with fixed format.
With reduced instruction set pipelining technique can be applied
effectively. RISC processors response for interrupts are more
effective compared to CISC.
15.2 Briefly explain the two basic approaches used to minimize
register-memory operations on RISC machines.
Ans. Two basic approaches to minimizing register-memory
operations are possible, one based on software and the other on
hardware. The software approach is to rely on the compiler to
maximize register usage. The compiler will attempt to
allocate registers to those variables that will be used the most
in a given time period.
15.3 If a circular register buffer is used to handle local variables
for nested procedures, describe two approaches for handling
global variables.
Ans. The two approaches for handling global variables
where a circular register buffer is used to handle local
variables for nested procedures:
1. Variables declared as global in an HLL can be assigned
memory locations by the compiler, and all machine
instructions that reference these variables will use memory-
reference operands.
2. Incorporate a set of global registers in the processor. These
registers would be fixed in number and available to all
procedures.
 15.4 What are some typical characteristics of a RISC instruction
set architecture?
Ans.
1. One instruction per cycle. 
2. Register-to-register operations. 
3. Simple addressing modes. 
4. Simple instruction formats.

15.5 What is a delayed branch?

Ans. The delayed branch means that the instruction following
the branch is always executed before the PC is modified to
perform the branch.

Chapter 16

16.1 What is the essential characteristic of the superscalar

approach to processor design?
Ans. Common instructions such as load/store instructions are
simultaneously initiated and execution is done independently.
Processing in superscalar approach issues more than one
instruction per cycle. Out-of-order execution is allowed
by superscalar approach.
16.2 What is the difference between the superscalar and
superpipelined approaches?
Ans. Superpipelining exploits the fact that many pipeline stages
perform tasks that require less than half a clock cycle.
Thus, a doubled internal clock speed allows the performance of
two tasks in one external clock cycle.
16.3 What is instruction-level parallelism?
Ans. Instruction-Level Parallelism is a measurement of the
number of operations that can be performed simultaneously in a
computer program. Microprocessors exploit ILP by executing
multiple instructions from a single program in a single cycle.
16.4 Briefly define the following terms: • True data dependency •
Procedural dependency • Resource conflicts • Output dependency
• Anti dependency
Ans.
 A Flow dependency, also known as a data
dependency or true dependency or read-after-write
(RAW), occurs when an instruction depends on the result of a
previous instruction: 1.
 Cannot execute instructions after a branch in parallel with
instructions before a branch • Also, if instruction length is
not fixed, instructions have to be decoded to find out how
many fetches are needed • This prevents simultaneous
fetches.
 A resource conflict is a situation when more than one
instruction tries to access the same resource in the same
cycle. A resource can be a register, memory, or ALU. In the
above scenario, in cycle 4, instructions I 1 and I4 are trying to
access same resource (Memory) which introduces
a resource conflict.
16.5 What is the distinction between instruction-level parallelism
and machine parallelism?
Ans.
 Instruction-level parallelism exists when instructions in a
sequence are independent and thus can be executed in
parallel by overlapping. Machine parallelism is a measure of
the ability of the processor to take advantage of instruction-
level parallelism. 
  Machine parallelism is determined by the number of
instructions that can be fetched and executed at the same
time (the number of parallel pipelines) and by the speed and
sophistication of the mechanisms that the processor uses to
find independent instructions.

16.6 List and briefly define three types of superscalar instruction

issue policies.
Ans.
 In-order issue with in-order completion: Issue
instructions in the exact order that would be achieved by
sequential execution and to write results in that same order.
 In-order issue with out-of-order completion: Issue
instructions in the exact order that would be achieved by
sequential execution but allow instructions to run to
completion out of order. 
 Out-of-order issue with out-of-order completion: The
processor has a look ahead capability, allowing it to identify
independent instructions that can be brought into the
execute stage. Instructions are issued with little regard for
their original program order. Instructions may also run to
completion out of order.

16.7 What is the purpose of an instruction window?

Ans. For an out-of-order issue policy, the instruction window is
a buffer that holds decoded instructions. These may be issued
from the instruction window in the most convenient order.
16.8 What is register renaming and what is its purpose?
Ans. In register renaming, registers are allocated dynamically by
the processor hardware, and they are associated with the values
needed by instructions at various points in time. When a new
register value is created (i.e., when an instruction executes that
has a register as a destination operand), a new register is
allocated for that value.
16.9 What are the key elements of a superscalar processor
organization?
Ans. The key elements of a superscalar processor are
outlined below: Instruction fetch strategies that simultaneously
fetch multiple instructions, often by predicting the outcomes of,
and fetching beyond, conditional branch instructions.

Chapter 17
17.1 List and briefly define three types of computer system
organization.
Ans.
1. Instruction fetch strategies that simultaneously fetch
multiple instructions, often by predicting the outcomes of,
and fetching beyond, conditional branch instructions. These
functions require the use of multiple pipeline fetch and
decode stages, and branch prediction logic.
2. Logic for determining true dependencies involving register
values, and mechanisms for communicating these values to
where they are needed during execution.
 3. Mechanisms for initiating, or issuing, multiple instructions in
parallel.
4. Resources for parallel execution of multiple instructions,
including multiple pipelined functional units and memory
hierarchies capable of simultaneously servicing multiple
memory references.
5. Mechanisms for committing the process state in correct
order.

17.2 What are the chief characteristics of an SMP?

Ans. The chief characteristics of SMP are as listed below;
1. There are two or more similar processors of comparable
capability. 
2. These processors share the same main memory and I/O
facilities and are interconnected by a bus or other internal
connection scheme, such that memory access time is
approximately the same for each processor. 
3. All processors share access to I/O devices, either through the
same channels or through different channels that provide
paths to the same device. 
4. All processors can perform the same functions (hence the
term symmetric). 
5. The system is controlled by an integrated operating system
that provides interaction between processors and their
programs at the job, task, file, and data element levels.

17.3 What are some of the potential advantages of an SMP

compared with a uniprocessor?
Ans.
SMP has a potential
advantages over uniprocessor architecture: - Performance: A
system with multiple processors will perform in a better way than
one with a single processor of the same type if the task can be
organized in such a manner that some portion of the work done
can be done in parallel.

17.4 What are some of the key OS design issues for an SMP?
Ans. SMP has some key OS design issues;
1. Simultaneous concurrent processes: OS routines need
to be reentrant to allow several processors to execute the
same IS code simultaneously. With multiple processors
executing the same or different parts of the OS, OS tables
and management structures must be managed properly to
avoid deadlock or invalid operations. 
2. Scheduling: Any processor may perform scheduling, so
conflicts must be avoided. The scheduler must assign ready
processes to available processors. 
3. Synchronization: With multiple active processes having
potential access to shared address spaces or shared I/O
resources, care must be taken to provide effective
synchronization. Synchronization is a facility that enforces
mutual exclusion and event ordering. 
4. Memory management: Memory management on a
multiprocessor must deal with all of the issues found on
uniprocessor machines. In addition, the operating system
needs to exploit the available hardware parallelism, such as
multiported memories, to achieve the best performance. The
paging mechanisms on different processors must be
coordinated to enforce consistency when several processors
share a page or segment and to decide on page
replacement. 
 5. Reliability and fault tolerance: The operating system
should provide graceful degradation in the face of processor
failure. The scheduler and other portions of the operating
system must recognize the loss of a processor and
restructure management tables accordingly.

17.5 What is the difference between software and hardware

cache coherent schemes?
Ans. Software cache coherence schemes attempt to avoid the
need for additional hardware circuitry and logic by relying on the
compiler and operating system to deal with the problem.

In hardware schemes, the cache coherence logic is implemented

in hardware.

17.6 What is the meaning of each of the four states in the MESI
protocol?
Ans.
Modified: The line in the cache has been modified (different
from main memory) and is available only in this cache. 
Exclusive: The line in the cache is the same as that in main
memory and is not present in any other cache. 
Shared: The line in the cache is the same as that in main
memory and may be present in another cache.
Invalid: The line in the cache does not contain valid data.

17.7 What are some of the key benefits of clustering?

Ans. Here's why clustering is important in computer
architecture;
Absolute scalability: It is possible to create large clusters that
far surpass the power of even the largest standalone machines. 
Incremental scalability: A cluster is configured in such a way
that it is possible to add new systems to the cluster in small
increments. Thus, a user can start out with a modest system and
expand it as needs grow, without having to go through a major
upgrade in which an existing small system is replaced with a
larger system. 
High availability: Because each node in a cluster is a
standalone computer, the failure of one node does not mean loss
of service. 
Superior price/performance: By using commodity building
blocks, it is possible to put together a cluster with equal or
greater computing power than a single large machine, at much
lower cost.

17.8 What is the difference between failover and failback?

Ans. The function of switching an applications and data resources
over from a failed system to an alternative system in the cluster
is referred to as failover. 
A related function is the restoration of applications and data
resources to the original system once it has been fixed; this is
referred to as failback.

17.9 What are the differences among UMA, NUMA, and CC-NUMA?
Ans.
 1. Uniform memory access (UMA): All processors have
access to all parts of main memory using loads and stores.
The memory access time of a processor to all regions of
memory is the same. The access times experienced by
different processors are the same. 
2. Nonuniform memory access (NUMA): All processors have
access to all parts of main memory using loads and stores.
The memory access time of a processor differs depending on
which region of main memory is accessed. The last
statement is true for all processors; however, for different
processors, which memory regions are slower and which are
faster differ. 
3. Cachecoherent NUMA (CC-NUMA): A NUMA system in
which cache coherence is maintained among the caches of
the various processors.

Chapter 18

18.1 Summarize the differences among simple instruction

pipelining, superscalar, and simultaneous multithreading.
Ans.
 Pipelining: Individual instructions are executed through a
pipeline of stages so that while one instruction is executing
in one stage of the pipeline, another instruction is executing
in another stage of the pipeline.
  Superscalar: Multiple pipelines are constructed by
replicating execution resources. This enables parallel
execution of instructions in parallel pipelines, so long as
hazards are avoided.
 Simultaneous multithreading (SMT): Register banks are
replicated so that multiple threads can share the use of
pipeline resources.

18.2 Give several reasons for the choice by designers to move to

a multicore organization rather than increase parallelism within a
single processor.
Ans. In the case of pipelining, simple 3-stage pipelines were
replaced by pipelines with 5 stages, and then many more stages,
with some implementations having over a dozen stages. There is
a practical limit to how far this trend can be taken, because with
more stages, there is the need for more logic, more
interconnections, and more control signals. 
With superscalar organization, performance increases can be
achieved by increasing the number of parallel pipelines. Again,
there are diminishing returns as the number of pipelines
increases. More logic is required to manage hazards and to stage
instruction resources. Eventually, a single thread of execution
reaches the point where hazards and resource dependencies
prevent the full use of the multiple pipelines available. This same
point of diminishing returns is reached with SMT, as the
complexity of managing multiple threads over a set of pipelines
limits the number of threads and number of pipelines that can be
effectively utilized.

18.3 Why is there a trend toward giving an increasing fraction of

chip area to cache memory?
Ans. The growing trend towards giving an increasing fraction of
chip area to cache memory is mainly due to the fact that Cache
memory uses less power than logic. This makes it an efficient
option to use in chip design.
18.4 List some examples of applications that benefit directly from
the ability to scale throughput with the number of cores.
Ans.
1. Multi-threaded native applications: Multi-threaded
applications are characterized by having a small number of
highly threaded processes. Examples of threaded
applications include Lotus Domino or Siebel CRM (Customer
Relationship Manager).
2. Multi-process applications: Multi-process applications are
characterized by the presence of many single-threaded
processes. Examples of multi-process applications include
the Oracle database, SAP, and PeopleSoft. 
3. Java applications: Java applications embrace threading in a
fundamental way. Not only does the Java language greatly
facilitate multithreaded applications, but the Java Virtual
Machine is a multi-threaded process that provides
scheduling and memory management for Java applications.
Java applications that can benefit directly from multicore
resources include application servers such as Sun’s Java
Application Server, BEA’s Weblogic, IBM’s Websphere, and
the open-source Tomcat application server. All applications
that use a Java 2 Platform, Enterprise Edition (J2EE platform)
application server can immediately benefit from multicore
technology.
4. Multi-instance applications: Even if an individual
application does not scale to take advantage of a large
number of threads, it is still possible to gain from multicore
architecture by running multiple instances of the application
in parallel. If multiple application instances require some
degree of isolation, virtualization technology (for the
hardware of the operating system) can be used to provide
each of them with its own separate and secure environment.
18.5 At a top level, what are the main design variables in a
multicore organization?
Ans.
The main design variables in a multicore organization are;
1. The number of core processors on the chip
2. The number of levels of cache memory
3. The amount of cache memory that is shared

18.6 List some advantages of a shared L2 cache among cores

compared to separate dedicated L2 caches for each core.
Ans.
1. Constructive interference can reduce overall miss rates.
That is, if a thread on one core accesses a main memory
location, this brings the frame containing the referenced
location into the shared cache. If a thread on another core
soon thereafter accesses the same memory block, the
memory locations will already be available in the shared on-
chip cache.
2. A related advantage is that data shared by multiple cores
is not replicated at the shared cache level.
3. With proper frame replacement algorithms, the amount of
shared cache allocated to each core is dynamic, so that
threads that have a less locality can employ more cache.
4. Interprocessor communication is easy to implement, via
shared memory locations.
5. The use of a shared L2 cache confines the cache coherency
problem to the L1 cache level, which may provide
some additional performance advantage.