DSP AND MULTICORE PROCESSORS

DSP:
Digital Signal Processors are powerful special purpose 8/16/32 bit
microprocessor designed to meet the computational demands and powerful
constraints of today’s embedded studio, video and communication
applications.
1. DSP are 2 to 3 times faster than the general purpose microprocessor in
signal processing applications. This is because of the architectural difference
between the two.
2. DSPs implement algorithms in hardware which speeds up the execution,
depends primarily on the clock for the processor.
3. DSP can be viewed as a microchip designed for performing high sped
computational operations for addition, subtraction and division.
4. DSP unit having the following key units - Computational Engine, Program
Memory, Data memory and I/O units

Applications of DSP:
1. Audio video signal processing
2. Telecommunication
3. Multimedia
4. Applications where processing of large amount of real time calculations
are required
Multicore Processor
 It is an integrated circuit in which two or more processor cores have been
packaged for enhanced performance, reduced power consumption and
more efficient simultaneous multitasking.
 Here, a single physical processor contains the core logic of two or more
processor and these processors are packaged into a single integrated
circuit.
 The multicore technology is mainly used for parallel computing which
increases computer speed and efficiency.
 Multicore processors will give the benefits to software using multithreaded
program.
 Applications: Mobile devices, desktops, workstations and servers.
 Harvard and Von-Neumann Architecture
Sr. Von Neumann Architecture Harvard Architecture
1

2 The Van Neumann architecture uses The Harvard architecture uses

single memory for their instructions physically separate memories for
and data. their instructions and data.
3 Requires single bus for instructions Requires separate & dedicated
and data buses for memories for
instructions and data.
4 Its design is simpler Its design is complicated
5 Instructions and data have to be Instructions and data can be
fetched in sequential order limiting fetched simultaneously as there is
the operation bandwidth. separate buses for instruction and
data which increasing operation
bandwidth.
6 Program segments & memory blocks Vectors & pointers, variables
for data & stacks have separate sets program segments & memory
of addresses. blocks for data & stacks have
different addresses in the
program.
7 Examples of Von – Neumann Examples of Harvard
Architecture: Architecture: 8051, ARM 9, AVR
ARM 7 and Pentium Processors etc. by Atmel Corporation and PIC
microcontrollers by microchip
Comparison (or Differences) of RISC and CISC architecture:

Aspect RISC CISC

Acronym Reduced Instruction Set Complex Instruction Set
Computer Computer
Instruction set Reduced and not Flexible. Complex and Flexible.
Each instruction needs Each instruction needs
few bus cycles many bus cycles
Program Size Long Short
Addressing Modes Few Many
No. of Registers Large Less
Processor Hardware Simple Complex
External Memory Accessed rarely Accessed frequently
Instructions Shorter so execution is Lengthy so execution is
faster slower
Compiler design Easy to design Hard to design
Hardware/Software Stresses more on software Stresses more on hardware
Memory Memory-to memory Register-to register
management operations Operations
Code size High in code size Less in code size
Clocking Single clock is used Multiple clocks are used
Instruction length Single word instruction Variable Length instruction
Pipelining Pipelining is the major Doesn’t support pipelining
feature
Examples ARM, ATMEL, AVR, MIPS, Interx86, Motorola, 68000
PIC, POWER PC, series.
SUNSPARC etc.
 Class: TY (IE) 2016-17 Subject: Embedded Systems (17658)
QUESTION BANK BASED ON CHAPTER NO. 1
Topic Weightage: 8 % Submission Date: 30th Dec. 2016

Winter 2016: EMS (17658)

1. Draw the architecture of 89C51 microcontroller
2. Describe DSP and multicore processor in brief.
3. Differentiate between Harvard and Von Neumann architecture with suitable
diagram.
Summer 2016: EMS (17658)
1. State four differences between RISC and CISC architectures.
2. Draw the format of TMOD. Describe the function of each bit.
3. Draw the format of SCON register and explain all the bits
 Winter 2015: EMS (17658)
1. List ports of 89C51 microcontroller and list alternative functions of port-3 pins.
2. Draw the internal data memory structure of 89C51 and describe register banks.
3. List the interrupts of 89c51 microcontroller with their vector locations and order
of priority.

Summer 2015: EMS (17658)

1. Compare RISC and CISC architecture.
2. Explain DSP in brief. State any two applications.
3. List various SFRs needed for serial communication using microcontroller 89C51.
Also list various baud rates for serial communication.
 Winter 2014: EDD (12269)
1. State the alternative function of port 3 pins.
2. Draw and explain SCON SFR used in 8051 microcontroller.
3. With suitable diagram explain port 0 of 8051 microcontroller.

Summer 2014: EDD (12269)

1. Draw diagram of port 3 of 8051 microcontroller and list alternate functions of
port 3 pins.
2. States interrupts in 8051 microcontroller and give their priority upon reset.
Summer 2013: EDD (12269)
1. List ports available in 8051 microcontroller. Give alternate function of port 3.
2. Explain the ports of 8051 microcontroller used for External memory access
3. Describe dual role of port 0 in 8051 microcontroller.