High Performance Current Mode Controllers: Semiconductor Technical Data
High Performance Current Mode Controllers: Semiconductor Technical Data
High Performance Current Mode Controllers: Semiconductor Technical Data
The MC34129/MC33129 are high performance current mode switching
HIGH PERFORMANCE
regulators specifically designed for use in low power digital telephone CURRENT MODE
applications. These integrated circuits feature a unique internal fault timer
that provides automatic restart for overload recovery. For enhanced system
CONTROLLERS
efficiency, a start/run comparator is included to implement bootstrapped SEMICONDUCTOR
operation of VCC. Other functions contained are a temperature compensated TECHNICAL DATA
reference, reference amplifier, fully accessible error amplifier, sawtooth
oscillator with sync input, pulse width modulator comparator, and a high
current totem pole driver ideally suited for driving a power MOSFET.
Freescale Semiconductor, Inc...
Error Amp
9 Noninverting ORDERING INFORMATION
+ Input
6 10
X2 – Inverting Operating
Vref 2.5V
Input Device Temperature Range Package
Latching 11
Feedback/
PWM
1 PWM Input MC34129D
TA = 0° to +70°C
SO–14
5 Drive Out Plastic DIP
RT/CT Oscillator MC34129P
2
Drive Gnd MC33129D SO–14
Sync/Inhibit 4 3 TA = – 40° to +85°C
Input Ramp Input MC33129P Plastic DIP
100 pF
200 k 20
100 k
50 k 5.0
20 k 2.0 VCC = 10 V
100pF
TA = 25°C
CT = 5.0 nF 2.0 nF 1.0 nF 500 pF 200 pF
10 k 1.0
5.0 10 20 50 100 200 500 5.0 10 20 50 100 200 500
fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz)
Freescale Semiconductor, Inc...
Figure 3. Oscillator Frequency Change Figure 4. Error Amp Open Loop Gain and
versus Temperature Phase versus Frequency
∆ f OSC, OSCILLATOR FREQUENCY CHANGE (%)
60 0
8.0 VCC = 10 V A VOL , OPEN LOOP VOLTAGE GAIN (dB) VCC = 10 V
RT = 25.5 k VO = 1.25 V
20 Phase
0 90
–4.0
0 135
–8.0
–20 180
–55 –25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M 10 M
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz)
TA = 25°C TA = 25°C
1.05 V 1.5 V
200 mV/DIV
20 mV/DIV
1.0 V 1.0 V
0.95 V 0.5 V
Figure 7. Error Amp Open Loop DC Gain Figure 8. Error Amp Output Saturation
versus Load Resistance versus Sink Current
90 1.0
VCC = 10 V
Pins 8 to 9, 6 to 10
0.8 Pins 2, 5, 7 to Gnd
80
TA = 25°C
0.6
70
0.4
60 VCC = 10 V
VO = 1.25 V 0.2
RL to 1.25 Vref
TA = 25°C
50 0
0 20 40 60 80 100 0 2.0 4.0 6.0 8.0
RL, OUTPUT LOAD RESISTANCE (kΩ) ISink, OUTPUT SINK CURRENT (mA)
Freescale Semiconductor, Inc...
Figure 9. Soft–Start Buffer Output Saturation Figure 10. Reference Output Voltage versus
versus Sink Current Supply Voltage
1.0 3.2
TA = 25°C
VCC = 10 V Vref 2.5 V, RL = 2.5 k
Pins 8 to 9
0.8 2.4
Pins 2, 5, 7, 10, 12 to Gnd
TA = 25°C
0.6
1.6 Vref 1.25 V, RL = ∞
0.4
0.8
0.2
0 0
0 100 200 300 400 500 0 4.0 8.0 12 16
ISink, OUTPUT SINK CURRENT (µA) VCC, SUPPLY VOLTAGE (V)
Figure 11. 1.25 V Reference Output Voltage Figure 12. 2.5 V Reference Output Voltage
∆ V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)
–8.0 –8.0
–20 –20
–24 –24
0 2.0 4.0 6.0 8.0 10 0 0.4 0.8 1.2 1.6 2.0
Iref, REFERENCE OUTPUT SOURCE CURRENT (mA) Iref, REFERENCE OUTPUT SOURCE CURRENT (mA)
Figure 13. 1.25 V Reference Output Voltage Figure 14. 2.5 V Reference Output Voltage
∆ V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)
–2.0 4.0
–4.0 8.0
–6.0 –12
VCC = 10 V VCC = 10 V
RL = ∞ RL = 2.5 k
–8.0 *Vref at TA = 25°C –16 *Vref at TA = 25°C
–10 –20
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
Freescale Semiconductor, Inc...
VCC VCC = 10 V 10 RL =
–1.0 TA = 25°C CL = 500 pF
TA = 25°C
–2.0 Source Saturation
(Load to Ground)
2.0 V/DIV
–3.0
1.0 0
Gnd
0
0 200 400 600 800 1.0 µs/DIV
IO, OUTPUT LOAD CURRENT (mA)
CT = 390 pF
8.0 TA = 25°C
6.0
4.0
CL = 500 pF
2.0
CL = 15 pF
0
0 4.0 8.0 12 16
VCC, SUPPLY VOLTAGE (V)
2 Drive Ground This pin is a separate power ground return that is connected back to the power source. It is
used to reduce the effects of switching transient noise on the control circuitry.
3 Ramp Input A voltage proportional to the inductor current is connected to this input. The PWM uses this
information to terminate output switch conduction.
4 Sync/Inhibit Input A rectangular waveform applied to this input will synchronize the Oscillator and limit the
maximum Drive Output duty cycle. A dc voltage within the range of 2.0 V to VCC will inhibit
the controller.
5 RT/CT The free–running Oscillator frequency and maximum Drive Output duty cycle are
programmed by connecting resistor RT to Vref 2.5 V and capacitor CT to Ground. Operation
to 300 kHz is possible.
6 Vref 2.50 V This output is derived from Vref 1.25 V. It provides charging current for capacitor CT through
resistor RT.
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7 Ground This pin is the control circuitry ground return and is connected back to the source ground.
8 Vref 1.25 V This output furnishes a voltage reference for the Error Amplifier noninverting input.
9 Error Amp Noninverting Input This is the noninverting input of the Error Amplifier. It is normally connected to the 1.25 V
reference.
10 Error Amp Inverting Input This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.
11 Feedback/PWM Input This pin is available for loop compensation. It is connected to the Error Amplifier and
Soft–Start Buffer outputs, and the Pulse Width Modulator input.
12 CSoft–Start A capacitor CSoft–Start is connected from this pin to Ground for a controlled ramp–up of peak
inductor current during startup.
13 Start/Run Output This output controls the state of an external bootstrap transistor. During the start mode,
operating bias is supplied by the transistor from Vin. In the run mode, the transistor is
switched off and bias is supplied by an auxiliary power transformer winding.
14 VCC This pin is the positive supply of the control IC. The controller is functional over a minimum
VCC range of 4.2 V to 12 V.
generates an internal blanking pulse that holds the lower increments is shown in Figure 22. This method is possible
input of the NOR gate high. This causes the Drive Output to because the Ramp Input bias current is always negative
be in a low state, thus producing a controlled amount of (typically –120 µA). A positive temperature coefficient equal
output deadtime. Figure 1 shows Oscillator Frequency to that of the diode string will be exhibited by Ipk(max). An
versus RT and Figure 2 Output Deadtime versus Frequency, adjustable method that is more precise and temperature
both for given values of CT. Note that many values of RT and stable is shown in Figure 23. Erratic operation due to noise
CT will give the same oscillator frequency but only one pickup can result if there is an excessive reduction of the
combination will yield a specific output deadtime at a give clamp voltage. In this situation, high frequency circuit layout
frequency. In many noise sensitive applications it may be techniques are imperative.
desirable to frequency–lock one or more switching regulators A narrow spike on the leading edge of the current
to an external system clock. This can be accomplished by waveform can usually be observed and may cause the power
applying the clock signal to the Synch/Inhibit Input. For supply to exhibit an instability when the output is lightly
reliable locking, the free–running oscillator frequency should loaded. This spike is due to the power transformer
be about 10% less than the clock frequency. Referring to the interwinding capacitance and output rectifier recovery time.
timing diagram shown Figure 19, the rising edge of the clock The addition of an RC filter on the Ramp Input with a time
signal applied to the Sync/Inhibit Input, terminates charging constant that approximates the spike duration will usually
of CT and Drive Output conduction. By tailoring the clock eliminate the instability; refer to Figure 25.
waveform, accurate duty cycle clamping of the Drive Output
can be achieved. A circuit method is shown in Figure 20. The Error Amp and Soft–Start Buffer
Sync/Inhibit Input may also be used as a means for system A fully–compensated Error Amplifier with access to both
shutdown by applying a dc voltage that is within the range of inputs and output is provided for maximum design flexibility.
2.0 V to VCC. The Error Amplifier output is common with that of the
Soft–Start Buffer. These outputs are open–collector (sink
PWM Comparator and Latch only) and are ORed together at the inverting input of the PWM
The MC34129 operates as a current mode controller Comparator. With this configuration, the amplifier that
whereby output switch conduction is initiated by the oscillator demands lower peak inductor current dominates control of
and terminated when the peak inductor current reaches a the loop. Soft–Start is mandatory for stable startup when
threshold level established by the output of the Error Amp or power is provided through a high source impedance such as
Soft–Start Buffer (Pin 11). Thus the error signal controls the the long twisted pair used in telecommunications. It
peak inductor current on a cycle–by–cycle basis. The PWM effectively removes the load from the output of the switching
Comparator–Latch configuration used, ensures that only a power supply upon initial startup. The Soft–Start Buffer is
single pulse appears at the Drive Output during any given configured as a unity gain follower with the noninverting input
oscillator cycle. The inductor current is converted to a voltage connected to Pin 12. An internal 1.0 µA current source
by inserting the ground–referenced resistor RS in series with charges the soft–start capacitor (CSoft–Start) to an internally
the source of output switch Q1. The Ramp Input adds an clamped level of 1.95 V. The rate of change of peak inductor
offset of 275 mV to this voltage to guarantee that no pulses current, during startup, is programmed by the capacitor value
appear at the Drive Output when Pin 11 is at its lowest state. selected. Either the Fault Timer or the Undervoltage Lockout
This occurs at the beginning of the soft–start interval or when can discharge the soft–start capacitor.
the power supply is operating and the load is removed. The
+ 8
1.25V
7 – Reference
+
275mV 9 Noninverting
2.5V Reference + + Input
6 + 1.25V 10 Inverting
– Error Amp –
– Input
Freescale Semiconductor, Inc...
R VCC Feedback/PWM
Soft–Start 11 Input
Buffer
RT R Latch Q1
R 1 Drive Output
Q
225k
5
Oscillator S 2
CT Drive
Gnd
4 3
+ Sink Only
– = Positive True Logic
Sync/Inhibit Input
Capacitor CT
Latch
“Set” Input
Feedback/PWM Input
Ramp Input
Latch
“Reset” Input
Drive Output
20 V
Start/Run
Output
14.3 V
in a skip cycle or hiccup mode until either the load power or Drive Ground is provided to reduce the effects of switching
source impedance is reduced. The minimum fault timeout is transient noise imposed on the Ramp Input. This feature
200 µs, which limits the useful switching frequency to a becomes particularly useful when the Ipk(max) clamp level is
minimum of 5.0 kHz. reduced. Figure 24 shows the proper implementation of the
MC34129 with a current sensing power MOSFET.
Start/Run Comparator
A bootstrap startup circuit is included to improve system Undervoltage Lockout
efficiency when operating from a high input voltage. The The Undervoltage Lockout comparator holds the Drive
output of the Start/Run Comparator controls the state of an Output and CSoft–Start pins in the low state when VCC is less
external transistor. A typical application is shown in Figure 21. than 3.6 V. This ensures that the MC34129 is fully functional
While CSoft–Start is charging, startup bias is supplied to VCC before the output stage is enabled and a soft–start cycle
(Pin 14) from Vin through transistor Q2. When begins. A built–in hysteresis of 350 mV prevents erratic
CSoft–Start reaches the 1.95 V clamp level, the Start–Run output behavior as VCC crosses the comparator threshold
output switches low (VCC = 50 mV), turning off Q2. Operating voltage. A 14.3 V zener is connected as a shunt regulator
bias is now derived from the auxiliary bootstrap winding of the from VCC to ground. Its purpose is to protect the MOSFET
transformer, and all drive power is efficiently converted down gate from excessive drove voltage during system startup. An
from Vin. The start time must be long enough for the power external 9.1 V zener is required when driving low threshold
supply output to reach regulation. This will ensure that there MOSFETs. Refer to Figure 21. The minimum operating
is sufficient bias voltage at the auxiliary bootstrap winding for voltage range of the IC is 4.2 V to 12 V.
sustained operation.
References
1.95 V CSoft–Start The 1.25 V bandgap reference is trimmed to ±2.0%
tStart = = 1.95 CSoft–Start in µF
1.0 µA tolerance at TA = 25°C. It is intended to be used in
conjunction with the Error Amp. The 2.50 V reference is
The Start/Run Comparator has 350 mV of hysteresis. The derived from the 1.25 V reference by an internal op amp with
output off–state is clamped to VCC + 7.6 V by the internal a fixed gain of 2.0. It has an output tolerance of ±5.0% at TA =
zener and PNP transistor base–emitter junction. 25°C and its primary purpose is to supply charging current to
the oscillator timing capacitor.
Figure 20. External Duty Cycle Clamp Figure 21. Bootstrap Startup
and Multi–Unit Synchronization Vin
6 2.5V
+ + 13
– – Q2
CSoft–Start 14
–+ 9.1
12 +
5.0V V
5 8
7
+– 1.25V
RA OSC
8 4 9
+– +
RB 5.0k 6 2.5V –
+
4 +– 10
6 R
5 – 3 11
5.0k Q
R 1
2 + 7 Q
– S 5
OSC S 2
To Additional
5.0k MC1455 MC34129’s
C 4 3
1
Freescale Semiconductor, Inc...
1.44 RB
f= Dmax = The external 9.1 V zener is required when driving low threshold MOSFETs.
(RA + 2RB)C RA + 2RB
Figure 22. Discrete Step Reduction of Clamp Level Figure 23. Adjustable Reduction of Clamp Level
Vin
Vin 8
8 1.25V
1.25V 9
9 + + +
+ + 275mV 10
275mV
+ – – R2
– 10
–
11
11
R1
Q1
Q1 R 1
R 1 Q
Q S 2
S 2
3
3 D1 D2
RS
≈ 120µA RS
1.25
1.675 – (VF(D1) + VF(D2)) – 0.275
Ipk(max) = R2
RS +1
R1
1.25 V
If: ≥ 1.0 mA Then: Ipk(max) ≈
R1 + R2 RS
Figure 24. Current Sensing Power MOSFET Figure 25. Current Waveform Spike Suppression
2
1 S
G K 3 R
M
2
C RS
3
Power Ground:
To Input Source
RS Return
1/4W
The addition of the RC filter will eliminate instability caused by the
Control Circuitry Ground: leading edge spike on the current waveform.
Freescale Semiconductor, Inc...
To Pin 7
Figure 26. MOSFET Parasitic Oscillations Figure 27. Bipolar Transistor Drive
IB
Vin
Vin +
0 t
– Base Charge
Removal
Q1
1 Rg C1
1
Q1
2
2
3
3
RS
RS
Series gate resistor Rg will damp any high frequency parasitic The totem–pole output can furnish negative base current for enhanced
oscillations caused by the MOSFET input capacitance and any transistor turn–off, with the addition of capacitor C1.
series wiring inductance in the gate–source circuit.
14 1N4148
12 +
– + 10 1N5819
5V/125mA
1N958A T1
0.1 +
+ 8 36k 100
1.25V R2
7 –
9 Gnd
+ +
10
– –
6 2.5 V +
+ 12k 100
500pF
– R1
Freescale Semiconductor, Inc...
11
–5V/20mA
24k
1 1N5819
R
Q MTP
5
2 2N20L
OSC S
470pF
T1: Coilcraft #G6807–A
4 3
Primary = 90T #28 AWG
Secondary ±5V = 26T #30 AW
128kHz 10
Gap = 0.05 n, for Lp of 600 µH
Sync
Core = Ferroxcube 813E187–3C8
Bobbin = Ferroxcube E187PCB1–8
R2
Vout = 1.25 +1
R1
5 Q MTP
Freescale Semiconductor, Inc...
OSC S 2 2N20
470pF
4 3
128kHz
Sync
100pF
2.7k 100
0.1
1 6
10k
T1: Primary = 35T #32 AWG
Feedback = 12T #32 AWG
4 Secondary ±5 V = 7T #32 AWG
Gap = 0.004″, for Lp of 180 µH
2 5 Core = Ferroxcube 813E187–3C8
MOC5007
Bobbin = Ferroxcube E187PCB1–8
Figure 30. Isolated 3.0 W Flyback Regulator with Secondary Side Sensing
Vin = 12V
L1
+ 13 1N5821 5/60mA
–
3.9k
14
12 51
100 + 1/2 +
4N26 100
470
0.1 0.1
+ 8
3.9k
7 – 1.25V
9
+ +
– – D TL431A Return
6 2.5V + 10
– MTP10N10M
11
2.2k
15k
R 1 G S
Q
Freescale Semiconductor, Inc...
5 M K
OSC S 2
Lp = 50 µH
0.001
1/2
200
Core = Ferroxcube
4N26 2616PA100–3C8
L1: Bobbin = Ferroxcube 2616F1D
Coilcraft Z7156, 15 µH
An economical method of achieving secondary sensing is to combine the TL431A with a 4N26 optocoupler.
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14) NOTES:
ISSUE F 1. DIMENSIONING AND TOLERANCING PER
–A– ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019
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