block_config::= component ID [is]

for LABELID [generic ( {ID : TYPEID [:= expr];} );]

[{block_config | comp_config}] [port ({ID : in | out | inout TYPEID [:= expr];});]
end for; end component [COMPID];
comp_config::= [impure | pure] function ID
for all | LABELID : COMPID [( {[constant | variable | signal | file] ID :
(use entity [LIBID.]ENTITYID [( ARCHID )] in | out | inout TYPEID [:= expr];})]
[[generic map ( {GENID => expr ,} )] return TYPEID [is
port map ({PORTID => SIGID | expr ,})]; begin
[for ARCHID {sequential_statement}
[{block_config | comp_config}] end [function] ID];
VHDL QUICK end for;]
end for;) |
procedure ID[({[constant | variable | signal] ID :
in | out | inout TYPEID [:= expr];})]
REFERENCE CARD (use configuration [LIBID.]CONFID
[[generic map ({GENID => expr ,})]
[is begin
Revision 2.1 [{sequential_statement}]
port map ({PORTID => SIGID | expr,})];) end [procedure] ID];
() Grouping [] Optional end for;
{} Repeated | Alternative for LABELID | others | all : COMPID use
bold As is CAPS User Identifier 2. DECLARATIONS (entity [LIBID.]ENTITYID [( ARCHID )]) |
italic VHDL-1993 (configuration [LIBID.]CONFID)
2.1. TYPE DECLARATIONS [[generic map ( {GENID => expr,} )]
port map ( {PORTID => SIGID | expr,} )];
1. LIBRARY UNITS type ID is ( {ID,} );
[{use_clause}] type ID is range number downto | to number; 3. EXPRESSIONS
entity ID is type ID is array ( {range | TYPEID ,}) of TYPEID;
[generic ({ID : TYPEID [:= expr];});] expression ::=
[port ({ID : in | out | inout TYPEID [:= expr];});] type ID is record (relation and relation) | (relation nand relation) |
[{declaration}] {ID : TYPEID;} (relation or relation) | (relation nor relation) |
[begin end record; (relation xor relation) | (relation xnor relation)
{parallel_statement}] type ID is access TYPEID; relation ::= shexpr [relop shexpr]
end [entity] ENTITYID; type ID is file of TYPEID; shexpr ::= sexpr [shop sexpr]
[{use_clause}] subtype ID is SCALARTYPID range range; sexpr ::= [+|-] term {addop term}
architecture ID of ENTITYID is
[{declaration}] subtype ID is ARRAYTYPID( {range,}); term ::= factor {mulop factor}
begin subtype ID is RESOLVFCTID TYPEID; factor ::=
[{parallel_statement}] range ::= (prim [** prim]) | (abs prim) | (not prim)
end [architecture] ARCHID; (integer | ENUMID to | downto integer | ENUMID) | prim ::=
[{use_clause}] (OBJID’[reverse_]range) | (TYPEID range <>) literal | OBJID | OBJID’ATTRID | OBJID({expr,})
package ID is | OBJID(range) | ({[choice [{| choice}] =>] expr,})
[{declaration}] 2.2. OTHER DECLARATIONS | FCTID({[PARID =>] expr,}) | TYPEID’(expr) |
end [package] PACKID; constant ID : TYPEID := expr; TYPEID(expr) | new TYPEID[‘(expr)] | ( expr )
[{use_clause}] [shared] variable ID : TYPEID [:= expr]; choice ::= sexpr | range | RECFID | others
package body ID is signal ID : TYPEID [:= expr];
[{declaration}] 3.1. OPERATORS, INCREASING PRECEDENCE
end [package body] PACKID; file ID : TYPEID (is in | out string;) | logop and | or | xor | nand | nor | xnor
(open read_mode | write_mode | relop = | /= | < | <= | > | >=
[{use_clause}]
append_mode is string;) shop sll | srl | sla | sra | rol | ror
configuration ID of ENTITYID is
for ARCHID alias ID : TYPEID is OBJID; addop +|-|&
[{block_config | comp_config}] attribute ID : TYPEID; mulop * | / | mod | rem
end for; miscop ** | abs | not
attribute ATTRID of OBJID | others | all : class is expr;
end [configuration] CONFID;
class ::=
use_clause::=
entity | architecture | configuration | © 1995-1998 Qualis Design Corporation. Permission to
library ID;
procedure | function | package | type | reproduce and distribute strictly verbatim copies of this
[{use LIBID.PKGID[. all | DECLID];}]
subtype | constant | signal | variable | document in whole is hereby granted.
component | label
See reverse side for additional information.
© 1995-1998 Qualis Design Corporation © 1995-1998 Qualis Design Corporation
4. SEQUENTIAL STATEMENTS [LABEL:] [postponed] SIGID <= SIGID’driving Active driver predicate
[transport] | [[reject TIME] inertial] SIGID’driving_value Value of driver
wait [on {SIGID,}] [until expr] [for time]; [{{expr [after TIME,]} | unaffected when expr else}] OBJID’simple_name Name of object
assert expr {expr [after TIME,]} | unaffected; OBJID’instance_name Pathname of object
[report string] OBJID’path_name Pathname to object
[LABEL:] [postponed] with expr select
[severity note | warning | error | failure];
SIGID <= [transport] | [[reject TIME] inertial]
report string {{expr [after TIME,]} | unaffected 7. PREDEFINED TYPES
[severity note | warning | error | failure]; when choice [{| choice}]}; BOOLEAN True or false
SIGID <= [transport] | [[reject TIME] inertial] LABEL: COMPID INTEGER 32 or 64 bits
{expr [after time],}; [[generic map ( {GENID => expr,} )] NATURAL Integers >= 0
port map ( {[PORTID =>] SIGID | expr,} )]; POSITIVE Integers > 0
VARID := expr;
REAL Floating-point
PROCEDUREID[({[PARID =>] expr,})]; LABEL: entity [LIBID.]ENTITYID [(ARCHID)]
BIT ‘0’, ‘1’
[[generic map ( {GENID => expr,} )]
[LABEL:] if expr then BIT_VECTOR(NATURAL) Array of bits
port map ( {[PORTID =>] SIGID | expr,} )];
{sequential_statement} CHARACTER 7-bit ASCII
[{elsif expr then LABEL: configuration [LIBID.]CONFID STRING(POSITIVE) Array of characters
{sequential_statement}}] [[generic map ( {GENID => expr,} )] TIME hr, min, sec, ms,
[else port map ( {[PORTID =>] SIGID | expr,} )]; us, ns, ps, fs
{sequential_statement}] LABEL: if expr generate DELAY_LENGTH Time >= 0
end if [LABEL]; [{parallel_statement}]
[LABEL:] case expr is end generate [LABEL]; 8. PREDEFINED FUNCTIONS
{when choice [{| choice}] => LABEL: for ID in range generate NOW Returns current simulation time
{sequential_statement}} [{parallel_statement}] DEALLOCATE(ACCESSTYPOBJ)
end case [LABEL]; end generate [LABEL]; Deallocate dynamic object
[LABEL:] [while expr] loop FILE_OPEN([status], FILEID, string, mode)
{sequential_statement} 6. PREDEFINED ATTRIBUTES Open file
end loop [LABEL]; FILE_CLOSE(FILEID) Close file
TYPID’base Base type
[LABEL:] for ID in range loop TYPID’left Left bound value
9. LEXICAL ELEMENTS
{sequential_statement} TYPID’right Right-bound value
end loop [LABEL]; TYPID’high Upper-bound value Identifier ::= letter { [underline] alphanumeric }
next [LOOPLBL] [when expr]; TYPID’low Lower-bound value decimal literal ::= integer [. integer] [E[+|-] integer]
TYPID’pos(expr) Position within type
exit [LOOPLBL] [when expr]; based literal ::=
TYPID’val(expr) Value at position
integer # hexint [. hexint] # [E[+|-] integer]
return [expression]; TYPID’succ(expr) Next value in order
TYPID’pred(expr) Previous value in order bit string literal ::= B|O|X “ hexint “
null;
TYPID’leftof(expr) Value to the left in order comment ::= -- comment text
TYPID’rightof(expr) Value to the right in order
5. PARALLEL STATEMENTS
TYPID’ascending Ascending type predicate
LABEL: block [is] TYPID’image(expr) String image of value
[generic ( {ID : TYPEID;} ); TYPID’value(string) Value of string image
[generic map ( {[GENID =>] expr,} );]] ARYID’left[(expr)] Left-bound of [nth] index
[port ( {ID : in | out | inout TYPEID } ); ARYID’right[(expr)] Right-bound of [nth] index
[port map ( {[PORTID =>] SIGID | expr,} )];] ARYID’high[(expr)] Upper-bound of [nth] index
[{declaration}] ARYID’low[(expr)] Lower-bound of [nth] index
begin ARYID’range[(expr)] ‘left down/to ‘right
[{parallel_statement}] ARYID’reverse_range[(expr)] ‘right down/to ‘left © 1995-1998 Qualis Design Corporation. Permission to
end block [LABEL]; ARYID’length[(expr)] Length of [nth] dimension reproduce and distribute strictly verbatim copies of this
[LABEL:] [postponed] process [( {SIGID,} )] ARYID’ascending[(expr)] ‘right >= ‘left ? document in whole is hereby granted.
[{declaration}] SIGID’delayed[(TIME)] Delayed copy of signal
SIGID’stable[(TIME)] Signals event on signal Qualis Design Corporation
begin
[{sequential_statement}] SIGID’quiet[(TIME)] Signals activity on signal Elite Consulting and Training in High-Level Design
end [postponed] process [LABEL]; SIGID’transaction Toggles if signal active
Phone: +1-503-670-7200 FAX: +1-503-670-0809
SIGID’event Event on signal ?
[LBL:] [postponed] PROCID({[PARID =>] expr,}); E-mail: [email protected] com
SIGID’active Activity on signal ?
[LABEL:] [postponed] assert expr Web: http://www.qualis.com
SIGID’last_event Time since last event
[report string] SIGID’last_active Time since last active Also available: 1164 Packages Quick Reference Card
[severity note | warning | error | failure]; SIGID’last_value Value before last event Verilog HDL Quick Reference Card
© 1995-1998 Qualis Design Corporation © 1995-1998 Qualis Design Corporation