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VHDL Code MUX and DeMUX PDF

The document contains VHDL code for a 4:1 multiplexer and a 1:4 demultiplexer. The 4:1 multiplexer code uses two select signals S0 and S1 to choose between four input signals A, B, C, and D and output the selected signal to Z. The 1:4 demultiplexer code uses the same two select signals to route the single input signal F to one of the four output signals A, B, C, or D.

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Abdul Rehman
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268 views2 pages

VHDL Code MUX and DeMUX PDF

The document contains VHDL code for a 4:1 multiplexer and a 1:4 demultiplexer. The 4:1 multiplexer code uses two select signals S0 and S1 to choose between four input signals A, B, C, and D and output the selected signal to Z. The 1:4 demultiplexer code uses the same two select signals to route the single input signal F to one of the four output signals A, B, C, or D.

Uploaded by

Abdul Rehman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL Code for 4:1 Mux:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux_4to1 is
port(
A,B,C,D : in STD_LOGIC;
S0,S1: in STD_LOGIC;
Z: out STD_LOGIC
);
end mux_4to1;
architecture bhv of mux_4to1 is
begin
process (A,B,C,D,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
Z = A;
elsif (S0 ='1' and S1 = '0') then
Z = B;
elsif (S0 ='0' and S1 = '1') then
Z = C;
else
Z = D;
end if;
end process;
end bhv;
VHDL Code for 1:4 Demux:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demux_1to4 is
port(
F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end demux_1to4;
architecture bhv of demux_1to4 is
begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A = F;
elsif (S0 ='1' and S1 = '0') then
B = F;
elsif (S0 ='0' and S1 = '1') then
C = F;
else
D = F;
end if;
end process;
end bhv;

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