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DFT Interview Question2

The document contains 14 interview questions related to scan insertion, design verification, and simulation for an ASIC design flow. The questions cover topics such as the inputs and outputs of scan insertion, the tool used for scan insertion, the purpose of design rule checking, ASIC design flow stages including scan insertion, different types of fault models for ATPG including path delay and transition faults, fault classes for ATPG, types of simulation including serial and parallel, and why parallel simulation has a shorter runtime.
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0% found this document useful (0 votes)
424 views1 page

DFT Interview Question2

The document contains 14 interview questions related to scan insertion, design verification, and simulation for an ASIC design flow. The questions cover topics such as the inputs and outputs of scan insertion, the tool used for scan insertion, the purpose of design rule checking, ASIC design flow stages including scan insertion, different types of fault models for ATPG including path delay and transition faults, fault classes for ATPG, types of simulation including serial and parallel, and why parallel simulation has a shorter runtime.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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DFT INTERVIEW QUESTIONS – 2

1. What are the inputs to the scan insertion?


2. What are the outputs to the scan insertion?
3. Which tool you used for scan insertion?
4. Why design rule checking?
5. ASIC flow?
6. In that ASIC flow after block diagram team the design verification team will be
there. That design team will check all the scan flop connections. Then why we are
using scan insertion?
7. Do you have done scan compression?
8. Tell me the different type of fault models which are present in ATPG?
9. Explain the difference between path delay fault model and transition fault model?
10. Tell me the fault classes present in ATPG?
11. Do you have any knowledge on simulation?
12. Tell me the simulation types?
13. Explain the difference between serial and parallel simulation?
14. Why run time is less in parallel simulation?

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