This document contains definitions and abbreviations related to design for testability (DFT) techniques in digital circuit design. It defines terms like scan flip-flops, level sensitive scan design, test access port, automatic test pattern generation, and other scan-based testing concepts. Abbreviations cover tools, file formats, design languages, and concepts in digital circuit design and testing.
This document contains definitions and abbreviations related to design for testability (DFT) techniques in digital circuit design. It defines terms like scan flip-flops, level sensitive scan design, test access port, automatic test pattern generation, and other scan-based testing concepts. Abbreviations cover tools, file formats, design languages, and concepts in digital circuit design and testing.
This document contains definitions and abbreviations related to design for testability (DFT) techniques in digital circuit design. It defines terms like scan flip-flops, level sensitive scan design, test access port, automatic test pattern generation, and other scan-based testing concepts. Abbreviations cover tools, file formats, design languages, and concepts in digital circuit design and testing.
This document contains definitions and abbreviations related to design for testability (DFT) techniques in digital circuit design. It defines terms like scan flip-flops, level sensitive scan design, test access port, automatic test pattern generation, and other scan-based testing concepts. Abbreviations cover tools, file formats, design languages, and concepts in digital circuit design and testing.
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DFT Design for Testability
sdf stuck at fault
tdf transition fault sa0/se0 stuck at 0 sdff scanned D flipflop LSSD level sensitive D flipflop LEC logical equivalent Circuit (mathematical tool to check if added DFT changes any functionality) FV formality Verification (same as LEC) SI Scan In SO Scan Out TE/TM Test Mode/Test Enable SE Scan Enable ICG Integrated Clock Gating Cell ATE Automatic Test Equipment TCL Tool Command Language .db database(one format of library file) CTL Core Test Language(used in hierchiacal scan insertion) contains scan insertion info to th SCANDEF Scan Definition-report after scan insertion used in pd for scan chain reordering JTAG Joint Test Action Group BSR Boundary Scan Register BSDL Boundary Scan Design Language TAP Test Access Port TDI Test Data In TDO Test Data Out TMS Test Mode Select TRST Test Reset TCK Test Clock OCC On Chip Clock Controller PLL Phase Locked Loop BIST Built In Self Test MBIST Memory BIST LBIST Logic BIST PBIST Programmable BIST DC compiler Design Compiler EDT Embedded Determinstic Test IDDQ Quiescent Current .sdc Synopsys Design Constraints .spf STIL protocol File STIL Standard Test Interface Languange TB TestBench DRC Design Rule Check PVT processor, voltage, Temperature OCV On Chip Variation ATPG Automatic Test Pattern Generator DT Detected PT Possibly Detected AU ATPG untestable ND Not Detected UD Undetectable STA Static Timing Analysis DTA Dynamic Timing Analysis IEEE Institute For Electrical and Electronics Engineers REFCLK Reference Clock DPPM Defected Parts Per Million GUI Graphical User Interface DCT Design Compiler Topographical Mode NICE Next Instance must be Clocked Concurrently or Earlier (SCAN ORDERING BASED ON THIS R IP Intellectual Property HSS Hierarchial Scan Sythesis HASS Hierarchial Adaptive Scan Sythesis TATR Test Application Time Reduction TDVR Test Data Volume Reduction CMOS Complimentary Metal Oxide Semiconductor FPGA Field Programmable Gate Array ASIC Application Specfic Integrated Circuit CPLD Complex Programmable Logic Devices vhdl Very High Speed Integrated Circuit Hardware Description Language(VHSIC HDL) DEF Design Exchange Format CTS Clock Tree Synthesis TE/LE Trailing Edge/Leading Edge SoC System on Chip DUT Design Under Test UDTP User Defined Test Points GSV Graphical Schematic Viewer PnR place and route HDL Hardware Description Language .sv system verilog FSM Finite State Machine EOC End Of Cycle UPF unified Power Format SVF Setup Verification File RAM Random Access Memory ROM Read Only Memory hanges any functionality)
