01 ARM® Cortex® M Processors
01 ARM® Cortex® M Processors
Md Mahfudz Md Zan
Faculty of Electrical Engineering,
UiTM Shah Alam
Brief History of ARM® (1)
• 1983 – Acorn Computer Group launched Acorn RISC Management project
to design a processor after being inspired by Berkerley RISC processor.
• 1985 – April 26, ARM1 chip prototype was delivered with VLSI Technology
Inc as its silicon partner. ARM originally stands for Acorn RISC machine.
• ARM1 is based on ARMv1 instruction set architecture (ISA)
• ARMv1 is a 32‐bit RISC design
• 26‐bit address space
• 1986 – ARM2 chip released using ARMv2 ISA.
• First commercial version of the ARM architecture.
• 1989 – ARM3 was introduced based on ARMv2 ISA.
Brief History of ARM® (2)
• 1990 – Advanced RISC Machines Ltd. Formed as a spin out from Acorn
Computer Group.
• A joint venture between Apple Computers, Acorn Computer Group, and VLSI
Technology.
• 1991 – Introduced its first embedded core, ARM6 using ARMv3 ISA
• Featuring a full 32‐bit address and data buses.
• 1993 – ARM7 launched based on ARMv3 ISA
• Designed as an IP core and is sold to other semiconductor companies to be
implemented in their own chips.
• 1996 – ARM8 launched based on ARMv4 ISA
ARM® Based Microcontrollers (1)
• ARM does not make microcontrollers.
• ARM designs processors and various components that silicon
designers need and licenses these designs to various silicon design
companies including microcontroller vendors.
• Typically we call these designs “Intellectual Property” (IP) and the
business model is called IP licensing.
• In a typical microcontroller design, the processor takes only a small
part of the silicon area. The other areas are taken up by memories,
clock generation (e.g., PLL) and distribution logic, system bus, and
peripherals (hardware units like I/O interface units, communication
interface, timers, ADC, DAC, etc.)
ARM® Based Microcontrollers (2)
• The memory system, memory map,
peripherals, and operation characteristics
(e.g., clock speed and voltage) can be
completed differently from one
vendor/product to another.
ARM® Architecture and Family (1)
• The architectures are the specifications, i.e. the set of registers,
instructions and operation modes that should be supported by
implementations of the architecture.
• A family is a specific detailed implementation of an architecture, i.e.
the actual hardware details needed to create an ARM core.
• The ARM architectures are modular so families may implement only some
features of the architecture and not others. Families may also have extensions
not in the architecture.
• A core is a specific implementation of an architecture, i.e. the actual
blue‐print of the transistors and other discrete parts needed to create
a ARM CPU.
ARM® Architecture and Family (2)
A microcontroller might contain multiple ARM® IP products.
ARM® Architecture and Family (3)
• The Cortex‐M3 and Cortex‐M4 processors are based on ARMv7‐M architecture.
• Architecture version numbers are independent of processor names.
The Evolution of ARM® Processor Architecture
ARM® Architecture and Family (4)
ARM® Architecture and Family (5)
ARM® Architecture & Thumb® ISA (2)
Thumb® ISA (1)
• The Thumb® instruction set is a re‐encoded subset of the ARM®
instruction set.
• Every Thumb® instruction is encoded in 16 bits.
• Thumb® is designed to increase the performance of ARM® implementations
that use a 16‐bit or narrower memory data bus and to allow better code
density than provided by the ARM® instruction set.
• In the ARM7TDMI processor design, a mapping function is used to translate
Thumb® instructions into ARM® instructions for decoding so that only one
instruction decoder is needed.
• The ARM7TDMI can operate in the ARM® state, the default state, and also in the
Thumb® state.
• During operation, the processor switches between ARM® state and Thumb® state under
software control.
Thumb® ISA (2)
• Has some limitations, such as restrictions on the register choices for
operations, available addressing modes, or a reduced range of
immediate values for data or addresses.
• When the processor is executing Thumb® instructions, eight general‐purpose
integer registers are available, R0 to R7.
• Registers R8 to R12 , which are known as the high registers, can only be used
in conjunction with MOV, ADD, SUB and CMP.
• There is very limited access to R13 (SP), R14 (LR) and R15 (PC) and only
indirect access to the CPSR.
Thumb®‐2 ISA (1)
• Thumb®‐2 technology combine 16‐bit and 32‐bit instruction sets in one
operation state.
• Introduced a new superset of the Thumb® instructions
• Many as 32‐bit size instructions.
• Can handle most of the operations previously only possible in the ARM® instruction
set.
• However, have different instruction encoding to the ARM® instruction set.
• First introduced with ARM1156T‐2 processor in 2003.
• Has two operating states: ARM state and Thumb state
• In 2006, ARM® released the Cortex®‐M3 processor, which supports just the
Thumb® operation state.
• Does not support the ARM® instruction set.
Thumb®‐2 ISA (2)
• The most important difference between the Thumb® ISA and the ARM® ISA
is that most 32‐bit Thumb® instructions are unconditional, whereas almost
all ARM® instructions can be conditional.
• Conditional execution controls whether or not the core will execute an instruction.
• Most ARM® instructions have a condition attribute that determines if the core will
execute it based on the setting of the condition flags.
• There are 15 condition codes specified with a two‐letter suffix, such as EQ or CC, appended to
the mnemonic.
• Prior to execution, the processor compares the condition attribute with the
condition flags in the CPSR. If they match, then the instruction is executed; otherwise
the instruction is ignored.
• Assembly language syntax changed with introduction of Thumb®‐2.
• Resulted in a unified assembler language (UAL) that is syntactically the same for both
ARM® and Thumb®‐2.
The Cortex®‐M Processor Family (1)
• The Cortex®‐M processor family
• Cortex®‐M3 and Cortex®‐M4 are based on ARMv7‐M architecture.
• Both are high‐performance processors that are designed for microcontrollers.
The Cortex®‐M Processor Family (2)
• The Cortex®‐M3 processor was the first of the Cortex® generation of
processors, released by ARM in 2005.
• The Cortex®‐M4 processor was released in 2010.
• The Cortex®‐M3 and Cortex®‐M4 processors use a 32‐bit architecture.
• Internal registers in the register bank, the data path, and the bus
interfaces are all 32 bits wide.
• The Instruction Set Architecture (ISA) in the Cortex®‐M processors is
the Thumb®‐2 ISA which supports a mixture of 16‐bit and 32‐bit
instructions.
The Cortex®‐M Processor Family (3)
• Some features of Cortex®‐M3 and Cortex®‐M4 processors:
• Three‐stage pipeline design Harvard bus architecture with unified memory
space: instructions and data use the same address space
• 32‐bit addressing, supporting 4GB of memory space
• On‐chip bus interfaces based on ARM® AMBA (Advanced Microcontroller Bus
Architecture) Technology, which allow pipelined bus operations for higher
throughput.
• Sleep mode support and various low power features
• The ARM® Cortex®‐M processors are regarded as RISC (Reduced
Instruction Set Computer) processors.
• It has a rich instruction set and mixed instruction sizes which are closer to
CISC (Complex Instruction Set Computer) characteristics.
The Cortex®‐M Processor Family (4)
• Cortex®‐M0:
56 instructions
• Cortex®‐M4:
169 instructions
Cortex®‐M Software Development (1)
• A toolchain is a set of programming tools that is used to perform a complex
software development task or to create a software product.
• A collection of tools that are chained together to streamline the software production
process.
• A set of specialized programs (the “tool‐” ) applied sequentially (the “‐chain” ) in the
process of building software for a given language and platform.
• A software development toolchain may include the following components:
• Assembler ‐ converts assembly language into machine code
• Linker ‐ merges multiple files into a single program
• Compiler ‐ generates executable code from a program's source code
• Library ‐ a collection of code, such as an API, that allows the app to reference
prebuilt functions or other resources
• Debugger ‐ an optional tool that can help fix bugs during the final build steps
Cortex®‐M Software Development (2)
• The Keil® MDK‐ARM (Microcontroller Development Kit for ARM)
toolchain provides a complete development environment for all
Cortex®‐M‐based microcontrollers.
• The MDK‐ARM Core installation contains μVision IDE, compiler, and
debugger. Device and middleware support is added through software
packs.
Cortex®‐M Software Development (3)
• Keil® MDK includes Arm C/C++ Compiler with assembler, linker, and
highly optimized run‐time libraries that are tailored for optimum code
size and performance.
• The core toolchain does not contain any support for specific Cortex‐M
microcontrollers.
• Support for a specific family of Cortex‐M microcontrollers is installed through
a software pack system.
• The pack installer allows selecting and installing support for a family of
microcontrollers.
• Once selected, a “Device Family Pack” will be downloaded from a Pack
Repository website and installed into the toolchain.
Cortex®‐M Software Development (3)
• Software Packs may be added any time to MDK‐Core making new
device support and middleware updates independent from the
toolchain.
• They contain device support, Cortex Microcontroller Software Interface
Standard (CMSIS) libraries, middleware, board support, code templates, and
example projects.
The End