Lecture 1:

Circuits &
Layout
 Complementary CMOS
❑ Complementary CMOS logic gates
– nMOS pull-down network pMOS

– pMOS pull-up network pull-up

network
inputs
– a.k.a. static CMOS output

nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 2

 Series and Parallel
❑
a a a a
nMOS: 1 = ON g1
a
0 0 1 1

❑
g2
pMOS: 0 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

❑ Series: both must be ON a a a a a

❑ Parallel: either can be ON g1

g2
0

0
0

1
1

0
1

1
b b b b b
(b) ON OFF OFF OFF

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF

1: Circuits & Layout CMOS VLSI Design 4th Ed. 3

Conduction Complement
❑ Complementary CMOS gates always produce 0 or 1
❑ Ex: NAND gate
– Series nMOS: Y=0 when both inputs are 1
– Thus Y=1 when either input is 0
– Requires parallel pMOS Y
A
B
❑ Rule of Conduction Complements
– Pull-up network is complement of pull-down
– Parallel -> series, series -> parallel

1: Circuits & Layout CMOS VLSI Design 4th Ed. 4

 Compound Gates
❑ Compound gates can do any inverting function
❑ Ex: Y = A B + C D (AND-AND-OR-INVERT, AOI22)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)

1: Circuits & Layout CMOS VLSI Design 4th Ed. 5

 Example: O3AI
❑ Y = ( A+ B + C) D

A
B
C D
Y
D
A B C

1: Circuits & Layout CMOS VLSI Design 4th Ed. 6

 Signal Strength
❑ Strength of signal
– How close it approximates ideal voltage source
❑ VDD and GND rails are strongest 1 and 0
❑ nMOS pass strong 0
– But degraded or weak 1
❑ pMOS pass strong 1
– But degraded or weak 0
❑ Thus nMOS are best for pull-down network

1: Circuits & Layout CMOS VLSI Design 4th Ed. 7

1: Circuits & Layout CMOS VLSI Design 4th Ed. 8
 Pass Transistors
❑ Transistors can be used as switches

g=0 Input g = 1 Output

g
s d 0 strong 0
s d g=1 g=1
s d 1 degraded 1

g=0 Input Output

g=0
g s d 0 degraded 0

s d g=1
g=0
s d 1 strong 1

1: Circuits & Layout CMOS VLSI Design 4th Ed. 9

 Transmission Gates
❑ Pass transistors produce degraded outputs
❑ Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

1: Circuits & Layout CMOS VLSI Design 4th Ed. 10

 Tristates
❑ Tristate buffer produces Z when not enabled

EN
EN A Y
0 0 Z A Y
0 1 Z
1 0 0
EN
1 1 1
A Y

EN

1: Circuits & Layout CMOS VLSI Design 4th Ed. 11

 Nonrestoring Tristate
❑ Transmission gate acts as tristate buffer
– Only two transistors
– But nonrestoring
• Noise on A is passed on to Y

EN

A Y

EN
1: Circuits & Layout CMOS VLSI Design 4th Ed. 12
 Tristate Inverter
❑ Tristate inverter produces restored output
– Violates conduction complement rule
– Because we want a Z output
A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A

1: Circuits & Layout CMOS VLSI Design 4th Ed. 13

 Multiplexers
❑ 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1
Y
D1 1
1 0 X 0
1 1 X 1

1: Circuits & Layout CMOS VLSI Design 4th Ed. 14

 Gate-Level Mux Design
❑ Y = SD1 + SD0 (too many transistors)
❑ How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2

1: Circuits & Layout CMOS VLSI Design 4th Ed. 15

 Transmission Gate Mux
❑ Nonrestoring mux uses two transmission gates
– Only 4 transistors
S

D0
S Y
D1

1: Circuits & Layout CMOS VLSI Design 4th Ed. 16

 Inverting Mux
❑ Inverting multiplexer Y = SD + SD (too many transistors)
1 0

– Use compound AOI22

– Or pair of tristate inverters
– Essentially the same thing
❑ Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1

1: Circuits & Layout CMOS VLSI Design 4th Ed. 17

 4:1 Multiplexer
❑ 4:1 mux chooses one of 4 inputs using two selects
– Two levels of 2:1 muxes
– Or four tristates S1S0 S1S0 S1S0 S1S0

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 18

 D Latch
❑ When CLK = 1, latch is transparent
– D flows through to Q like a buffer
❑ When CLK = 0, the latch is opaque
– Q holds its old value independent of D
❑ a.k.a. transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q

1: Circuits & Layout CMOS VLSI Design 4th Ed. 19

 D Latch Design
❑ Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK

1: Circuits & Layout CMOS VLSI Design 4th Ed. 20

 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

1: Circuits & Layout CMOS VLSI Design 4th Ed. 21

 D Flip-flop
❑ When CLK rises, D is copied to Q
❑ At all other times, Q holds its value
❑ a.k.a. positive edge-triggered flip-flop, master-slave
flip-flop

CLK
CLK
D
Flop

D Q
Q

1: Circuits & Layout CMOS VLSI Design 4th Ed. 22

 D Flip-flop Design
❑ Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK

1: Circuits & Layout CMOS VLSI Design 4th Ed. 23

 D Flip-flop Operation
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

1: Circuits & Layout CMOS VLSI Design 4th Ed. 24