Quad-Core Microprocessor Specific Architectures: Coordinating Teacher - Radescu Radu
Quad-Core Microprocessor Specific Architectures: Coordinating Teacher - Radescu Radu
Quad-core microprocessor
specific architectures
Coordinating Teacher
-Radescu Radu-
Craciun Stefan-Viorel
441F
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Quad-Core Microprocessors Craciun Stefan-Viorel
system can be in more than one chip, typically connected by some type of
bus, and each chip can then be a multiprocessor system. A third option is a
multiprocessor system working with more than one computer connected by
a network, in which each computer can contain more than one chip, and
each chip can contain more than one processor. Most modern
supercomputers are built this way. A parallel system is presented with more
than one task, known as threads. It is important to spread the workload
over the entire processor, keeping the difference in idle time as low as
possible. To do this, it is important to coordinate the work and workload
between the processors. Here, it is most important to consider whether or
not some processors are specialpurpose IP cores. To keep a system with
N processors effective, it has to work with N or more threads so that each
processor constantly has something to do. Furthermore, it is necessary for
the processors to be able to communicate with each other, usually via a
shared memory, where values that other processors can use are stored.
This introduces the new problem of thread safety. When thread safety is
violated, two processors (working threads) access the same value at the
same time. Consider the following code representation:
A=A+1
When two processors P1 and P2 execute this code, a number of
different out come may arise due to the real fact that the code will be split
into three parts.
L1: get A;
L2: add 1 to A;
L3: store A;
It could be that P1 will first execute L1, L2 and L3 and afterward P2
will execute L1, L2 and L3. It could also be that P1 will first execute L1
followed by P2 executing L1 and L2, giving another result. Therefore, some
methods for restricting access to shared resources are necessary. These
methods are known as Thread safety or synchronization. Moreover, it is
necessary for each processor to have some internal memory, where the
processor does not have to think about thread safety to speed up the
processor. As an example, each processor needs to have a private stack.
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Design
The proposed quad core executes the multiple tasks. These multi
tasks may be implemented by the Height tree evaluation technique and
reordering of instruction Execution is necessary for this proposed
architecture. The Clock is the heart beat of any processor. The processor
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executes one instruction within one clock period. The quad core is
responsible for many concurrent computing operations and it consists of
three main modules. These are Core processor, Quad RISC Processor, I/O
Ports. Generic RISC Processor are called scalar RISC Processor because
they are designed to issue one instruction per cycle, similar to the base
scalar processor. Four representatives RISC based processors from the
year 1990, the sun SPARC, Intel i860, Motorola M88100, and AMD
29000.Each processor use 32 bit instruction length. The instruction set
consists of 51 to 124 basic instructions. We consider these four processors
as generic scalar RISC, issuing essentially only these four processors as
scalar RISC, issuing essentially only one instruction per pipeline cycle.
Among the four scalars RISC Processor, we choose to examine the sun
SPARC and i860 architectures. The sun SPARC is derived from the
original Berkeley RISC design. The concept of parallel and distributed
computing Processor Core mainly consists of SIMD array, mapping, and
duplicate memories. Duplicate memories: The most important thing in
quad processor mapping is the boundaries and data flow of concurrent
processors. Duplicate memories are important and make a design flexible
and have a high throughput for both parallel and distributed strategies and
are too efficient for concurrent Architecture. SIMD array: This SIMD array
supports the multidimensional array of data. It allows the simultaneous use
of multiple processors for solving a task. An SIMD array is a synchronous
array of Processing Elements under the supervision of one control unit and
all P.E’s receive the same instruction broadcast from the control unit, but
operate on different multiple data sets from distinct data streams. It is
usually loads data into its duplicate memories before starting the
computation. All these are working together as a single processor that
involves both the parallel and distributed concurrent strategy.
RISC Processors (RISC): In the present work, the design of an 8-bit
data width Quad Reduced Instruction Set Computer (RISC) processor is
presented. It was developed with implementation efficiency and simplicity in
mind. It has a complete instruction set, program memories and data
memories, general purpose registers and a simple Arithmetical Logical Unit
(ALU) for basic operations. In this design, most of the instructions are
uniform length and similar format. Arithmetic operations are restricted to
CPU registers. The Instruction cycle consists of three stages namely
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fetches, decode and execute. Many numbers of RISC processors give the
highest performance per unit area for parallel codes. A larger number of
RISC processor cores allow a fine-grained ability to perform dynamic
voltage scaling and power down. The RISC processor core with a simple
architecture is easier to design and functionally verify. This processor is an
economic element that is easy to shut down in the face of catastrophic
defects and easier to reconfigure in the face of large parametric variation.
FPGA IMPLEMENTATION
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delivers higher performance per watt than competing single and dual core
processors.
In order to meet peak performance demands in a multitasking
environment, a single core CPU not only runs at higher clock frequencies
and voltages than a multi-core CPU, but also takes longer periods of time
to complete a given task. Multi-core CPUs are able to use symmetrical
multiprocessing and distribute workload across multiple CPU cores. Due to
workload sharing, each CPU core can run at lower frequency and voltage
to complete a multi-threaded task, or multiple tasks in a multi-tasking
scenario. Also, due to lower operating frequency and voltage, each core
consumes significantly lower power and offers much higher performance
per watt compared to single core CPUs.
Mobile devices that have a multi-core CPU with SMP support will be
able to deliver a fast desktop PC-style Web browsing experience. Modern
browsers such as Google Chrome and Mozilla Firefox are now multi-
threaded and capable of spawning several concurrent processes. Each
page tab in a Chrome browser is a separate process, and each process
manages its own set of threads. Both the processes and threads are highly
parallelizable. Figure 1 below shows the utilization of each core of a quad
core CPU system while browsing the popular New York Times Website.
From the figure it is seen that the browser uses all four cores of the quad
core CPU, and this parallel processing results in a Web browsing
experience that is much faster than on a dual core CPU-based mobile
device. Quad Core CPUs also deliver higher performance for browsers that
support tabbed browsing. Figure 2 below shows the CPU utilization across
the four CPU cores when multiple tabs are opened in a Web browser. In
fact, tabbed browsing uses significant CPU processing and as seen in the
figure, may even saturate all four cores of a quad core CPU.
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50%
Time (second)
Figure 2 CPU utilization on Quad core CPU system during Web browsing
50%
Time (second)
On a quad core CPU based system, the operating system will be able
to allocate multiple Web scripts across the four CPU cores and deliver
much faster execution of JavaScript heavy pages. Results from Moonbat, a
Web based JavaScript benchmark, show that a quad core CPU delivers
almost fifty percent faster Web browsing performance compared to dual
core CPU based mobile processors.
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Gaming consoles and PCs today all use multi-core chips that support
SMP technology, and most console and PC games are coded to take
advantage of the multi-core and SMP capabilities of the hardware. Today,
most game engines such as Unreal 3.0, Id Tech 5 and Frostbite are
multithreaded, and the engines are increasingly migrating to task-
processing models where the “size” of each individual job is reduced while
the number of threads is increased. These threads are used for tasks such
as audio, collision detection, artificial intelligence, user input processing,
game strategy and network communications. All modern game platforms
support many threads, and this trend will continue to increase on future
platforms.
Due to the higher performance delivered by quad core processors,
advanced gaming features such as real-time physics and real-time texture
generation can now be used in mobile games to deliver significantly higher
graphics quality and more realistic gameplay experience.
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Figure 9 Glowball Demo with Real-time Physics and Dynamic Lighting. Left side enabled, Right side disabled
boost delivered by quad core CPU based mobile processors will bring us
closer to true console and PC class games for mobile devices.
Figure 10 Performance benefit from Quad Core mobile processor for advanced games
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created in real-time based on the narrative and state of the game. Since
the textures are generated on the fly, they do not have to be provided at the
time of purchase. Using this technique, game developers can reduce game
file sizes by several orders of magnitude.
Figure 11 Scene variations in games, all dynamically generated on Kal-El’s 4 CPU cores
Conclusion
CPUs. Today’s desktop PCs are seeing the many benefits of multi-core
CPUs.
In the mobile space, the transition from single core CPUs to multi-
core CPUs has been much quicker. The mobile software ecosystem is
evolving from the work already done in the desktop space to enable
support for multi-core mobile CPUs. Widely used mobile software already
supports multitasking and multi-threading.
The Android operating system evolved from Linux, and therefore has
native support for multitasking and multi-threading. Recent releases of
Android 2.3 and Android 3.0/3.1/3.2 have added several features that
improve the operating system’s ability to leverage the processing power of
multi-core CPUs.
Mobile browsers such as Firefox and Webkit are based on their
desktop counterparts and therefore natively include support for multi-
threading. The new browser included with Android 3.0 supports not only
multi-threading, but also tabbed browsing. These browsers are able to
utilize the increased processing power offered by multi-core CPUs to
deliver a faster and better Web browsing experience.
Due to rapid growth in mobile gaming, developers are porting popular
PC and console game engines to the mobile environment. These game
engines were originally developed for multicore desktop PC platforms, and
therefore will leverage the multi-core CPUs in mobile processors to deliver
immediate benefits for mobile gamers. Quad core CPUs provide significant
processing power for game developers and will enable developers to
include advanced physics effects, artificial intelligence, collision
detection/avoidance, virtual texturing, better network playability, and more.
Quad core CPUs and variable SMP technology will enable mobile
devices to further push the performance envelope, and allow application
and game developers to deliver new mobile experiences, all while
extending battery life for the most popular use cases.
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References
Design and Implementation of Quad Core Architecture Using FPGA -V.Prasanth,
K.Raja Sekhar ( V. PRASANTH et al. Int. Journal of Engineering Research and
Applications ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.745-749)
NVIDIA Corporation Tegra White Paper
Wikipedia
John Shen Modern Processor Design: Fundamentals of Superscalar Processors,
1st Edition,McGraw-Hill Series in Electrical and Computer Engineering, 2015.
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