Look Ahead Carry Adder Using Diode Free

Adiabatic Logic Family

Vishwas Gosain, Vasudev Grover, Neeta Pandey Kirti Gupta
Dept. of Electronics and Communication Engineering, Dept. of Electronics and Communication Engineering,
Delhi Technological University, India Bharati Vidyapeeth’s College of Engineering, India
[email protected] , [email protected], [email protected]
[email protected]

Abstract— Reduction in power dissipation is one of the major II. DIODE FREE ADIABATIC LOGIC (DFAL) CIRCUITS
concerns for researchers in electronics industry. Carry look
ahead adder is widely used for fast calculations but it dissipates The DFAL circuits operate in two steps: evaluation phase and
lot of power due to which expensive cooling system has to be hold phase. It employs split-level power supplies (Vpc and
deployed. In this paper a 3-bit carry look ahead adder is ) as shown in Fig.1. In the evaluation phase, the clock
implemented using diode free adiabatic logic which has much signal is in the positive half cycle and is in the
superior performance than CMOS circuits in terms of power
dissipation and power delay product. The performance of the negative half cycle. The power supplies move in opposite
circuit is verified through simulations in Tanner EDA simulator direction in hold phase.
using 180nm CMOS TSMC parameters. Higher energy efficiency
is achieved in the proposed circuit.

Keywords— Adiabatic; DFAL; PDP; adder,CLA

I. INTRODUCTION
The major area of research with advancement of
technology is reduction of power dissipation in the electronic
devices. Digital circuits with high performance also lead to
high power dissipation. Thus to reduce the power dissipated by
a circuit new logic families have emerged and one of the most
effective family is adiabatic logic family. The power is Fig. 1.Split level Power Supplies (Vpc and )
dissipated in a circuit in majorly two ways i.e. static and
dynamic power dissipation. While static power dissipation The structure of a DFAL inverter [8] is shown in Fig.2 to
occurs due to leakage current flowing in the off state of the elaborate evaluation phase and hold phase. The inverter
device, dynamic power dissipation occurs due to charging and consists of two n-MOS transistors (M2 and M3) and one p-
discharging of the output capacitance i.e. when switching MOS (M1). For LOW input signal (in=0), M1 is switched on
occurs in the circuit. Adiabatic logic family mainly reduces the which leads to charging of the load capacitance. For HIGH
dynamic power dissipation of the logic circuit by recycling the
input signal (in=1), M2 and M3 are both switched on, which
energy of the power supply.
makes the load capacitance follow . Hence charge
There are different variants of adiabatic family[2-8] and recycling takes place.
DFAL (Diode Free Adiabatic Family) is one of them. The
other variants of adiabatic logic are Glitch Free Cascadable
Adiabatic Logic (GFCAL)[2], Clocked Adiabatic Logic
(CAL)[3,4], Efficient Charge Recovery Logic (ECRL)[6] and
Two Phase Adiabatic Static CMOS Logic (2PASCL)[7].
GFCAL contains diodes and suffers amplitude degradation and
high delay. ECRL and CAL have problems like floating nodes
and current leakage. These limitations are overcome by DFAL
and are highly efficient due to absence of diodes in its circuit.
In the paper, carry look ahead adder is implemented
using DFAL family. In section II the basic working of DFAL
circuit is explained. Implementation and working of Carry look
ahead Adder is explained in section III. The simulation results
are shown and compared in section IV. The paper is then Fig.2. Basic DFAL Inverter
concluded in section V.
 Fig.3. Generalized Sum and Carry in Carry look ahead Adder

Fig.5. DFAL based XOR gate

Fig.4. DFAL based AND gate

In the hold phase no output transitions occur. Power

dissipation is therefore reduced due to lesser switching
activity. The implementation of Carry look ahead Adder [9]
mainly requires AND gate and XOR gate as shown in Fig.3.
Their DFAL based implementation is shown in Fig.4 and Fig.
5 respectively.

III. DFAL BASED CARRY LOOK AHEAD ADDER

An adder is a vital part of arithmetic logic unit and since
most arithmetic operations like multiplication and division are
done using addition, the speed of the adder determines the
system’s speed. In conventional ripple carry adder, the Fig.6. Carry Look Ahead Adder Block Diagram [9]
propagation time of the carry is the speed limiting factor and
to remove this limitation carry look ahead adder is used. The
principle of carry look ahead adder is that by calculating the IV. SIMULATION RESULTS WITH PERFORMANCE ANALYSIS
carry in advance, we avoid waiting for calculation of carry,
thus making the addition quicker. The block diagram of carry The operation of the adiabatic carry look ahead adder of Fig. 7
look ahead adder is shown in Fig. 6. Also the gate level is verified using adiabatic AND and XOR gates of Figs. 4 and
implementation of the adder is shown in Fig.7. 5 through simulations. The CMOS technology parameter of
0.18 micron is used for the simulation purpose. The
performance of DFAL carry look ahead adder is compared
with its CMOS based counterparts. The comparison of power Power Dissipation

Power Dissipation
dissipation and power delay product (PDP) is done by 60
considering two cases i.e. constant load capacitance with

(µW)
varying input frequency and constant input frequency with 40
varying load capacitance.
20

0
0 50 100
Frequency of operation (MHz)
CMOS DFAL
Fig.8 Power dissipation vs Input Frequency

Time Delay
1.5

Delay(ns)
1
0.5
0
0 50 100
Frequency of Operation(MHz)
CMOS DFAL
Fig.9 Delay vs Input Frequency

Power Delay Product

40
30
PDP(fJ)

20
10
Fig.7. Gate level representation of Carry look ahead Adder 0
A. PDP analysis with constant load capacitance 0 50 100
Here the load capacitance is kept constant at 50 fF and the Frequency of Operation(MHz)
power dissipation and PDP is calculated at different input CMOS DFAL
frequencies (2 MHz to 80 MHz). The simulation results are
enlisted in Table I and are plotted graphically in Figures 8, 9 Fig.10 PDP vs Input Frequency
and 10. It may be observed that maximum and minimum
reduction in power dissipation and PDP are (45.7%, 36.5%)
and (31.4 %, 5.26 %) respectively. The delay of DFAL based B. PDP analysis with constant input frequency
circuit is slightly higher than CMOS counterpart; the overall
PDP of DFAL circuit was much lower, so DFAL based carry Here the load capacitance is varied and the power
look ahead adder is more efficient than CMOS based adder. dissipation and PDP are studied at fixed input frequency. The
TABLE I ANALYSIS WITH CONSTANT LOAD CAPACITANCE AND VARYING
frequency was fixed to 100 MHz and the value of load
INPUT FREQUENCY capacitance was varied from 10 fF to 200 fF. The simulation
results are summarized in Table II and graphically shown in
Frequency
Figure 11, 12 and 13.
2MHz 10MHz 20MHz 40MHz 80MHz
Family On varying the load capacitance, the reduction of power
Power Dissipation (µW) dissipation in DFAL based circuit is found to be 30% to 36%
CMOS 1.04103 5.16 10.29 20.53 40.84 while reduction in PDP is observed as 12% to 29.1%. It is also
DFAL 0.62 2.8 6.53 12.39 23.9 observed that at higher value of load capacitances, the time
Delay(ns) delay in both CMOS and DFAL circuits was almost the same
CMOS 0.78 0.775 0.772 0.758 0.725 but the power and PDP of DFAL circuit was much lesser. Thus
DFAL 1.38 1.35 1.21 1.03 0.85 the DFAL carry look ahead adder dissipates much lesser power
Power Delay Product (PDP) and is more efficient even at different capacitance load values.
CMOS 0.81 3.99 7.94 15.56 29.61
DFAL 0.85 3.78 7.90 12.76 20.31
 TABLE II: ANALYSIS WITH CONSTANT INPUT FREQUENCY AND VARYING
LOAD CAPACITANCE Time Delay
3

Time Delay(ns)
Capacitance
10fF 25fF 50fF 100f 125fF 150f 200fF 2
Family F F
Power Dissipation (µW)
1
CMOS 8.90 10.8 13.6 19.0 21.7 24.3 29.41
DFAL 6.23 6.93 8.86 12.8 14.7 16.4 19.32
0
Time Delay (ns)
CMOS 0.32 0.47 0.76 1.3 1.61 1.91 2.43 0 50 100 150 200 250
DFAL 0.53 0.65 0.91 1.45 1.92 2.05 2.62 Load Capacitance(fF)
Power Delay Product CMOS DFAL
CMOS 2.90 5.11 10.3 24.7 34.97 46.5 71.46 Fig.13 Delay vs load capacitance
DFAL 3.30 4.50 8.06 18.6 28.22 33.6 50.62
V. CONCLUSION
In this paper, adiabatic carry look ahead adder using DFAL
family is implemented. Performance of this adder is measured
under different parameters. It was shown that DFAL is better
Power Dissipation in terms of energy consumption. The maximum power and
40 PDP reduction achieved were 45.7% and 31.4% respectively
Dissipation(µW)

30 as compared to CMOS circuit. Thus, the PDP comparison

Power

clearly proves that the performance of carry look ahead adder

20
implemented using DFAL family is much superior to that of
10 CMOS family.
0
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