Flexible Checker: A One-Stop Shop For All Your Checkers and A Methodology For Elastic Scoreboarding
Flexible Checker: A One-Stop Shop For All Your Checkers and A Methodology For Elastic Scoreboarding
checkers and
a methodology for elastic scoreboarding
Saad Zahid, Chandra Veedhi, Sumit Dhamanwala
Arteris Inc
9601 Amberglen Blvd. Building G, Suite 117,
Austin TX, 78729
Abstract—This paper aims to define a methodology for a composite checker/scoreboard called Flexible Checker
that provides test-bench writers a solution that can adapt to ever-changing design configurations. Flexible
Checker also provides a solution that is portable across blocks, sub-blocks, and chip-level environments. It can
also support flexible “transaction trace checking,” which checks transactions at multiple internal nodes before
reaching their end points. Flexible Checker is equipped to record and dump vital statistics, including bandwidth,
latency, traffic distribution, transaction count (type, size, etc.), from end to end in the report phase of a UVM.
I. INTRODUCTION
The scoreboard for the UVM test bench of a SoC is a crucial piece that checks the data integrity across the DUT (design under
test). The way a scoreboard is coded traditionally varied from engineer to engineer, configuration to configuration, and block
to block. In this paper, we will show how to templatize a scoreboard to make it more configurable, scalable, and lightweight at
the same time. To achieve this, we introduce what we call a proxy transaction container class, a proxy monitor, and proxy
transaction queues.
II. ARTERIS VERIFICATION CHALLENGE
For companies like Arteris, which provides IP interconnects with the capability to be constituted of an infinite number of
configurations, it is essential to make the corresponding test benches fully flexible and elastic yet robust and effective to deliver
high quality. Our biggest challenges to consider during the development process are as follows:
1. Each and every interface field and position is configurable.
2. Each block/unit/component is also fully elastic in terms of
a. The number of input/outputs,
b. how its features can be enabled/disabled from a code-generation prospective, and
c. the buffer sizes, pipeline stages, states, registers, etc.
3. Similarly, all the above must be complemented by an equivalent test bench to verify each available feature accordingly.
These above-mentioned challenges cannot be solved just by using the SystemVerilog (SV) parameter alone, so we have to
develop a custom tool to preprocess our embedded (inline) and parameterized code to generates the final SV code.
III. KEY COMPONENTS
To make Flexible Checker highly scalable, agile, and portable, we needed to make a few fundamental verification strategy
decisions and develop the key components as follows:
1. All in-house UVCs (or VIPs) must have a portable monitor so that we can instantiate it directly in Flexible Checker.
2. For external (third-party) VIPs, we wrote a proxy monitor to collect third-party transactions and embed them into our
proxy transaction container class and pass them to an elastic scoreboard.
3. All test-bench components must use a single transaction type (proxy transaction container) regardless of the actual
transaction type (for example, AXI, APB, AHB, or any number of in-house protocols).
4. We assembled a wrapper class (extended from UVM_COMPONENT) called Flexible Checker, which includes all the
required monitors and the elastic scoreboard.
X. CONCLUSION
Flexible Checker was used in a highly configurable test bench and was able to do the checker functions just by passing the
configuration parameters. It made building a block-level test bench redundant by using the transaction trace-checking feature,
which helped the designer greatly in debugging failures as they were able to see the transaction flow and translation at each
node of the design before reaching the target. Additionally, a statistics generator was used to print a table listing the transaction
count, latency, and bandwidth numbers. This gave firsthand statistic numbers to the architects and gave a comparison point
with the actual performance model numbers.