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Logic Cricuit Design Lab: LAB3: Study Level of Abstraction in Fig 1

This lab document outlines steps for designing and simulating logic circuits. It includes: 1. Studying levels of abstraction and design flow diagrams 2. Writing VHDL code for a register and testbench 3. Comparing asynchronous and synchronous resets 4. Designing a 4-bit register using a package and connecting it to a 7-segment display decoder 5. Writing a testbench to simulate the design

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Ravipon Phongharin
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64 views12 pages

Logic Cricuit Design Lab: LAB3: Study Level of Abstraction in Fig 1

This lab document outlines steps for designing and simulating logic circuits. It includes: 1. Studying levels of abstraction and design flow diagrams 2. Writing VHDL code for a register and testbench 3. Comparing asynchronous and synchronous resets 4. Designing a 4-bit register using a package and connecting it to a 7-segment display decoder 5. Writing a testbench to simulate the design

Uploaded by

Ravipon Phongharin
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Logic Cricuit Design Lab

LAB3: Study Level of Abstraction in Fig 1


and design flow diagram in Fig 2, focus on
RTP Simulation using Testbench. In Fig 3,
write VHDL to create register and Testbench
for simulation. What is the difference between
asynchrounous reset and synchronous reset? In
Fig 4, write VHDL and Testbench?

Figure 1 Levels of Abstraction


Figure 2 Design flow diagram

Figure 3 Register
Figure 4 asynchrounous reset vs synchronous
reset Register
LAB4:
1. Design 4 bit register using input name and
output name as following in Fig 4, create
the4 bit register Package and simulation.
2. Use Seg7_decorder Package in Lab 2
connect output of the 4 bit register
Package, shown in Fig 5
Figure 4. The 4 bit register

Figure 5. The 7-segment


3. Use Testbench as shown Fig 6 for
simulation, describe each process of
Testbench.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb_seg7_decoder_vhd IS
END tb_seg7_decoder_vhd;

ARCHITECTURE test OF tb_seg7_decoder_vhd IS

COMPONENT seg7_decoder
Port ( clk :in std_logic;
rst :in std_logic;
in_en :in std_logic;
bin_in : in std_logic_vector(3 downto 0);
seg7_out : out std_logic_vector(7 downto 0));
END COMPONENT;

SIGNAL bin_in : std_logic_vector(3 downto 0) := (others=>'0');


SIGNAL seg7_out : std_logic_vector(7 downto 0);
signal clk :std_logic:= '0';
signal rst :std_logic;
signal in_en :std_Logic;

BEGIN

uut: seg7_decoder PORT MAP( clk => clk,


rst => rst,
in_en => in_en,
bin_in => bin_in,
seg7_out => seg7_out
);

clk <= not clk after 5 ns;

process
begin
rst <= '0';
wait for 234 ns;
rst <= '1';
wait for 123 ns;
rst <= '0';
wait;
end process;

process
begin
in_en <= '0';
wait for 10 ns;
in_en <= '1';
wait for 10 ns;
in_en <= '0';
wait for 50 ns;
in_en <= '1';
wait for 10 ns;
in_en <= '0';
wait for 50 ns;

in_en <= '1';


wait for 10 ns;
in_en <= '0';
wait for 50 ns;

in_en <= '1';


wait for 10 ns;
in_en <= '0';
wait for 50 ns;

end process;

tb : PROCESS
BEGIN
bin_in <= "0000";
wait for 500 ns;
bin_in <= "0001";
wait for 500 ns;
bin_in <= "0010";
wait for 500 ns;
bin_in <= "0011";
wait for 500 ns;
bin_in <= "0100";
wait for 500 ns;
bin_in <= "0101";
wait for 500 ns;
bin_in <= "0110";
wait for 500 ns;
bin_in <= "0111";
wait for 500 ns;
bin_in <= "1000";
wait for 500 ns;
bin_in <= "1001";
wait for 500 ns;

END PROCESS;

END;

Figure 6. The Testbench file


Example LAB
Write VHDL using Package.
TEST LAB

TEST LAB. Design counter which can count


from 0 to 99 and recount again, write
Testbench for simulation

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