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Lecture 2A RTL Design Methodology Transition From Pseudocode & Interface To A Corresponding Block Diagram

The document describes the design process for digital systems using RTL and VHDL. It introduces the typical structure of a digital system with a datapath and controller. The steps of the design process are outlined, including developing the text description, interface, pseudocode, block diagram, state machine chart, and final VHDL code. An example statistics circuit is used to demonstrate the process, showing the pseudocode, interface, and block diagram divided into a datapath and controller component.

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Ali Mohamed Eltemsah
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82 views12 pages

Lecture 2A RTL Design Methodology Transition From Pseudocode & Interface To A Corresponding Block Diagram

The document describes the design process for digital systems using RTL and VHDL. It introduces the typical structure of a digital system with a datapath and controller. The steps of the design process are outlined, including developing the text description, interface, pseudocode, block diagram, state machine chart, and final VHDL code. An example statistics circuit is used to demonstrate the process, showing the pseudocode, interface, and block diagram divided into a datapath and controller component.

Uploaded by

Ali Mohamed Eltemsah
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lecture 2A

RTL Design Methodology

Transition from
Pseudocode & Interface
to a Corresponding Block Diagram
Structure of a Typical Digital
System
Data Inputs Control & Status Inputs
Control
Signals
Datapath Controller
(Execution (Control
Unit) Unit)
Status
Signals
Data Outputs Control & Status Outputs
Hardware Design with RTL VHDL

Pseudocode Interface

Datapath Controller

Block ASM
diagram chart

VHDL code VHDL code


Steps of the Design Process
1.  Text description
2.  Interface
3.  Pseudocode
4.  Block diagram of the Datapath
5.  Interface divided into Datapath and Controller
6.  ASM chart of the Controller
7.  RTL VHDL code of the Datapath, Controller, and
Top-Level Unit
8.  Testbench for the Datapath, Controller, and Top-Level
Unit
9.  Functional simulation and debugging
10.  Synthesis and post-synthesis simulation
11.  Implementation and timing simulation
12.  Experimental testing using FPGA board
4
Steps of the Design Process
Introduced in Class Today
1.  Text description
2.  Interface
3.  Pseudocode
4.  Block diagram of the Datapath
5.  Interface divided into Datapath and Controller
6.  ASM chart of the Controller
7.  RTL VHDL code of the Datapath, Controller, and Top-
level Unit
8.  Testbench for the Datapath, Controller, and Top-Level
Unit
9.  Functional simulation and debugging
10.  Synthesis and post-synthesis simulation
11.  Implementation and timing simulation
12.  Experimental testing using FPGA board
5
Class Exercise 1
STATISTICS
Pseudocode
no_1 = no_2 = no_3 = sum = 0
for i=0 to k-1 do
sum = sum + din
if din > no_1 then
no_3 = no_2
no_2 = no_1
no_1 = din
elseif (din > no_2) then
no_3 = no_2
no_2 = din
elseif (din > no_3) then
no_3 = din
end if
end for
avr = sum / k
Circuit Interface

clk done
reset n
n dout
din Statistics
2
dout_mode
go
Interface Table

Port Width Meaning


clk 1 System clock.
reset 1 System reset.
din n Input Data.
go 1 Control signal indicating that the first input is ready.
Active for one clock cycle.
done 1 Signal set to high after the output is ready.
dout n Output dependent on the dout_mode input.
dout_mode 2 Control signal determining value available at the output.
00: avr, 01: no_1, 10: no_2, 11: no_3.
STATISTICS:
Solutions
din

n
n en1
en reset
n+m rst
clk A gt1
n+m
clk
n no_1 A>B
esum n B
en reset
rst
clk 1 0 s2
clk
sum
n+m en2
reset enc en reset
en rst
rst clk clk
clk
clk A gt2
no_2 m
n+m n A>B
n B i
1 0 s3
>> m = k-1
en3
en reset
rst
n clk A gt3
clk
avr n no_3 A>B zi
no_1 no_2 no_3 B
n n n

00 01 10 11 dout_mode

2
n dout
Block diagram of the Datapath
Interface with the division into
the Datapath and the Controller
din dout_mode clk reset go

n 2

gt1
gt2
gt3
Datapath zi Controller
en1
en2
en3
esum
enc
s2
s3

dout
done

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