Assignment AE-‘2’

[ IC – fabrication]

Topic- ‘ Microelectronic
Circuit Layout ‘

By-
Yatharth Saxena , 2K18/EC/197
Shubham Gupta ,2K18/EC/163
Shubham ,2K18/EC/164
Yogesh Rathore , 2K18/EC/197
What is a LAYOUT DESIGN?
• Layout Design is a schematic of the Integrated Circuit(IC) which describes the exact
placement of the components for fabrication.

• Layout Design rules describe how small features can be & how closely they can be
packed in a manufacturing process

Why do we need Layout Design Rules?

• Industrial Design rules are generally specified in microns.
• This makes migrating from one process to more advanced process difficult because
not all rules scale in the same way.
• In order to bring uniformity, Mead & Conway popularized lambda-based design rules
based on single parameter.
• Lambda, characterizes the resolution of the process & is generally the half of the
minimum drawn transistor channel length.
• The channel length is the distance between drain & the source which is set by a
minimum width of a polysilicon wire.
• Ex:-A 180 nm process has a minimum polysilicon width of 0.18microns and uses
design rules with lambda=0.09
• However the designers make the scaling layout trivial.
• The same layout can be moved to a new process simply by specifying the Lambda
value.
• The potential density advantage of micron rules is sacrificed for simplicity and easy
scalability of lambda rules.
• Designers often describe a process by its feature size.
• Feature Size refers to the minimum transistor length, So lambda is half the feature
size.
• Transistor dimensions are always specified by Width/Length ratio.
• Ex-In 0.6 um technology, width corresponds to 1.2um & length to 0.6um.
• In digital systems, the transistors are chosen to have minimum possible length
because short channel transistors are faster, smaller & consume less power.
BIPOLAR INTEGRATION TECHNIQUE
The basic steps of the fabrication process. The fabrication of a great number of identical bipolar
integrated circuits starts with slicing and polishing a wafer of p-type silicon, which will serve as the
substrate of the circuits. Next, an n-type "epitaxial" layer is grown on the surface of the wafer. The
crystal structure of the substrate is continued in the epitaxial layer by passing a gas containing both
silicon atoms and n-type impurities over it in a heated environment. In the next steps a number of
diffusions are performed into the epitaxial layer (p-type or n-type) ,with the first of these diffusions,
the so called deep p-diffusion, channels are created, that reach the p-type substrate. Into the
regions of n-type epitaxial material, generated by this deep p-diffusion, p- and n-type impurities are
diffused, thus realizing the other p-type and n-type layers of which the integrated components
consist. The diffusions only have to take place on certain areas of the wafer, and therefore a
photolithographic process is applied before the execution of each diffusion step. This process
involves the following actions - a thin silicon dioxide coating is grown by exposing the wafer to an
oxygen atmosphere of about 1000° c. - this silicon dioxide layer is covered with a special kind of
photosensitive emulsion (photoresist) - the wafer is locally exposed to ultra-violet light. This is done
by placing a photographic mask on top of the photoresist. The transparent windows of the mask
determine the areas that will be exposed to the ultra-violet light - the unexposed parts of the
emulsion are dissolved, thus leaving selected areas of the silicon dioxide uncovered - in the
uncovered areas the oxide is etched away - the photoresist is removed. After this process a part of
the wafer is covered with silicon dioxide, which acts as a barrier to the diffusion of dopants.

Each diffusion step has its own "process parameters", determining the diffusion profile, i.e. the
"depth" of the diffusion layer and its concentration of impurities. In order to isolate the completed
(pn-structured) semiconductor material from the aluminium interconnection pattern that will be
added in the last step, a new sio2 layer is grown and the contact holes are etched in this layer. Then
a thin film of aluminium is evaporated over the wafer; certain areas of this aluminium are thereupon
etched away in order to obtain the desired pattern for component interconnection. After testing the
completed circuits on the wafer, they are separated into individual "chips" by scribing and breaking
the wafer. Finally the chip is "packaged": it is bounded to a lead frame, its bonding pads are wired to
the pins of its house, and the house is hermetically sealed or encapsulated.
The integrated components.
Now, we will discuss the component structures that are commonly used in realizing a circuit with the
described manufacturing process.

n-p-n Transistors

The process parameters of the diffusions in the fabrication process are chosen such that a good
performance of the npn-transistors is obtained. The configuration of an npn-transistor is depicted.
The n-type epitaxial layer serves as the collector region of this transistor. The base region is obtained
by a shallow p-diffusion in the epitaxial layer, and the n+-type emitter region is diffused into the p-
type base region. The fact that the impurity concentration of the emitter diffusion is much higher
than that of base and collector region, is indicated by the plus sign. In order to make an ohmic
contact with the collector region, the area + under its contact hole is also made n -type. The pn-
junction between the collector region and the substrate is reverse-biased by giving the substrate the
most negative potential. The capacitance and breakdown voltage of this junction is optimized by
using highly resistive material for the substrate. It is possible to reduce the collector series resistance
by extending the basic process and placing an extra n+-diffusion in the substrate (before growing the
epitaxial layer) over the whole collector area of the transistor ("buried layer"). More diffusion steps
may be added in order to create special devices (e.g. an extra "side wall" diffusion to reduce the
collector resistance further, or an extra emitter diffusion to narrow the base width (and thus
achieving a high current gain).

p-n-p Transistors

With the same p-type diffusion ("base diffusion") and n +-type diffusion ("emitter diffusion") that
have been used for the construction of the npn-transistors, it is possible to construct a pnp-
transistor of the "lateral" type. Since the average base width of this pop-transistor is very large its
gain is rather small. The effective base width can be reduced by shaping the collector such that it
surrounds the emitter completely. The gain can be increased further by reducing the downward
injection introduced by the parasitic pnp-transistor having the substrate as collector. This can be
achieved by placing a "buried" layer between epitaxial layer and substrate. A different type of the
pop-transistor is the "substrate pop-transistor", which is formed by the base diffusion, the n-
epitaxial layer, and the substrate. With this type a better performance can be obtained, but then the
control over the epitaxial layer thickness has to be tighter, since it is directly related to the effective
base width of the transistor. Therefore it might be recommendable to avoid substrate transistors
completely. Since the substrate is connected with the most negative potential in the circuit, this
substrate transistor can only be used for transistors of which the collector is connected with this
potential.

Diodes: For the construction of the diodes the base and emitter diffusions already mentioned can be
utilized. Those field: - the base-emitter diode. 10 L Since the collector region is also present, its bias
is of importance. The base and collector region are usually connected. If the diode is forward-biased,
the component works like an npn-transistor in its active region. In reverse-biased state the
breakdown voltage for this type is about 6 volts, so that for higher reverse operating voltages we
have to use the base-collector junction: -the base-collector diode. This diode has the disadvantage
that if it is forward-biased, the parasitic pnp-transistor is in its active region. The gain of this pnp-
transistor can be reduced by addition of the buried layer.

Resistors: Resistors can be made by using the resistive nature of doped semiconductor layers. It is
most common to use the base-diffused layer, since its resistivity is convenient, and the tolerances
and temperature coefficients are acceptable ("p-type diffused resistor"). The high impurity
concentration of the emitter diffusion makes it only suitable for the realization of resistors with very
low values (n+-type diffused resistors). The value of a resistor is of course dependent on the length,
width and depth of its resistance layer. A convenient measure of the value of a diffused resistor (if
the resistivity of the material and the thickness of the layer is fixed), is the "sheet resistance" in
ohms per square: the resistance of a square area is independent of the length of its sides. In order to
obtain the required value of a resistor, the appropriate number of "squares" has to be added
together in series between its contacts. In designing large-valued resistors one often applies bends
in the resistor path. Due to current crowding around the inside corner, one has to correct the
("effective") contribution of this bend to the total resistor value. The (design of the) geometry of a
diffused resistor with a large value, is very flexible. This flexibility is used to fit the resistors in the
regions assigned to them, even if the regions have a somewhat uncommon shape. As a consequence
the resistor diffusion may be given a rather intricate shape. The .Determination of this shape is
called the "meandering of the resistor".

The layout of a circuit.

An electrical circuit specification is any collection consisting of the following items:

1. a set of components, specified either by reference to a model stored in a library, or completely

described in terms of parameters of the applied process;

2. a partition over the set of component contacts, which is such that all the contacts contained in the
same block, should always be at the same potential;

3. a predescribed circuit performance with certain tolerances.

When a circuit is integrated by the process described in the preceding sections, the components are
usually realized completely by the part that consists of semiconductor material, whereas the
interconnections, that provide the potential correspondences between the contacts in the same
block, can be recognized in the aluminium configuration. For this reason the part of the integrated
chip that is separated from the aluminium by the silicon dioxide layer is called the "component
layer", and the part that consists of the aluminium interconnections is called the "wiring layer",
Remark: Distinguishing between the two layers on the described grounds is not always correct. On
the one hand, the component layer is 14 L used for the accommodation of a small diffusion coructor,
the "cross under", which makes it possible that leads cross each other without making contact. On
the other hand, the aluminium layer is sometimes used as a part of a component as for example in
case of a metal-oxide-silicon capacitor. The layout of a circuit is any set of data that completely
specify all the masks necessary for integrating the circuit such that:

1. all the components of the circuit can be recognized;

2. all the potential correspondences are realized by conducting leads;

3. the circuit behaves within the given tolerances.

The special characteristics of the applied manufacturing process make that the design of the circuit
(both the electrical diagram and the layout) is highly dependent on the (technological) factors that
have an influence on: - the electrical performance of the integrated circuit - the manufacturing cost
of the integrated circuit. An important design objective is the minimization of the chip area, since
the overall yield of chips decreases if the occupied area increases due to the occurrence of defects in
the semiconductor crystal. The circuit designer will therefore try to avoid components that require
relatively large areas on the chip such as large-valued diffusion resistors and capacitors. Some other
factors that may have consequences for the design of the electrical circuit, are: - the tolerances of
the resistors are rather high, and therefore the electrical behaviour {e.g. the biasing of the active
components) should not be critically dependent on the values of these resistors; - "matched
components" can be realized more easily. By placing the components close to each other and in the
same orientation, this "matching" can even be improved ; - non-ideal properties of components
(parasitic effects, temperature effects, breakdown voltages, etc. have to be taken into account, too).
The applied technology also has its consequences for the design of the layout. One has to strive after
minimization of the chip area . But also other requirements may establish constraints on the layout
design: L 15 - for connecting the circuit to the pins of the housing it is advantageous to have the
"bonding pads" on the periphery of the chip. An additional reason for doing this is to have the
components on the chip not placed too far from each other, and thus obtain low temperature
differences between the components; - there may be several demands from the circuit designer that
are important for an adequate electrical performance of the circuit. One may wish·certain
components to be placed close to each other (matching) or far from each other (thermal effects,
parasitic coupling). For certain component contacts it may be important to have very little loss of
tential along the interconnection lead (no crossunder!), or between certain potentials capacitive
coupling must be avoided (input and output potential). In general the length of the interconnection
leads is to be kept as small as possible; - one has to exploit possibilities to reduce the total chip area,
e.g. the total area occupied by the isolation diffusion can be reduced by using the minimum number
of isolated regions that is possible, and by giving these regions an approximately squared form.
Furthermore one has to be careful with measures that consume extra area, such as: the application
of crossunders, increasing the width and length of a (low-valued) resistor in order to move its
contacts farther from each other, and realizing a resistor as diffused resistor, even though the design
would admit a pinch resistor; - standardization rules may dictate that the terminals of the integrated
circuit occur in a previously specified sequence; - it may occur that the designer requires to use a
special, predesigned layout for some part of the electrical circuit. The "terminal"-potential-leads
leave this "layout-block" in a certain sequence. The isolation of the components. Isolation between
the components can be obtained by pn-junctions that are reverse-biased. The substrate is connected
with the (most) negative supply voltage and thus its junction with the epitaxial layer will always be
reverse-biased. The same holds for the junction between the deep p-diffusion channels (reaching
the substrate) and the epitaxial layer. 16 L By surrounding a certain region of the chip by a deep p-
type "isolation channel" it is possible to isolate this region from the rest of the chip. Such an isolated
region (IR) is called an "island", and the "island potential" is defined as the potential of its n-type
epitaxial layer. Not all components have to be placed in separate islands. The voltage states of the
electrical circuit at any moment may be such that for certain components, even if they are part of
the same island, the required electrical isolation is automatically guaranteed. Such components are
called "IR-compatible". For example, an npn-transistor of which the collector is connected with the
(most) positive supply voltage is IR-compatible with any p-type diffused resistor. The components of
the circuit have to be distributed over a number of isolated regions, and thus a partition of the set of
components has to be determined. The components of which the epitaxial layer is a part of their
structure, determine the island potential of the isolated region they are in, and are called "epitaxial
components" (EP-components). EP-components cannot be embedded in the same island if their
epitaxial parts are to be connected with different potentials. Components of which the n-type
epitaxial layer is not a part of their structure are called "non-epitaxial components" (NEP-
components). For all voltage states of the circuit, the potential of their fundamental layer (i.e. the
layer that, on the bottom side, is surrounded by the epitaxial layer) has to be less than or equal to
the island potential.
The potential graph.
A direct translation of the ideas on integration reviewed in the preceding chapter leads to a more or
less stylistic layout. We start with an inquiry into the existence of such a layout, taking into account
certain constraints if required. We therefore give a precise definition of this layout. A layout of a
circuit is called a formal layout if A1: there is a component layer in which every component has its
own domain without overlapping domains of other components, A2: there is a wiring layer in which
all interconnections between components are realized and no interconnection path crosses a
component, A3: every component contact is made by exactly one contact hole which is the end of an
interconnection path, A4: all contacts of a component can be reached simultaneously from given
points at the boundary of its domain by interconnection leads. Clearly, the requirements for a formal
layout are too rigid to be conclusive about the existence of a layout ‘of a given circuit: components
are not allowed to share certain diffusions, an interconnection lead only enters a component domain
to reach a contact hole, a diffusion is contacted via exactly one hole in the silicon dioxide layer, etc..
However, this concept gives a convenient starting point for the discussion on the existence of a
layout for a circuit. Before entering this discussion, we make some remarks about A4. This
requirement is included in the definition to make sure that, no matter from which direction the
component domain is approached, if it can be reached, the proper contact can also be reached. This
is necessary because of the finite distances between contacts and the width of the aluminium
interconnection leads. Thus A4 (and partly also A3) is a restriction on the types of components that
are allowed in the circuit.

The problem now is to formulate a criterion for the existence of a formal layout of a given circuit.
The available data consist of a list of components and their mutual connections, i.e. which contacts
of which components must always be at the same potential. These data are usually conveniently
displayed in a schematic diagram, where components are represented by suitable symbols and the
interconnections by trees, the "potential trees".
The following represent some reasonable layout rules used in bipolar
circuit fabrication:
1 . In the layout, allow an isolation border equal to twice the epitaxial thickness to take lateral
diffusion into account.

2. Since the isolation diffusion occupies an appreciable area of the chip, the number of isolation
islands should be minimized.

3. Place all p-type resistors in the same isolation island and return that isolation region to the most
positive potential in the circuit. For p-type resistors, isolation regions are connected to the most
negative potential in the circuit.

4. For resistors, use the widest possible designs consistent with die-size limitations. Resistances
which must have a close ratio must have the same width and be placed close to one another.

5. Place all transistors whose collectors are tied together into the same isolation island. For most
circuits, each transistor will be in a separate island.

6. Connect the substrate to the most negative potential of the circuit.

7. Use minimum dimensions for emitter regions, base regions, and contacts consistent with device
current requirements.

8. Determine component and metallization geometries from the performance requirements of the
circuit. For example, the transistor in the output stage of an amplifier would have a larger area than
the other transistors if the output stage were to supply the maximum current.

9. Keep all metallization runs as short and wide as possible, particularly at the emitter and collector
connections of a saturating transistor.

10. Optimize the layout arrangement for the smallest possible chip size.

11. Use an alignment pattern of the artwork so as to simplify the registration of successive masks.

12. Minimize the number of crossovers.

Many of the layout rules also apply to MOS-circuit fabrication. Note, again, that isolation islands are
not needed, thereby increasing component densities. One important factor in large-scale ICs is the
utilization of minimum gate dimensions consistent with desired current levels. The use of polysilicon
gates is an aid in using small devices. Because polysilicon is an effective barrier to dopants, the
implantation of the drain and source regions is self-aligned and mask registration errors are
minimized.
Stick Diagrams Rules:
1)When two or more ‘sticks’ of the same type cross or touch each other which represents electrical
contact.

2)When two or more ‘sticks’ of different type cross or touch each other which represents no
electrical contact.

3) When poly crosses diffusion, it represents a transistor.

4) In CMOS, a demarcation line is drawn to avoid touching of p-diffusion & n-diffusion. All p-MOS
should lie on one side of the line & all n-MOS should be on the other side of the line.

CMOS NAND gate stick diagram

Crossovers:
Very often the layout of a monolithic circuit requires two conducting paths to cross over each other.
This crossover cannot be made directly because it will result in electric contact between two parts of
the circuit. Since all resistors are protected by the SiO: layer, any resistor may be used as a crossover
region. In other words, if aluminum metallization is run over a resistor, no electric contact will take
place between the resistor and the aluminum. Sometimes the layout is so complex that additional
crossover regions may be required. A diffused structure, useful in bipolar circuits, which allows a
crossover is obtained as follows. During the emitter fabrication, n + impurities are diffused along a
line in the epitaxial region and contact windows are opened at each end of the line. This process
forms a "diffused wire." Aluminum is deposited on the insulating Si02 (between the two end
contacts) in a line per- pendicular to the diffused section so as to form a connecting wire for some
other part of the circuit. Thus the two wires (one of aluminum and the other of « + material) cross
over each other without making electric contact. The diffused wire is called a "buried crossover." In
MOS fabrication, the equivalent of the buried crossover is accomplished by the use of a second
polysilicon layer. Consequently, component interconnection can be made by using a polysilicon
buried layer as well as with the aluminum metallization.

Computer Aided design: (CAD)

Electronic design automation (EDA), also referred to as electronic computer-aided
design (ECAD), is a category of software tools for designing electronic systems such
as integrated circuits and printed circuit boards. The tools work together in a design
flow that chip designers use to design and analyze entire semiconductor chips. Since a
modern semiconductor chip can have billions of components, EDA tools are essential for
their design.
Before EDA, integrated circuits were designed by hand, and manually laid out. Some
advanced shops used geometric software to generate the tapes for
the Gerber photoplotter, but even those copied digital recordings of mechanically drawn
components. The process was fundamentally graphic, with the translation from electronics
to graphics done manually. The best known company from this era was Calma,
whose GDSII format survives.
By the mid-1970s, developers started to automate the design along with the drafting. The
first placement and routing tools were developed. The proceedings of the Design
Automation Conference cover much of this era.
The next era began about the time of the publication of "Introduction to VLSI Systems"
by Carver Mead and Lynn Conway in 1980. This ground breaking text advocated chip design
with programming languages that compiled to silicon. The immediate result was a
considerable increase in the complexity of the chips that could be designed, with improved
access to design verification tools that used logic simulation. Often the chips were easier to
lay out and more likely to function correctly, since their designs could be simulated more
thoroughly prior to construction. Although the languages and tools have evolved, this
general approach of specifying the desired behavior in a textual programming language and
letting the tools derive the detailed physical design remains the basis of digital IC design
today.
The earliest EDA tools were produced academically. One of the most famous was the
"Berkeley VLSI Tools Tarball", a set of UNIX utilities used to design early VLSI systems. Still
widely used are the Espresso heuristic logic minimizer and Magic.
Another crucial development was the formation of MOSIS, a consortium of universities and
fabricators that developed an inexpensive way to train student chip designers by producing
real integrated circuits. The basic concept was to use reliable, low-cost, relatively low-
technology IC processes, and pack a large number of projects per wafer, with just a few
copies of each projects' chips. Cooperating fabricators either donated the processed wafers,
or sold them at cost, seeing the program as helpful to their own long-term growth.

MODERN : 1981 marks the beginning of EDA as an industry. For many years, the larger
electronic companies, such as Hewlett Packard, Tektronix, and Intel, had pursued EDA
internally. In 1981, managers and developers spun out of these companies to concentrate
on EDA as a business. Daisy Systems, Mentor Graphics, and Valid Logic Systems were all
founded around this time, and collectively referred to as DMV. Within a few years there
were many companies specializing in EDA, each with a slightly different emphasis. The first
trade show for EDA was held at the Design Automation Conference in 1984.
In 1981, the U.S. Department of Defense began funding of VHDL as a hardware description
language. In 1986, Verilog, another popular high-level design language, was first introduced
as a hardware description language by Gateway Design Automation. Simulators quickly
followed these introductions, permitting direct simulation of chip designs: executable
specifications. In a few more years, back-ends were developed to perform logic synthesis.

CURRENTLY: Current digital flows are extremely modular (see Integrated circuit
design, Design closure, and Design flow). The front ends produce standardized design
descriptions that compile into invocations of "cells,", without regard to the cell technology.
Cells implement logic or other electronic functions using a particular integrated circuit
technology. Fabricators generally provide libraries of components for their production
processes, with simulation models that fit standard simulation tools. Analog EDA tools are
far less modular, since many more functions are required, they interact more strongly, and
the components are (in general) less ideal.
EDA for electronics has rapidly increased in importance with the continuous scaling
of semiconductor technology.[2] Some users are foundry operators, who operate
the semiconductor fabrication facilities, or "fabs", and design-service companies who use
EDA software to evaluate an incoming design for manufacturing readiness. EDA tools are
also used for programming design functionality into FPGAs.

The components in an IC cannot be modified once the chip is fabri- cated. Consequently,
much more analysis of a given design is required prior to fabrication than is generally
needed for discrete-component circuits. Computer-aided design (CAD) and tools for circuit
analysis (SPICE), device fab- rication (SUPREM). and circuit layout are employed extensively.
These tools are not used to design ICs but provide the information necessary to evaluate the
effectiveness of a given design. No commercial ICs are fabricated without such analyses.
 ORCAD example of a HV floating MOS-Gate Driver ICs

Conclusion:

We do have learned that as a human civilization we have come a long way if we look
our we look how we used to make the Microelectronic circuit layout from performing
tasks by hand to making and designing with the help of Super Powerful Computers and
hence we’re still improving . Since, we keep listening to the advancements and we’re
actually living dream since as a human civilization we’re not only fabricating chips ,
SOCs , our transistors at 7nm but we’re aiming to go down to 5nm , which in reality is
just a few electrons. Also we don’t know what future has in store for us as a civilization
but as an engineers in this ever developing world , our aim should be to have a clear
mind and principle of serving humanity as well as sustainable approaches , since we
are too responsible for sustaining ourselves in future.
• Yatharth Saxena , 2K18/EC/197
• Shubham Gupta, 2K18/EC/163
• Shubham, 2K18/EC/164
• Yogesh Rathore 2K18/EC/198
 References:

• Microelectronics by Jacob Millman, Arvin Grabel

• Layout design for bipolar integrated circuits – R.H.J.M Otten EN M.C. Van
Lier
• Layout Design rules and gate layout – S.Varun
• ECAD - Wikipedia

By-
Yatharth Saxena , 2K18/EC/197
Shubham Gupta ,2K18/EC/163
Shubham ,2K18/EC/164
Yogesh Rathore , 2K18/EC/197