EE5311- Digital IC Design

Module 3 - The Inverter

Janakiraman V
Assistant Professor
Department of Electrical Engineering
Indian Institute of Technology Madras
Chennai

September 3, 2018

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 1/37

Learning Objectives

◮ Explain the functioning of a CMOS inverter

◮ Explain the Voltage Transfer Characteristics of an inverter
◮ Derive an expression for the trip point of an inverter
◮ Derive an expression for the delay of an inverter driving a
load
◮ Derive expressions for Static, Dynamic and Short Circuit
power of an inverter.

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 2/37

Outline

◮ Switch Model
◮ Transfer Characteristics
◮ Switching Threshold
◮ Noise Margin
◮ Supply Voltage Scaling
◮ Propagation Delay
◮ Power
◮ Dynamic
◮ Short circuit
◮ Leakage

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 3/37

Inverters - Robust Configuration
VDD → 0 VDD → |VT p |

VDD

0 → VDD − VT n 0 → VDD
VDD

◮ Pull down to GND with NMOS

◮ Pull up to VDD with PMOS
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 4/37
Load Line
S
Vin D
G Vout
D
S

Figure: The CMOS Inverter

IDSp = −IDSn
VGSn = Vin
VGSp = Vin − VDD
VDSn = Vout
VDSp = Vout − VDD

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 5/37

Load Line
IDn

Vin = 0 Vin = VDD

Vin = 0.7VDD
Vin = 0.4VDD
Vin = 0.5VDD

Vin = 0.7VDD
Vin = 0.4VDD
Vin = VDD Vin = 0
Vout
Figure: Solid lines- NMOS, Dashed lines - PMOS
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 6/37
Voltage Transfer Characterisitcs
Vout

Vin Vout Vin = VOut = VM

CL

1 2 3 4 5 Vin

Figure: VTC of a CMOS Inverter

Region NMOS PMOS

1 Off Lin
2 Sat Lin
3 Sat Sat
4 Lin Sat
5 Lin Off
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 7/37
Switching Threshold

Vout

Vin Vout Vin = VOut =

CL

1 2 3 4 5 Vin

Figure: Switching Threshold

◮ Both NMOS and PMOS are in saturation

◮ Assume velocity saturation
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 8/37
Switching Threshold

IDSp = −IDSn
VGSn = Vin
VGSp = Vin − VDD
VDSn = Vout
VDSp = Vout − VDD
Vin = Vout

◮ Both NMOS and PMOS are in saturation

◮ Assume velocity saturation

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 9/37

Switching Threshold
Ignoring channel length modulation
Wn VDSATn
IDSn = kn′ (VM − VTn − )VDSATn
L 2
Wp VDSATp
IDSp = kp′ (VM − VDD − VTp − )VDSATp
L 2
V
VTn + VDSATn
2
+ r (VDD + VTp + DSATp
2
)
VM =
1+r
kp (Wp /L)VDSATp
′
Wp vsatp
r= ′ =
kn (Wn /L)VDSATn Wn vsatn
r
VM ≈ VDD
r +1

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 10/37

Switing Threshold

Vout
Vin = VOut = VM

Increasing r

Vin

Figure: VTC Trip Point

Wp
Ratio of Wn
determines VM

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 11/37

Switing Threshold Without Velocity Saturation

VTn + r (VDD + VTp )

VM =
1+r r
−kp
r=
kn
Left as an exercise

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 12/37

Noise Margin
Vout

VOH
VOH
NMH
VIH
VOL
VIL VIH Vin VIL
NML
VOL

Figure: Noise Margin of a CMOS Inverter

◮ Logic levels from the driver should be recognized by the

load
◮ Points of slope -1 provide the noise margin levels
NMH = VOH − VIH
NML = VIL − VOL
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 13/37
Noise Margin Approximation
Vout

VM

VIL Vin
VIH

Figure: Noise Margin approximation of a CMOS Inverter

◮ Extend the tangent at VM

◮ Slope is the gain (g ) of the VTC
VM
NMH = VDD − VIH = VDD − VM +
g
VDD − VM
NML = VIL = VM +
g
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 14/37
Noise Margin Calculations
◮ Need to consider channel length modulation
◮ Slope is the gain (g = dVout
dVin
) of the VTC

no−clm
IDSn = IDSn (1 + λn Vout )
no−clm
IDSp = IDSp (1 + λp (Vout − VDD ))
1 kn VDSATn + kp VDSATp
g =−
ID (VM ) λn − λp
1+r
g≈
(VM − VTn − VDSATn /2)(λn − λp )
kp VDSATp
r=
kn VDSATn

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 15/37

Pass Transistors
VD
vC (0− ) = 0
VG
VD
vC (0− ) = VDD
VG

vC (t) = min(VG − VTn , VD )

vC (t) = max(VG − VTp , VD )
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 16/37
Switch Model
Vin = 0 Vin = VDD

Rp
Vin Vout
Rn
CL

Figure: The CMOS Inverter

◮ The high and low logic levels are VDD and GND(0)
◮ Logic levels are independent of sizes - Ratioless Logic
◮ Low output impedance (kΩ) - Immune to noise
◮ Large input impedance - Infinite fanout
◮ No conduction path from supply to ground in steady state
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 17/37
Switch Model Dynamic Behaviour
Vin ↓ 0 Vin ↑ VDD

Rp

Rn
CL CL

Low → High High → Low

Figure: Dynamic Behaviour of CMOS Inverter

τrise = Rp CL
τfall = Rn CL

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 18/37

Delay

◮ Propagation Delay - 50% input to 50% output

◮ Rise delay. Output goes from L ↑ H - tpLH
◮ Fall delay . Output goes from H ↓ L - tpHL
t +t
◮ Propagation delay is defined as tp = pHL 2 pLH
◮ Slew
◮ Rise time - Time taken for output to go from 10% to
90%
◮ Fall time - TIme taken for output to go from 90% to
10%

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 19/37

Delay

Vin Vout

Vin Vout
tpHL tpLH
CL
t

Figure: Delay

tpHL = Reqn CL
tpLH = Reqp CL
Reqn + Reqp
tp = CL
2
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 20/37
Transistor Sizing - Symmetric delay
◮ Rising propagation delay should be identical to falling
propagation delay.
◮ This also ensures a symmeteric VTC

tpHL = tpLH
Reqn = Reqp
CL VDD CL VDD
=
2IDSATn 2IDSATp
W n µn = W p µp
Wp ≈ 2Wn

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 21/37

Transistor Sizing - Minimum delay

CL = Cdp1 + Cdn1 + Cgn2 + Cgp2 + Cwire

Reqn + Reqp
tp = CL
2
α
tp = (0.5)[(1 + β)(Cgn2 + Cdn1 ) + Cwire ]Reqn (1 + )
β
Reqp Wp
α= @Wp = Wn ; β =
Reqn Wn
∂tp
=0
∂β
s  
Cwire
βopt = α 1 +
Cdn1 + Cgn2
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 22/37
 Power Dissipation

Energy lost as heat disspation in the devices

◮ Dynamic - Charge/ Discharging of cpacitance

◮ Short Circuit - Conductive path from VDD → GND

◮ Static - Leakage even when no activity happens

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 23/37

 Dynamic Power
Vin ↓ 0 Vin ↑ VDD

Rp

Rn
CL CL

Low → High High → Low

Figure: Capacitor charge and discharge

L↑H
Z ∞
EVDD = iVDD (t)VDD dt
0
Z ∞
EC = iVDD (t)Vout dt
0
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 24/37
 Dynamic Power

L↑H
Z ∞
EVDD = iVDD (t)VDD dt
0
Z ∞
dvout
EVDD = CL VDD dt
0 dt
Z VDD
EVDD = CL VDD dvout
0
2
EVDD = CL VDD
2
CL VDD
EC =
2

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 25/37

 Dynamic Power
C V2
◮ L ↑ H - Load capacitor charges and disspates L 2DD in
PMOS
C V2
◮ H ↓ L - Load capacitor discharges and disspates L 2DD in
NMOS
◮ Note that the energy dissipated is independent of size
◮ Depends on
◮ Probability of switching (P0→1 ) - Activity factor
◮ Frequency of operation (f )

2
Pdyn = CL VDD f0→1
2
Pdyn = CL VDD P0→1 f

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 26/37

 Short Circuit Power
VDD − VT
Vin Vout VT
Isc
Ipeak
CL

Figure: Both NMOS and PMOS conduct

Ipeak tsc IPeak tsc

Esc = VDD + VDD
2 2
Psc = tsc VDD Ipeak f
VDD + VTp − VTn
tsc = ts
VDD
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 27/37
 Static Power

ON Isubp
0 VDD VDD 0
Isubn ON

Figure: NMOS or PMOS leaks current

Pstat = Istat VDD

Ptot = Pdyn + Psc + Pstat
2
Ptot = (CL VDD + VDD Ipeak ts )f0→1 + VDD Ileak

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 28/37

Stacking Effect
◮ The intermedaite node : 0 < VX < VDD
◮ Exponentially reduces the leakage of the series stack
(I2 << I1 )
◮ Increase in VTH of the top transistor due to body effect

0 VDD 0 I1

VGS = −VX , VSB = VX

0
VX
0 VDD I2
0

VGS = 0

IT OP ∝ e(−VX −VT n )/nφt

IBOT ∝ e(−VT n )/nφt
IBOT = IT OP

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 29/37

Process Variations

◮ Impossible to manufacture tiny dimensions accurately

◮ Variations are not avoidable
◮ Process Parameters : TOX , NA , Le xj , µn , µp see
variations
◮ Performance Parameters: Currents and Voltages
◮ Process variation information (µ, σ) are provided to
designers
◮ Performance parameter variation in simulation should
match measured variations

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 30/37

Process Variations
M EAS
ID,1

MANUFACTURING
Le
M EAS
ID,2

M EAS
ID,3

NA
WAFER : 200mm (8 in) or 300mm (12 in)
SIMULATION

SHOULD MATCH

IDSIM

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 31/37

Global Variations DIFFERENT

M EAS
ID,1
M EAS
ID,2
CHIP 1
CHIP 2
M EAS
ID,1
M EAS
ID,2

SAME

WAFER : 200mm (8 in) or 300mm (12 in)

◮ All transistors within a chip affected in the same way

◮ Transistors in different chips across the wafer affected
differently

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 32/37

Global Variations
M EAS
IDP,1

FAST N
M EAS
IDP,2

SLOW N
CHIP 1

SLOW P
CHIP 2

FAST P
M EAS
IDN,1
M EAS
IDN,2

WAFER : 200mm (8 in) or 300mm (12 in)

◮ Manufacturing process of (N and P)MOS are different

◮ Transistors end up being Fast (F), Slow (S) or Typical (T)
◮ All N can get biased in one direction
◮ All P can get biased in another
◮ Corner simulation (N,P) : (TT, FS, FF, SF, SS)
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 33/37
Local Variations

◮ Transistors sitting right next to each other will be different

◮ Happens mainly due to Random Dopant Fluctuation
◮ Large transistors are affect lesser than small ones
1
(σLocal ∝ √LW )
◮ Requires large number of statistical simulations to ensure
correct functionality

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 34/37

Ring Oscillators
◮ Excellent process monitors
◮ Good representative of all digital circuits
◮ Can be added by the FAB in Kerf regions or by designers
in their chip
◮ Measure the frequency of oscilations to determine the
global process corner
◮ Can be added in multiple corners of a large chip to
measure any across chip variation

2N + 1 Inverters

TP
Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 35/37
Ring Oscillators
2N + 1 Inverters
EN

TP

TP ≈ 2x(2N + 1)τinv

◮ EN = 0 prevents any oscillations - Saves dynamic power

◮ Usually a couple of 100 INV long
◮ Very high frequency of oscillations
◮ Divided several times before being brought out of the chip

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 36/37

References

The material presented here is based on the following books/

lecture notes
1. Digital Integrated Circuits Jan M. Rabaey, Anantha
Chandrakasan and Borivoje Nikolic 2nd Edition, Prentice
Hall India

Janakiraman, IITM EE5311- Digital IC Design, Module 3 - The Inverter 37/37