UM0306

Reference manual
STM32F101xx and STM32F103xx
advanced ARM-based 32-bit MCUs

Introduction
This Reference Manual targets application developers. It provides complete information on
how to use the STM32F101xx and ST32M103xx microcontroller memory and peripherals.
The STM32F101xx and ST32M103xx will be referred to as STM32F10x throughout the
document.
The STM32F10x is a family of microcontrollers with different memory sizes, packages and
peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
STM32F101xx and ST32M103xx datasheets.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10x Flash Programming Manual.
For information on the ARM Cortex-M3 core, please refer to the Cortex-M3TM Technical
Reference Manual.

Related documents
Available from www.arm.com:
■ Cortex-M3TM Technical Reference Manual

Available from www.st.com:

■ STM32F101xx ST32M103xx datasheets
■ STM32F10x Flash Programming Manual

June 2007 Rev 1 1/519

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Contents UM0306

Contents

1 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2 Memory and bus architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.3.1 Peripheral memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.3 Bit banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.4 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . . 33
3.1.2 Battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2.1 Power On Reset (POR)/Power Down Reset (PDR) . . . . . . . . . . . . . . . . 34
3.2.2 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.3 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.1 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.3.2 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.3 SLEEP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3.4 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.3.5 STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.3.6 Auto-Wake-Up (AWU) from low-power mode . . . . . . . . . . . . . . . . . . . . . 40
3.4 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.1 Power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.2 Power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . . . . . . 43
3.5 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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4 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.1 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1.2 Power Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.1.3 Backup domain Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.2 HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2.3 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.2.4 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.5 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.6 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2.7 Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.8 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.9 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.2.10 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 RCC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3.2 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . . 54
4.3.3 Clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.4 APB2 Peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . . 60
4.3.5 APB1 Peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . . 62
4.3.6 AHB Peripheral Clock enable register (RCC_AHBENR) . . . . . . . . . . . . 64
4.3.7 APB2 Peripheral Clock enable register (RCC_APB2ENR) . . . . . . . . . . 65
4.3.8 APB1 Peripheral Clock enable register (RCC_APB1ENR) . . . . . . . . . . 67
4.3.9 Backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . . . . . . 69
4.3.10 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.4 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5 General purpose and alternate function I/O (GPIO and AFIO) . . . . . . 73

5.1 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.1.1 General purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.1.2 Atomic bit set or bit reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.3 External interrupt/wake-up lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.4 Alternate functions (AF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.1.5 Software remapping of I/O alternate functions . . . . . . . . . . . . . . . . . . . 76

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5.1.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

5.1.7 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1.8 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.9 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.1.10 Analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.2 GPIO register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.2.1 Port configuration register low (GPIOx_CRL) (x=A..E) . . . . . . . . . . . . . 80
5.2.2 Port configuration register high (GPIOx_CRH) (x=A..E) . . . . . . . . . . . . 81
5.2.3 Port input data register (GPIOx_IDR) (x=A..E) . . . . . . . . . . . . . . . . . . . 82
5.2.4 Port output data register (GPIOx_ODR) (x=A..E) . . . . . . . . . . . . . . . . . 83
5.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..E) . . . . . . . . . . . . . . . . 84
5.2.6 Port bit reset register (GPIOx_BRR) (x=A..E) . . . . . . . . . . . . . . . . . . . . 85
5.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..E) . . . . . . . . . . . 86
5.3 Alternate function I/O and debug configuration (AFIO) . . . . . . . . . . . . . . 87
5.3.1 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1 . . . . . . . . . . . 87
5.3.2 BXCAN alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.3.3 JTAG/SWD alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . 87
5.3.4 Timer alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.5 USART Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.3.6 I2C 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.7 SPI 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.4 AFIO register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.4.1 AF remap and debug I/O configuration register (AFIO_MAPR) . . . . . . . 92
5.4.2 External interrupt configuration register 1 (AFIO_EXTICR1) . . . . . . . . . 95
5.4.3 External interrupt configuration register 2 (AFIO_EXTICR2) . . . . . . . . . 95
5.4.4 External interrupt configuration register 3 (AFIO_EXTICR3) . . . . . . . . . 96
5.4.5 External interrupt configuration register 4 (AFIO_EXTICR4) . . . . . . . . . 96
5.5 GPIO and AFIO register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.5.1 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.5.2 AFIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

6 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

6.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 98
6.1.1 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.1.2 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.2 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . 101

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6.2.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.2.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.2.3 Wake-up event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.2.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.2.5 External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3 EXTI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.1 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

7 DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
7.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3.4 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.3.5 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.4 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 113
7.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 115
7.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7) . . . . . . 116
7.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7) . 117
7.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7) 118
7.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7) . 118
7.5 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

8 Real-Time Clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.3.2 Resetting RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.3.3 Reading RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8.3.4 Configuring RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.3.5 Asserting RTC flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
8.4 RTC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

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8.4.1 RTC control register High (RTC_CRH) . . . . . . . . . . . . . . . . . . . . . . . . 125

8.4.2 RTC control register low (RTC_CRL) . . . . . . . . . . . . . . . . . . . . . . . . . . 126
8.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL) . . . . . . . . . . . 128
8.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL) . . . . . . . . . . 129
8.4.5 RTC counter register (RTC_CNTH / RTC_CNTL) . . . . . . . . . . . . . . . . 130
8.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL) . . . . . . . . . . . . . . 131
8.5 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

9 Backup registers (BKP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.3 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
9.4 RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.5 BKP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
9.5.1 Backup data register x (BKP_DRx) (x = 1 ..10) . . . . . . . . . . . . . . . . . . 134
9.5.2 RTC clock calibration register (BKP_RTCCR) . . . . . . . . . . . . . . . . . . . 134
9.5.3 Backup control register (BKP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
9.5.4 Backup control/status register (BKP_CSR) . . . . . . . . . . . . . . . . . . . . . 135
9.6 BKP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.1.1 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.1.2 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.1.3 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
10.2 IWDG register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.2.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
10.2.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.2.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
10.3 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

11 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
11.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

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11.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . 146

11.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.6.1 Control Register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.6.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.6.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
11.7 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

12 Advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
12.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.4.1 Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.4.3 Repetition down-counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
12.4.4 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
12.4.5 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
12.4.6 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
12.4.7 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
12.4.8 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
12.4.9 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12.4.10 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
12.4.11 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 174
12.4.12 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
12.4.13 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 179
12.4.14 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
12.4.15 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
12.4.16 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
12.4.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.4.18 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
12.4.19 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 187
12.4.20 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.4.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.5 TIM1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.5.1 Control register 1 (TIM1_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

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12.5.2 Control register 2 (TIM1_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

12.5.3 Slave mode control register (TIM1_SMCR) . . . . . . . . . . . . . . . . . . . . . 195
12.5.4 DMA/Interrupt enable register (TIM1_DIER) . . . . . . . . . . . . . . . . . . . . 198
12.5.5 Status register (TIM1_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
12.5.6 Event generation register (TIM1_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 202
12.5.7 Capture/compare mode register 1 (TIM1_CCMR1) . . . . . . . . . . . . . . . 204
12.5.8 Capture/compare mode register 2 (TIM1_CCMR2) . . . . . . . . . . . . . . . 208
12.5.9 Capture/compare enable register (TIM1_CCER) . . . . . . . . . . . . . . . . . 209
12.5.10 Counter (TIM1_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.5.11 Prescaler (TIM1_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.5.12 Auto-reload register (TIM1_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
12.5.13 Repetition counter register (TIM1_RCR) . . . . . . . . . . . . . . . . . . . . . . . 213
12.5.14 Capture/compare register 1 (TIM1_CCR1) . . . . . . . . . . . . . . . . . . . . . 213
12.5.15 Capture/compare register 2 (TIM1_CCR2) . . . . . . . . . . . . . . . . . . . . . 214
12.5.16 Capture/compare register 3 (TIM1_CCR3) . . . . . . . . . . . . . . . . . . . . . 214
12.5.17 Capture/compare register 4 (TIM1_CCR4) . . . . . . . . . . . . . . . . . . . . . 215
12.5.18 Break and dead-time register (TIM1_BDTR) . . . . . . . . . . . . . . . . . . . . 216
12.5.19 DMA control register (TIM1_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
12.5.20 DMA address for burst mode (TIM1_DMAR) . . . . . . . . . . . . . . . . . . . . 218
12.6 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

13 General purpose timer (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
13.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.4.1 Time base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.4.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.4.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
13.4.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
13.4.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
13.4.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
13.4.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
13.4.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
13.4.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
13.4.10 One pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
13.4.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 244

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13.4.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

13.4.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
13.4.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 248
13.4.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
13.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
13.5 TIMx register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.5.1 Control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
13.5.2 Control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
13.5.3 Slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . . . . . 260
13.5.4 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . . . . . 263
13.5.5 Status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
13.5.6 Event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . . . . . 267
13.5.7 Capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . . . . . 268
13.5.8 Capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . . . . . 272
13.5.9 Capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . . . . . 274
13.5.10 Counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
13.5.11 Prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
13.5.12 Auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
13.5.13 Capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . . . . . 276
13.5.14 Capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . . . . . 277
13.5.15 Capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . . . . . 277
13.5.16 Capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . . . . . 278
13.5.17 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
13.5.18 DMA address for burst mode (TIMx_DMAR) . . . . . . . . . . . . . . . . . . . . 279
13.6 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

14 Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
14.3.1 CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.3.2 Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . . 283
14.3.3 Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.3.4 Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
14.3.5 Receive FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
14.4 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

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14.4.1 Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

14.4.2 Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
14.4.3 SLEEP mode (low power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.4.4 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.4.5 Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
14.4.6 Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.4.7 Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.5.1 Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
14.5.2 Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 289
14.5.3 Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
14.5.4 Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
14.5.5 Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
14.5.6 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
14.5.7 Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
14.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
14.7 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
14.8 CAN register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
14.8.1 Control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
14.8.2 Mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
14.8.3 CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
14.9 bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

15 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 327

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
15.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
15.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
15.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
15.4.1 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
15.4.2 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
15.4.3 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
15.4.4 SDA/SCL line control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
15.4.5 SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
15.4.6 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
15.4.7 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
15.5 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344

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15.6 I2C register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

15.6.1 Control register 1(I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
15.6.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
15.6.3 Own address register 1 (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 349
15.6.4 Own address register 2 (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 349
15.6.5 Data register (I2C_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
15.6.6 Status register 1 (I2C_SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
15.6.7 Status register 2 (I2C_SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
15.6.8 Clock control register (I2C_CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356
15.6.9 TRISE Register (I2C_TRISE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
15.7 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

16 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
16.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
16.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
16.3.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
16.3.2 SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
16.3.3 SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
16.3.4 Simplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
16.3.5 Status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
16.3.6 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
16.3.7 SPI communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
16.3.8 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
16.3.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
16.4 SPI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
16.4.1 SPI control register 1 (SPI_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
16.4.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
16.4.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
16.4.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
16.4.5 SPI CRC polynomial register (SPI_CRCPR) . . . . . . . . . . . . . . . . . . . . 374
16.4.6 SPI Rx CRC register (SPI_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 374
16.4.7 SPI Tx CRC register (SPI_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . . . 375
16.5 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

17 Universal synchronous asynchronous receiver transmitter (USART) . .

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17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377

17.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
17.2.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
17.2.2 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
17.2.3 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
17.2.4 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
17.2.5 Fractional baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
17.2.6 Multi-processor communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
17.2.7 Parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
17.2.8 LIN (local interconnection network) mode . . . . . . . . . . . . . . . . . . . . . . 392
17.2.9 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
17.2.10 Single wire half duplex communication . . . . . . . . . . . . . . . . . . . . . . . . 397
17.2.11 Smartcard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
17.2.12 IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
17.2.13 Continuous communication using DMA . . . . . . . . . . . . . . . . . . . . . . . . 401
17.2.14 Hardware flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
17.3 Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
17.4 USART register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
17.4.1 Status register (USART_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
17.4.2 Data register (USART_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
17.4.3 Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
17.4.4 Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
17.4.5 Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
17.4.6 Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
17.4.7 Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . . 417
17.5 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418

18 USB full speed device interface (USB) . . . . . . . . . . . . . . . . . . . . . . . . 419

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
18.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
18.3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
18.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
18.4.1 Description of USB blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
18.5 Programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
18.5.1 Generic USB device programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
18.5.2 System and power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

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18.5.3 Double-buffered endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

18.5.4 Isochronous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
18.5.5 Suspend/Resume events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
18.6 USB register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
18.6.1 Common registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
18.6.2 Endpoint-specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
18.6.3 Buffer descriptor table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
18.7 USB Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450

19 Analog/digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
19.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
19.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.4.1 ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.4.2 ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.4.3 Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
19.4.4 Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
19.4.5 Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
19.4.6 Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
19.4.7 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
19.4.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
19.4.9 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
19.4.10 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
19.5 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
19.6 Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
19.7 Channel-by-channel programmable sample time . . . . . . . . . . . . . . . . . . 460
19.8 Conversion on external trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
19.9 DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
19.10 Dual ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
19.10.1 Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
19.10.2 Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
19.10.3 Fast interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
19.10.4 Slow interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
19.10.5 Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
19.10.6 Independent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

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19.10.7 Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 467

19.10.8 Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 467
19.10.9 Combined injected simultaneous + interleaved . . . . . . . . . . . . . . . . . . 468
19.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
19.12 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
19.13 ADC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
19.13.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
19.13.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
19.13.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
19.13.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 477
19.13.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 478
19.13.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4) . . 479
19.13.7 ADC watchdog high threshold register (ADC_HTR) . . . . . . . . . . . . . . 479
19.13.8 ADC watchdog low threshold register (ADC_LTR) . . . . . . . . . . . . . . . 480
19.13.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 481
19.13.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 482
19.13.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 482
19.13.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 483
19.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 484
19.13.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 484
19.14 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

20 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

20.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
20.2 Referenced ARM documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
20.3 SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . 488
20.3.1 Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . . 489
20.4 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
20.4.1 SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
20.4.2 Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
20.4.3 Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . 491
20.4.4 Using serial wire and releasing the unused debug pins as GPIOs . . . 492
20.5 STM32F10x JTAG TAP connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
20.6 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
20.6.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
20.6.2 TMC TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

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20.6.3 Cortex-M3 TAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

20.6.4 Cortex-M3 JEDEC-106 ID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
20.7 This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW
Debug Port (two pins) or by the user software.JTAG debug port 494
20.8 SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
20.8.1 SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
20.8.2 SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
20.8.3 SW-DP state machine (Reset, idle states, ID code) . . . . . . . . . . . . . . 497
20.8.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
20.8.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
20.8.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
20.9 AHB-AP (AHB Access Port) - valid for both JTAG-DP or SW-DP . . . . . 499
20.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
20.11 Capability of the debugger host to connect under system reset . . . . . . 500
20.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
20.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
20.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . 501
20.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
20.14.2 Timestamp packets, synchronization and overflow packets . . . . . . . . 502
20.15 MCU debug component (MCUDBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
20.15.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 503
20.15.2 Debug support for timers and watchdog and bxCAN . . . . . . . . . . . . . . 504
20.15.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
20.16 TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
20.16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
20.16.2 Trace pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
20.16.3 TPUI formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
20.16.4 TPUI frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . . 510
20.16.5 Emission of synchronization frame packet . . . . . . . . . . . . . . . . . . . . . . 510
20.16.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
20.16.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
20.16.8 TRACECLKIN connection inside STM32F10x . . . . . . . . . . . . . . . . . . . 511
20.16.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
20.16.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
20.17 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

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21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

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UM0306 List of tables

List of tables

Table 1. Register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 2. Flash module organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 3. Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 4. Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5. SLEEP-NOW mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 6. SLEEP-ON-EXIT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7. STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 8. STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 10. RCC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 11. Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 12. Output Mode bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 13. BXCAN alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 14. Debug interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 15. Debug port mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 16. Timer 4 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 17. Timer 3 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 18. Timer 2 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 19. Timer 1 alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 20. USART3 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 21. USART2 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 22. USART1 remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 23. I2C1 Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 24. SPI1 Remapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 25. GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 26. AFIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 27. Vector table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 28. External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 107
Table 29. Summary of DMA requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 30. DMA - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 31. RTC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 32. BKP - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 33. Watchdog time-out period (with 32 kHz input clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 34. IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 35. WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 36. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 37. Output control bits for complementary OCx and OCxN channels with break feature . . . . 211
Table 38. TIM1 - Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 39. Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Table 40. Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Table 41. TIMx - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
Table 42. Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 43. Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Table 44. bxCAN - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
Table 45. SMBus vs I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
Table 46. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Table 47. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Table 48. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

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Table 49. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

Table 50. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Table 51. Error Calculation for Programmed Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Table 52. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Table 53. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Table 54. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Table 55. Double-buffering buffer flag definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Table 56. Bulk double-buffering memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Table 57. Isochronous memory buffers usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Table 58. Resume event detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Table 59. Reception status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
Table 60. Endpoint type encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Table 61. Endpoint kind meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Table 62. Transmission status encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
Table 63. Definition of allocated buffer memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Table 64. USB register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
Table 66. Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
Table 67. External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Table 68. External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Table 69. ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Table 70. ADC - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Table 71. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
Table 72. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 495
Table 73. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Table 74. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Table 75. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Table 76. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
Table 77. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Table 78. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Table 79. DBG - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Table 80. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

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List of figures

Figure 1. System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 2. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 3. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 4. Power On Reset/Power Down Reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 5. PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 6. Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 8. HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 9. Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 10. Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 11. Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 12. Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 13. High impedance-analog input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 14. External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 15. External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 16. DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 17. DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 18. RTC simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Figure 19. RTC second and alarm waveform example with PR=0003, ALARM=00004 . . . . . . . . . . 124
Figure 20. RTC Overflow waveform example with PR=0003. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 21. Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 22. Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 23. Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 24. Advanced control timer (TIM1) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 25. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 154
Figure 26. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 154
Figure 27. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 28. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 29. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 30. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 31. Counter timing diagram, Update event when ARPE=0 (TIM1_ARR not preloaded) . . . . 156
Figure 32. Counter timing diagram, Update event when ARPE=1 (TIM1_ARR preloaded) . . . . . . . 157
Figure 33. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 34. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 35. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 36. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Figure 37. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 159
Figure 38. Counter timing diagram, internal clock divided by 1, TIM1_ARR=0x6 . . . . . . . . . . . . . . . 160
Figure 39. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 40. Counter timing diagram, internal clock divided by 4, TIM1_ARR=0x36 . . . . . . . . . . . . . . 161
Figure 41. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 42. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 161
Figure 43. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 162
Figure 44. Update rate examples depending on mode and TIM1_RCR register settings . . . . . . . . . 163
Figure 45. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 46. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 47. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 48. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

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Figure 49. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Figure 50. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 167
Figure 51. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 52. Output stage of capture/compare channel (channel 1 to 3) . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 53. Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 54. PWM input mode timing.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Figure 55. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 56. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 57. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Figure 58. Complementary output with dead-time insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 59. Dead-Time waveforms with delay greater than the negative pulse. . . . . . . . . . . . . . . . . . 175
Figure 60. Dead-Time waveforms with delay greater than the positive pulse.. . . . . . . . . . . . . . . . . . 175
Figure 61. Output behavior in response to a break.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 62. Clearing TIM1 OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 63. 6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 64. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 65. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 66. Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 184
Figure 67. Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 68. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 69. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 70. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 71. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 72. General purpose timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Figure 73. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 223
Figure 74. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 224
Figure 75. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 76. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 77. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 78. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
Figure 79. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 226
Figure 80. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 227
Figure 81. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 82. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 83. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
Figure 84. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
Figure 85. Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . 229
Figure 86. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 230
Figure 87. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
Figure 88. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 231
Figure 89. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Figure 90. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 231
Figure 91. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 232
Figure 92. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 93. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 94. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 95. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 96. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Figure 97. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 235
Figure 98. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 99. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Figure 100. PWM input mode timing.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

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UM0306 List of figures

Figure 101. Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

Figure 102. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Figure 103. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Figure 104. Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 105. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Figure 106. Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 246
Figure 107. Example of encoder interface mode with IC1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 246
Figure 108. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
Figure 109. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Figure 110. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Figure 111. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Figure 112. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 113. Gating Timer 2 with OC1REF of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Figure 114. Gating Timer 2 with ENABLE of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 115. Triggering Timer 2 with UPDATE of Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 116. Triggering Timer 2 with ENABLE of Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
Figure 117. Triggering Timer 1 and 2 with Timer 1 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Figure 118. CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Figure 119. CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 120. bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
Figure 121. bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Figure 122. bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 123. bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Figure 124. Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 125. Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
Figure 126. Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
Figure 127. Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Figure 128. Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Figure 129. CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Figure 130. Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
Figure 131. CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
Figure 132. Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Figure 133. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
Figure 134. I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Figure 135. Transfer sequence diagram for slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Figure 136. Transfer sequence diagram for slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Figure 137. Transfer Sequence Diagram for Master Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Figure 138. Transfer sequence diagram for master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Figure 139. I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Figure 140. SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
Figure 141. Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 142. Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Figure 143. Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Figure 144. USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Figure 145. Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Figure 146. Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Figure 147. Data sampling for noise detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Figure 148. Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 149. Mute mode using Address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Figure 150. Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 394
Figure 151. Break detection in LIN mode vs Framing error detection . . . . . . . . . . . . . . . . . . . . . . . . . 395
Figure 152. USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

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List of figures UM0306

Figure 153. USART data clock timing diagram (M=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

Figure 154. USART data clock timing diagram (M=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Figure 155. RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Figure 156. ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Figure 157. Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
Figure 158. IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 159. IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 160. Hardware flow control between 2 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Figure 161. RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
Figure 162. CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Figure 163. USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Figure 164. USB Peripheral block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Figure 165. Packet buffer areas with examples of buffer description table locations . . . . . . . . . . . . . 425
Figure 166. Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
Figure 167. Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 168. Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
Figure 169. Injected Conversion Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
Figure 170. Calibration timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
Figure 171. Right alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Figure 172. Left alignment of data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Figure 173. Dual ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
Figure 174. Injected simultaneous mode on 4 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Figure 175. Regular simultaneous mode on 16 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Figure 176. Fast interleaved mode on 1 channel in continuous conversion mode . . . . . . . . . . . . . . . 465
Figure 177. Slow interleaved mode on 1 channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 178. Alternate trigger: injected channel group of each ADCl . . . . . . . . . . . . . . . . . . . . . . . . . . 466
Figure 179. Alternate trigger: 4 injected channels (each ADC) in discontinuous model . . . . . . . . . . . 467
Figure 180. Alternate + Regular simultaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
Figure 181. Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
Figure 182. Interleaved single channel with injected sequence CH11, CH12 . . . . . . . . . . . . . . . . . . . 468
Figure 183. Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 469
Figure 184. Block diagram of STM32F10x-level and Cortex-M3-level debug support. . . . . . . . . . . . . 487
Figure 185. JTAG TAP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493

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UM0306 Documentation conventions

1 Documentation conventions

1.1 List of abbreviations for registers

The following abbreviations are used in register descriptions:

read/write (rw) Software can read and write to these bits.

read-only (r) Software can only read these bits.

write-only (w) Software can only write to this bit. Reading the bit returns the reset value.

read-clear (rc) The software can only read or clear this bit.

Software can read as well as clear this bit by writing 1. Writing ‘0’ has no
read/clear (rc_w1)
effect on the bit value.
Software can read as well as clear this bit by writing 0. Writing ‘1’ has no
read/clear (rc_w0)
effect on the bit value.
Software can read as well as set this bit. Writing ‘0’ has no effect on the bit
read/set (rs)
value.

toggle (t) The software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.

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Memory and bus architecture UM0306

2 Memory and bus architecture

2.1 System architecture

The main system consists of:
● Four masters:
– Cortex-M3 core ICode bus (I-bus), DCode bus (D-bus), and System bus (S-bus)
– GP-DMA (General Purpose DMA)
● Three slaves:
– Internal SRAM
– Internal Flash memory
– AHB to APB bridges (AHB2APBx) which connect all the APB peripherals
These are interconnected using a Multi-Layer AHB bus architecture as shown in Figure 1:

Figure 1. System architecture

ICode
FLITF Flash
DCode memory
Cortex-M3
System

SRAM

DMA AHB System Bus Bridge 1

Ch.1
Bridge 2 APB2 APB1
Ch.2

Ch.7 GPIOA USART1 USART2 WWDG

GPIOB SPI1 USART3 CAN
GPIOC ADC1 SPI2 BKP
GPIOD ADC2 I2C1 PWR
GPIOE TIM1 I2C2 TIM2
EXTI AFIO USB TIM3
IWDG TIM4

DMA Request

ICode bus
This bus connects the Instruction bus of the Cortex-M3 core to the Flash memory instruction
interface. Prefetching is performed on this bus.

DCode bus
This bus connects the DCode bus (literal load and debug access) of the Cortex-M3 core to
the Flash memory Data interface.

System bus
This bus connects the system bus of the Cortex-M3 core (peripherals bus) to a BusMatrix
which manages the arbitration between the core and the DMA.

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UM0306 Memory and bus architecture

DMA bus
This bus connects the AHB master interface of the DMA to the BusMatrix which manages
the access of CPU DCode and DMA to SRAM, Flash memory and peripherals.

BusMatrix
The BusMatrix manages the access arbitration between the core system bus and the DMA
master bus. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of
three masters (CPU DCode, System bus and DMA bus) and three slaves (FLITF, SRAM,
and AHB2APB bridges).
AHB peripherals are connected on system bus through a BusMatrix to allow DMA access.

AHB/APB bridges (APB)

The two AHB/APB bridges provide full synchronous connections between the AHB and the
2 APB buses. APB1 is limited to 36 MHz, APB2 operates at full speed (up to 72 MHz
depending on device).
Refer to Table 1 on page 27 for the address mapping of the peripherals connected to each
bridge.

2.2 Memory organization

Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
Figure 2 on page 26 shows the STM32F10x Memory Map. For the detailed mapping of
peripheral registers, please refer to the related chapters.
The addressable memory space is divided into 8 main blocks, each of 512MB.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved” (gray shaded areas in the Figure 2 on page 26).

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Memory and bus architecture UM0306

2.3 Memory map

Figure 2. Memory map

APB Memory Space

0xFFFF FFFF
reserved
0xE010 0000
reserved
Addressable Memory Space 0x6000 0000
4 Gbytes reserved 4K
0x4002 3400
0xFFFF FFFF reserved 4K
0x4002 2400
0xFFFF F000 Flash memory Interface 1K
0x4002 2000
reserved 3K
7 0x4002 1400
RCC 1K
0xE010 0000 0x4002 1000
Cortex-M3 Internal reserved 3K
0xE000 0000 Peripherals 0x4002 0400
DMA 1K
0x4002 0000

reserved 1K
6 0x4001 3C00
USART1 1K
0x4001 3800
0xC000 0000 reserved 1K
0x4001 3400
SPI1 1K
0x4001 3000
TIM1 1K
0x4001 2C00
5 ADC2 1K
0x4001 2800
ADC1 1K
0x4001 2400
0xA000 0000
reserved 2K
0x4001 1C00
Port E 1K
4 0x1FFF FFFF 0x4001 1800
Port D 1K
reserved
0x1FFF F9FF 0x4001 1400
Port C 1K
0x8000 0000
0x4001 1000
OPTION BYTES
Port B 1K
0x1FFF F800 0x4001 0C00
Port A 1K
0x4001 0800
EXTI 1K
3 SYSTEMMEMORY 0x4001 0400
AFIO 1K
0x4001 0000
0x1FFF F000
0x6000 0000 reserved 35K
0x4000 7400
PWR 1K
0x4000 7000
2 BKP 1K
0x4000 6C00
reserved 1K
reserved 0x4000 6800
0x4000 0000 PERIPHERALS bxCAN 1K
0x4000 6400
USB SRAM 256 x 16-bit 1K
0x4000 6000
USB Registers 1K
0x4000 5C00
1 I2C2 1K
0x4000 5800
I2C1 1K
SRAM 0x4000 5400
0x2000 0000

0x0801 FFFF
reserved 2K
0x4000 4C00
USART3 1K
0 FLASH
0x4000 4800
USART2 1K
0x4000 4400

0x0000 0000
CODE 0x0800 0000 reserved 2K
0x4000 3C00
SPI2 1K
0x4000 3800
reserved 1K
0x4000 3400
IWDG 1K
0x4000 3000
WWDG 1K
Reserved 0x4000 2C00
RTC 1K
0x4000 2800

reserved 7K
0x4000 0C00
TIM4 1K
0x4000 0800
TIM3 1K
0x4000 0400
TIM2 1K
0x4000 0000

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UM0306 Memory and bus architecture

2.3.1 Peripheral memory map

Table 1. Register boundary addresses

Boundary Address Peripheral Bus Register Map

0x4002 2400 - 0x4002 3FFF Reserved

0x4002 2000 - 0x4002 23FF Flash memory interface
0x4002 1400 - 0x4002 1FFF Reserved
0x4002 1000 - 0x4002 13FF Reset and Clock control RCC AHB Section 4.4 on page 72
0x4002 0400 - 0x4002 0FFF Reserved
Section 7.5 on page
0x4002 0000 - 0x4002 03FF DMA
118
0x4001 3C00 - 0x4001 3FFF Reserved
Section 17.5 on page
0x4001 3800 - 0x4001 3BFF USART1
418
0x4001 3400 - 0x4001 37FF Reserved
Section 16.5 on page
0x4001 3000 - 0x4001 33FF SPI 1
376
Section 12.6 on page
0x4001 2C00 - 0x4001 2FFF TIM1 timer
219
Section 19.14 on page
0x4001 2800 - 0x4001 2BFF ADC2
485
Section 19.14 on page
0x4001 2400 - 0x4001 27FF ADC1
485
0x4001 2000 - 0x4001 1FFF Reserved
APB2
Section 5.5.1 on page
0x4001 1800 - 0x4001 1BFF GPIO Port E
97
Section 5.5.1 on page
0x4001 1400 - 0x4001 17FF GPIO Port D
97
Section 5.5.1 on page
0x4001 1000 - 0x4001 13FF GPIO Port C
97
Section 5.5.1 on page
0X4001 0C00 - 0x4001 0FFF GPIO Port B
97
Section 5.5.1 on page
0x4001 0800 - 0x4001 0BFF GPIO Port A
97
Section 6.2 on page
0x4001 0400 - 0x4001 07FF EXTI
101
0x4001 0000 - 0x4001 03FF AFIO Section 5.5 on page 97

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Memory and bus architecture UM0306

Table 1. Register boundary addresses (continued)

Boundary Address Peripheral Bus Register Map

0x4000 8000 - 0x4000 77FF Reserved

0x4000 7000 - 0x4000 73FF Power control PWR Section 3.5 on page 44
Section 9.6 on page
0x4000 6C00 - 0x4000 6FFF Backup registers (BKP)
137
0x4000 6800 - 0x4000 6BFF Reserved
Section 14.9 on page
0x4000 6400 - 0x4000 67FF bxCAN
324
0x4000 6000 - 0x4000 63FF USB SRAM 256 x 16-bit
Section 18.7 on page
0x4000 5C00 - 0x4000 5FFF USB Registers
450
Section 15.7 on page
0x4000 5800 - 0x4000 5BFF I2C2
358
Section 15.7 on page
0x4000 5400 - 0x4000 57FF I2C1
358
0x4000 5000 - 0x4000 4FFF Reserved
Section 17.5 on page
0x4000 4800 - 0x4000 4BFF USART3
418
APB1 Section 17.5 on page
0x4000 4400 - 0x4000 47FF USART2
418
0x4000 4000 - 0x4000 3FFF Reserved
Section 16.5 on page
0x4000 3800 - 0x4000 3BFF SPI2
376
0x4000 3400 - 0x4000 37FF Reserved
Section 10.3 on page
0x4000 3000 - 0x4000 33FF Independent watchdog (IWDG)
144
0x4000 2C00 - 0x4000 2FFF Window watchdog (WWDG)
Section 8.5 on page
0x4000 2800 - 0x4000 2BFF RTC
132
0x4000 2400 - 0x4000 0FFF Reserved
Section 13.6 on page
0x4000 0800 - 0x4000 0BFF TIM4 timer
280
Section 13.6 on page
0x4000 0400 - 0x4000 07FF TIM3 timer
280
Section 13.6 on page
0x4000 0000 - 0x4000 03FF TIM2 timer
280

2.3.2 Embedded SRAM

The STM32F10x features 20 KBytes of static SRAM. It can be accessed as bytes, half-
words (16 bits) or full words (32 bits). The SRAM start address is 0x2000 0000.

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UM0306 Memory and bus architecture

2.3.3 Bit banding

The Cortex-M3 memory map includes two bit-band regions. These regions map each word
in an alias region of memory to a bit in a bit-band region of memory. Writing to a word in the
alias region has the same effect as a read-modify-write operation on the targeted bit in the
bit-band region.
In the STM32F10x both peripheral registers and SRAM are mapped in a bit-band region.
This allows single bit-band write and read operations to be performed.
A mapping formula shows how to reference each word in the alias region to a corresponding
bit in the bit-band region. The mapping formula is:
bit_word_addr = bit_band_base + (byte_offset x 32) + (bit_number × 4)
where:
bit_word_addr is the address of the word in the alias memory region that maps to the
targeted bit.
bit_band_base is the starting address of the alias region
byte_offset is the number of the byte in the bit-band region that contains the targeted bit
bit_number is the bit position (0-31) of the targeted bit.
Example:
The following example shows how to map bit 2 of the byte located at SRAM address
0x20000300 in the alias region:
0x22006008 = 0x22000000 + (0x300*32) + (2*4).
Writing to address 0x22006008 has the same effect as a read-modify-write operation on bit
2 of the byte at SRAM address 0x20000300.
Reading address 0x22006008 returns the value (0x01 or 0x00) of bit 2 of the byte at SRAM
address 0x20000300 (0x01: bit set; 0x00: bit reset).
For more information on Bit-Banding, please refer to the Cortex-M3 Technical Reference
Manual.

2.3.4 Embedded Flash memory

The high-performance Flash memory module has the following key features:
● Density of 128 Kbytes
● Endurance: 1000 cycles
● Memory organization: the Flash memory is organized in main blocks and information
blocks:
– Main memory block of size 16K * 64 bits. Each main block is divided into 128
pages of 1Kbyte each (seeTable 2).
– Information block of size 320 * 64 bits. Each information block is divided into 2
pages or 2Kbyte and 0.5Kbyte (seeTable 2).
The Flash memory interface features:
● Read interface with prefetch buffer (2x64-bit words)
● Option byte Loader
● Flash Program / Erase operation
● Access / Write Protection

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Table 2. Flash module organization

Block Name Addresses Size (bytes)

Page 0 0x0800 0000 - 0x0800 03FF

Page 1 0x0800 0400 - 0x0800 07FF
4x 1K
Page 2 0x0800 0800 - 0x0800 0BFF
Page 3 0x0800 0C00 - 0x0800 0FFF

Main memory Page 4 to 7 0x0800 1000 - 0x0800 1FFF 4x 1K

Page 8 to 11 0x0800 2000 - 0x0800 2FFF 4x 1K
. . .
. . .
. . .
Page 124 to 127 0x0801 F000 - 0x0801 FFFF 4x 1K
System memory 0x1FFF F000 - 0x1FFF F7FF 2K
Information block
User Option Bytes 0x1FFF F800 - 0x1FFF F9FF 512
FLASH_ACR 0x4002 2000 - 0x4002 2003 4
FLASH_KEYR 0x4002 2004 - 0x4002 2007 4
FLASH_OPTKEYR 0x4002 2008 - 0x4002 200B 4
FLASH_SR 0x4002 200C - 0x4002 200F 4

Flash memory FLASH_CR 0x4002 2010 - 0x4002 2013 4

registers FLASH_AR 0x4002 2014 - 0x4002 2017 4
Reserved 0x4002 2018 - 0x4002 201B 4
FLASH_OBR 0x4002 201C - 0x4002 201F 4
FLASH_WRPR 0x4002 2020 - 0x4002 2023 4
Reserved 0x4002 2024 - 0x4002 2087 100

Note: For further information on the Flash memory registers, please refer to the STM32F10x Flash
Programming manual.

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Reading Flash memory

Flash memory instructions and data access are performed through the AHB bus. The
prefetch block is used for instruction fetches through the ICode bus. Arbitration is performed
in the Flash memory interface, and priority is given to data access on the DCode bus.
Read accesses can be performed with the following configuration options:
● Latency: Number of wait states for a read operation programmed on-the-fly (from 1 to
7).
● Prefetch: it can be enabled/disabled on-the-fly to optimize CPU execution.
● HalfCycle: for power optimization
Note: 1 These options should be used in accordance with the Flash memory access time.
2 Half cycle configuration is not available in combination with a prescaler on the AHB. The
clock system should be equal to the HCLK clock. This feature can therefore be used only
with a direct clock from 8 MHz RC Oscillator or with the Main Oscillator.
3 Enable and Disable Prefetch modes should be performed when fast clock is disabled (no
Prescaler on AHB)
4 Using DMA: DMA accesses Flash memory on the DCode bus and has priority over ICode
instructions. The DMA provides one free cycle after each transfer. Some instructions can be
performed together with DMA transfer.

Programming and erasing Flash memory

The Flash memory can be programmed 16 bits (half words) at a time.
The Flash memory erase operation can be performed at page level or on the whole Flash
area (mass-erase). The mass-erase does not affect the information blocks.
To ensure that there is no over-programming, the Flash Programming and Erase Controller
blocks are clocked by a fixed clock.
The End of write operation (programming or erasing) can trigger an interrupt. This interrupt
can be used to exit from WFI mode, only if the FLITF clock is enabled. Otherwise, the
interrupt is served only after an exit from WFI.

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2.4 Boot configuration

In the STM32F10x, 3 different boot modes can be selected through BOOT[1:0] pins as
shown in Table 3.

Table 3. Boot modes

BOOT mode
selection pins
Boot Mode Aliasing
BOOT1 BOOT0

x 0 User Flash memory User Flash memory is selected as boot space

0 1 SystemMemory SystemMemory is selected as boot space
1 1 Embedded SRAM Embedded SRAM is selected as boot space

This aliases the physical memory associated with each boot mode to Block 000 (boot
memory). The values on the BOOT pins are latched on the 4th rising edge of SYSCLK after
a Reset. It is up to the user to set the BOOT1 and BOOT0 pins after Reset to select the
required boot mode.
The BOOT pins are also re-sampled when exiting from STANDBY mode. Consequently they
must be kept in the required Boot mode configuration in STANDBY mode.
Even when aliased in the boot memory space, the related memory (Flash memory or
SRAM) is still accessible at its original memory space.
After this startup delay has elapsed, the CPU starts code execution from the boot memory,
located at the bottom of the memory address space starting from 0x0000_0000h.

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3 Power control (PWR)

3.1 Power supplies

The device requires a 2.0-3.6V operating voltage supply (VDD). An embedded regulator is
used to supply the internal 1.8V digital power.
The Real-Time Clock (RTC) and backup registers can be powered from the VBAT voltage
when the main VDD supply is powered off.

Figure 3. Power supply overview

VDDA domain
(from 0V VREF-
up to VDDA) VREF+ A/D converter
Temp. sensor
VDDA Reset block
(VDD) PLL
VSSA

VDD domain 1.8V domain

I/O Ring
VSS Core
(3.3V) STANDBY circuitry Memories
VDD (Wake-up logic, digital
IWDG) peripherals

Voltage Regulator

Low voltage detector

Backup domain
LSE crystal 32K osc
(VDD) VBAT
BKP registers
RCC BDCR register
RTC

3.1.1 Independent A/D converter supply and reference voltage

To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.
● The ADC voltage supply input is available on a separate VDDA pin.
● An isolated supply ground connection is provided on pin VSSA.
When available (according to package), VREF- must be tied to VSSA.
On 100-pin packages:
To ensure a better accuracy on low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF+ and VREF-. The voltage on VREF+ can range from 0V
to VDDA.
On packages with 64 pins or less:
The ADC voltage supply and ground are internally tied to the ADC reference voltage pins.

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3.1.2 Battery backup

To retain the content of the Backup registers when VDD is turned off, VBAT pin can be
connected to an optional standby voltage supplied by a battery or by another source.
The VBAT pin also powers the RTC unit, allowing the RTC to operate even when the main
digital supply (VDD) is turned off. The switch to the VBAT supply is controlled by the Power
Down Reset embedded in the Reset block.
If no external battery is used in the application, VBAT must be connected externally to VDD.

Warning: During the tRSTTEMPO temporization at VDD startup, the power

switch between VBAT and VDD remains connected to VBAT. As
VDD rises fast and may become established during this time,
a current may be injected into VBAT through a diode
connected between VDD and VBAT when VBAT is lower than
VDD−0.6V. Refer to the datasheet for the value of tRSTTEMPO.

3.1.3 Voltage regulator

The voltage regulator is always enabled after Reset. It works in three different modes
depending on the application modes.
● In Run mode, the regulator supplies full power to the 1.8 V domain (core, memories
and digital peripherals).
● In STOP mode the regulator supplies low-power to the 1.8 V domain, preserving
contents of registers and SRAM
● In STANDBY Mode, the regulator is powered off. The contents of the registers and
SRAM are lost except for the STANDBY circuitry and the Backup Domain.

3.2 Power supply supervisor

3.2.1 Power On Reset (POR)/Power Down Reset (PDR)

The device has an integrated POR/PDR circuitry that allows proper operation starting
from/down to 2 V.
The device remains in Reset mode when VDD is below a specified threshold, VPOR/PDR,
without the need for an external reset circuit. For more details concerning the Power
On/Power Down Reset threshold, refer to the electrical characteristics of the datasheet.

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Figure 4. Power On Reset/Power Down Reset waveform

VDD

POR

40 mV
hysteresis
PDR

Temporization
tRSTTEMPO

Reset

3.2.2 Programmable voltage detector (PVD)

You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the Power control register (PWR_CR).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the Power control/status register (PWR_CSR), to indicate if VDD
is higher or lower than the PVD threshold. This event is internally connected to the EXTI
line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output
interrupt can be generated when VDD drops below the PVD threshold and/or when VDD
rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration.
As an example the service routine could perform emergency shutdown tasks.

Figure 5. PVD thresholds

VDD

100 mV
PVD Threshold hysteresis

PVD Output

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3.3 Low-power modes

By default, the microcontroller is in Run mode after a system or a power Reset. In Run mode
the CPU is clocked by HCLK and the program code is executed. Several low-power modes
are available to save power when the CPU does not need to be kept running, for example
when waiting for an external event. It is up to the user to select the mode that gives the best
compromise between low-power consumption, short startup time and available wake-up
sources.
The STM32F10x devices feature three low-power modes:
● SLEEP mode (Cortex-M3 core stopped, peripherals kept running)
● STOP mode (all clocks are stopped)
● STANDBY mode (1.8V domain powered-off)
In addition, the power consumption in Run mode can be reduce by one of the following
means:
● Slowing down the system clocks
● Gating the clocks to the APB and AHB peripherals when they are unused.

Table 4. Low-power mode summary

Effect
Effect on 1.8V on VDD Voltage
Mode Name Entry Wake-up
domain clocks domain Regulator
clocks

SLEEP WFI Any interrupt CPU CLK OFF

(SLEEP NOW no effect on other ON
or SLEEP-ON WFE Wake-up event clocks or analog
-EXIT) clock sources
ON or in low-
power mode
PDDS and LPDS
Any EXTI line (depends on
bits +
STOP (configured in the Power
SLEEPDEEP bit None
EXTI registers) All 1.8V domain control
+ WFI or WFE
clocks OFF register
HSI and HSE (PWR_CR))
WKUP pin rising oscillators OFF
PDDS bit + edge, RTC alarm,
STANDBY SLEEPDEEP bit external reset in OFF
+ WFI or WFE NRST pin,
IWDG reset

3.3.1 Slowing down system clocks

In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 4.3.2: Clock configuration register (RCC_CFGR).

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3.3.2 Peripheral clock gating

In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped
at any time to reduce power consumption.
To further reduce power consumption in SLEEP mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB Peripheral Clock enable register
(RCC_AHBENR), APB1 Peripheral Clock enable register (RCC_APB1ENR) and APB2
Peripheral Clock enable register (RCC_APB2ENR).

3.3.3 SLEEP mode

Entering SLEEP mode
The SLEEP mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select SLEEP mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex-M3 System Control register:
● SLEEP-NOW: if the SLEEPONEXIT bit is cleared, the MCU enters SLEEP mode as
soon as WFI or WFE instruction is executed.
● SLEEP-ON-EXIT: if the SLEEPONEXIT bit is set when the WFI or WFE instruction is
executed, the MCU enters SLEEP mode as soon as it exits the lowest priority ISR.
Refer to Table 5 and Table 6 for details on how to enter SLEEP mode.

Exiting SLEEP mode

If the WFI instruction is used to enter SLEEP mode, any peripheral interrupt acknowledged
by the Nested Vectored Interrupt Controller (NVIC) can wake up the device from SLEEP
mode.
If the WFE instruction is used to enter SLEEP mode, the MCU exits SLEEP mode as soon
as an event occurs. This event can be either an interrupt enabled in the peripheral control
register but not in the NVIC, or an EXTI line configured in event mode.
This mode offers the lowest wake-up time as no time is wasted in interrupt entry/exit.
Refer to Table 5 and Table 6 for more details on how to exit SLEEP mode.

Table 5. SLEEP-NOW mode

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
Mode Entry
– SLEEPONEXIT = 0
Refer to the Cortex-M3 System Control register.
If WFI was used for entry:
Interrupt: Refer to Table 27: Vector table
Mode Exit
If WFE was used for entry
Wake-up event: Refer to Section 6.2.3: Wake-up event management
Wake-up latency None

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Table 6. SLEEP-ON-EXIT mode

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0 and
Mode Entry
– SLEEPONEXIT = 1
Refer to the Cortex-M3 System Control register.
If WFI was used for entry:
Interrupt or Reset of Cortex Control register bit 1.
Mode Exit
If WFE was used for entry:
Wake-up event: Refer to Section 6.2.3: Wake-up event management
Wake-up latency None

3.3.4 STOP mode

The STOP mode is based on the Cortex-M3 deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode. In
STOP mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC
oscillators are disabled. SRAM and register contents are preserved.

Entering STOP mode

Refer to Table 7 for details on how to enter STOP mode.
To further reduce power consumption in STOP mode, the internal voltage regulator can be
put in low-power mode. This is configured by the LPDS bit of the Power control register
(PWR_CR).
If Flash memory programming is ongoing, the STOP entry is delayed until the memory
access is finished.
If an access to APB domain is ongoing, STOP mode entry is delayed until the APB access is
finished.
In STOP mode, the following features can be selected by programming individual control
bits:
● Independent Watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 10.1 in Section 10: Independent watchdog (IWDG).
● Real-Time Clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR).
Exiting STOP mode
Refer to Table 7 for more details on how to exit STOP mode.
When exiting STOP mode by issuing an interrupt or a wake-up event, the HSI RC oscillator
is selected as system clock.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from STOP mode. By keeping the internal regulator ON during
STOP mode, the consumption is higher although the startup time is reduced.

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Table 7. STOP mode

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP bit in Cortex-M3 System Control register
– Clear PDDS bit in Power Control register (PWR_CR)
Mode Entry – Select the voltage regulator mode by configuring LPDS bit in PWR_CR

Note: To enter STOP mode, all EXTI Line pending bits (in Pending register
(EXTI_PR)) and RTC Alarm flag must be reset. Otherwise, the STOP mode
entry procedure is ignored and program execution continues.
If WFI was used for entry:
Any EXTI Line configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). Refer to Table 27: Vector
Mode Exit table on page 98
If WFE was used for entry:
Any EXTI Line configured in event mode. Refer to Section 6.2.3: Wake-
up event management on page 102
Wake-up latency None

3.3.5 STANDBY mode

The STANDBY mode allows to achieve the lowest power consumption. It is based on the
Cortex-M3 deepsleep mode, with the voltage regulator disabled. The 1.8 V domain is
consequently powered off. The PLL, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the Backup domain
and STANDBY circuitry (see Figure 3).

Entering STANDBY mode

Refer to Table 8 for more details on how to enter STANDBY mode.
In STANDBY mode, the following features can be selected by programming individual
control bits:
● Independent Watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 10.1 in Section 10: Independent watchdog (IWDG).
● Real-Time Clock (RTC): this is configured by the RTCEN bit in the Backup domain
control register (RCC_BDCR)
● Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
● External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
Backup domain control register (RCC_BDCR)
Exiting STANDBY mode
The microcontroller exits STANDBY mode when an external Reset (NRST pin), IWDG
Reset, a rising edge on WKUP pin or an RTC alarm occurs. All registers are reset after
wake-up from STANDBY except for Power control/status register (PWR_CSR).
After waking up from STANDBY mode, program execution restarts in the same way as after
a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the Power
control/status register (PWR_CSR) indicates that the MCU was in STANDBY mode.

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Refer to Table 8 for more details on how to exit STANDBY mode.

Table 8. STANDBY mode

WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– Set SLEEPDEEP in Cortex-M3 System Control register
Mode Entry
– Set PDDS bit in Power Control register (PWR_CR)
– Clear WUF bit in Power Control/Status register (PWR_CSR)
WKUP pin rising edge, RTC alarm, external Reset in NRST pin, IWDG
Mode Exit
Reset.
Wake-up latency Regulator start up. Reset phase

I/O states in STANDBY mode

In STANDBY mode, all I/O pins are high impedance except:
● Reset pad (still available)
● Anti-tamper pin if configured for tamper or calibration out
● WKUP pin, if enabled

Debug mode
The debug connection is lost if the application puts the MCU in STOP or STANDBY mode
while the debug features are used. This is due to the fact that the Cortex-M3 core is no
longer clocked.
However, the STM32F10x/ST32M103xx integrate special capabilities that allow the user to
perform software debugging in low-power modes. For more details, refer to section
Section 20.15.1: Debug support for low-power modes.

3.3.6 Auto-Wake-Up (AWU) from low-power mode

The RTC can be used to wake-up the MCU from low-power mode without depending on an
external interrupt (Auto-Wake-Up mode). The RTC provides a programmable time base for
waking-up from STOP or STANDBY mode at regular intervals. For this purpose, two of the
three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits
in the Backup domain control register (RCC_BDCR):
● Low-power 32.768 kHz external crystal oscillator (LSE OSC).
This clock source provides a precise time base with very low-power consumption (less
than 1µA added consumption in typical conditions)
● Low-power internal RC Oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC Oscillator is designed to add minimum power consumption.
To wake-up from STOP mode with an RTC alarm event, it is necessary to:
● Configure the EXTI Line 17 to be sensitive to rising edge
● Configure the RTC to generate the RTC alarm
To wake-up from STANDBY mode, there is no need to configure the EXTI Line 17.

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3.4 Power control registers

3.4.1 Power control register (PWR_CR)

Address Offset: 00h
Reset Value: 0000 0000 0000 0000 (0000h) (reset by wake-up from STANDBY mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved DBP PLS[2:0] PVDE CSBF CWUF PDDS LPDS

rw rw rw rw rw rc_w1 rc_w1 rw rw

Bits 31:9 Reserved, always read as 0.

DBP: Disable Backup Domain write protection.
In reset state, the RTC and backup registers are protected against parasitic
Bit 8 write access. This bit must be set to enable write access to these registers.
0: Access to RTC and Backup registers disabled
1: Access to RTC and Backup registers enabled
PLS[2:0]: PVD Level Selection.
These bits are written by software to select the voltage threshold detected by
the Power Voltage Detector
000: 2.2V
001: 2.3V
010: 2.4V
Bits 7:5
011: 2.5V
100: 2.6V
101: 2.7V
110: 2.8V
111: 2.9V
Note: Refer to the electrical characteristics of the datasheet for more details.
PVDE: Power Voltage Detector Enable.
This bit is set and cleared by software.
Bit 4
0: PVD disabled
1: PVD enabled
CSBF: Clear STANDBY Flag.
This bit is always read as 0.
Bit 3
0: No effect
1: Clear the SBF Standby Flag (write).
CWUF: Clear Wake-up Flag.
This bit is always read as 0.
Bit 2
0: No effect
1: Clear the WUF Wake-up Flag after 2 System clock cycles. (write)

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PDDS: Power Down Deepsleep.

This bit is set and cleared by software. It works together with the LPDS bit.
Bit 1 0: Enter STOP mode when the CPU enters Deepsleep. The regulator status
depends on the LPDS bit.
1: Enter STANDBY mode when the CPU enters Deepsleep.
LPDS: Low-Power Deepsleep.
This bit is set and cleared by software. It works together with the PDDS bit. 0:
Bit 0
Voltage regulator on during STOP mode
1: Voltage regulator in low-power mode during STOP mode

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3.4.2 Power control/status register (PWR_CSR)

Address Offset: 04h
Reset Value: 0000 0000 0000 0000 (0000h) (not reset by wake-up from STANDBY mode)
Additional APB cycles are needed to read this register versus a standard APB read.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved EWUP Reserved PVDO SBF WUF

rw r r r

Bits 31:9 Reserved, always read as 0.

EWUP: Enable WKUP pin
This bit is set and cleared by software.
0: WKUP pin is used for general purpose I/O. An event on the WKUP pin does
not wake-up the device from STANDBY mode.
Bit 8
1: WKUP pin is used for wake-up from STANDBY mode and forced in input
pull down configuration (rising edge on WKUP pin wakes-up the system from
STANDBY mode).
Note: This bit is reset by a system Reset.
Bits 7:3 Reserved, always read as 0.
PVDO: PVD Output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the
PVDE bit.
Bit 2 0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by STANDBY mode. For this reason, this bit is equal
to 0 after STANDBY or reset until the PVDE bit is set.
SBF: STANDBY Flag
This bit is set by hardware and cleared only by a POR/PDR (Power On
Reset/Power Down Reset) or by setting the CSBF bit in the Power control
Bit 1
register (PWR_CR)
0: Device has not been in STANDBY mode
1: Device has been in STANDBY mode
WUF: Wake-Up Flag
This bit is set by hardware and cleared only by a POR/PDR (Power On
Reset/Power Down Reset) or by setting the CWUF bit in the Power control
Bit 0
register (PWR_CR)
0: No wake-up event occurred
1: A wake-up event was received from the WKUP pin or from the RTC alarm

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3.5 PWR register map

The following table summarizes the PWR registers.

Table 9. PWR - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
CWUF
PDDS
PVDE
CSBF

LPDS
DBP
PWR_CR PLS[2:0]
000h Reserved
Reset Value 0 0 0 0 0 0 0 0 0

EWUP

PVDO

WUF
SBF
PWR_CSR
004h Reserved Reserved
Reset Value 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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4 Reset and clock control (RCC)

4.1 Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.

4.1.1 System Reset

A system Reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 3.).
A system Reset is generated when one of the following events occurs:
1. A low level on the NRST pin (External Reset)
2. Window Watchdog end of count condition (WWDG Reset)
3. Independent Watchdog end of count condition (IWDG Reset)
4. A software Reset (SW Reset) (see Section : Software Reset)
5. Low-power management Reset (see Section : Low-power management Reset)
The reset source can be identified by checking the Reset flags in the Control/Status register,
RCC_CSR (see Section 4.3.10: Control/status register (RCC_CSR)).

Software Reset
The SYSRESETREQ bit in Cortex-M3 Application Interrupt and Reset Control Register
must be set to force a software Reset on the device. Refer to the Cortex-M3 technical
reference manual for more details.

Low-power management Reset

There are two ways to generate a low-power management Reset:
1. Reset generated when entering STANDBY mode:
This type of reset is enabled by resetting nRST_STDBY bit in User Option Bytes. In this
case, whenever a STANDBY mode entry sequence is successfully executed, the
device is reset instead of entering STANDBY mode.
2. Reset when entering STOP mode:
This type of reset is enabled by resetting nRST_STOP bit in User Option Bytes. In this
case, whenever a STOP mode entry sequence is successfully executed, the device is
reset instead of entering STOP mode.
For further information on the User Option Bytes, refer to the STM32F10x Flash
Programming Manual.

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4.1.2 Power Reset

A power Reset is generated when one of the following events occurs:
1. Power On/Power down Reset (POR/PDR Reset)
2. When exiting STANDBY mode
A power Reset sets all registers to their reset values except the Backup domain (see
Figure 3)
These sources act on the RESET pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at addresses 0x0000_0000-0x0000_0004 in the memory
map.

Figure 6. Reset circuit

VDD

RON
EXTERNAL SYSTEM NRESET
RESET Filter
NRST

WWDG Reset
PULSE
IWDG Reset
GENERATOR POR/PDR Reset
(min 20µs) Software Reset
Low-power management Reset

The Backup domain has two specific resets that affect only the Backup domain (see
Figure 3)

4.1.3 Backup domain Reset

A backup domain Reset is generated when one of the following events occurs:
1. Software Reset, triggered by setting the BDRST bit in the Backup domain control
register (RCC_BDCR).
2. VDD or VBAT power on, if both supplies have previously been powered off.

4.2 Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
● HSI oscillator clock
● HSE oscillator clock
● PLL clock
The devices have the following two secondary clock sources:
● 32 kHz Low Speed Internal RC (LSI RC) which drives the Independent Watchdog and
optionally the RTC used for Auto Wake-up from STOP/STANDBY mode.
● 32.768 kHz Low Speed External crystal (LSE crystal) which optionally drives the Real-
Time Clock (RTCCLK)

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Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.

Figure 7. Clock tree

8 MHz
HSI RC HSI USBCLK
USB 48 MHz
Prescaler to USB interface
/2 /1, 1.5
HCLK
72 MHz max to AHB bus, core,
Clock memory and DMA
Enable (3 bits)
/8 to Cortex System timer
PLLSRC SW
PLLMUL FCLK Cortex
HSI free running clock
..., x16 SYSCLK AHB APB1
36 MHz max PCLK1
x2, x3, x4 PLLCLK 72 MHz
Prescaler Prescaler
to APB1
PLL max /1, 2 ..512 /1, 2, 4, 8, 16 peripherals
Peripheral Clock
HSE
Enable (13 bits)
to TIM2, 3
TIM2, 3, 4 and 4
CSS x1, 2 Multiplier TIMXCLK
Peripheral Clock
Enable (3 bits)
PLLXTPRE APB2
72 MHz max PCLK2
Prescaler
OSC_OUT to APB2
4-16 MHz /1, 2, 4, 8, 16 peripherals
Peripheral Clock
HSE OSC Enable (11 bits)
OSC_IN /2
TIM1 Timer to TIM1
x1, 2 Multiplier TIM1CLK
Peripheral Clock
/128 Enable (1 bit)
ADC to ADC
OSC32_IN to RTC Prescaler
LSE OSC LSE ADCCLK
32.768 kHz RTCCLK /2, 4, 6, 8
OS32_OUT
RTCSEL[1:0]

to Independent Watchdog (IWDG)

LSI RC LSI
32 kHz IWDGCLK

Main /2 PLLCLK Legend:

Clock Output HSE = High Speed External clock signal
MCO HSI HSI = High Speed Internal clock signal
HSE LSI = Low Speed Internal clock signal
SYSCLK LSE = Low Speed External clock signal
MCO

Several prescalers allow the configuration of the AHB frequency, the high speed APB
(APB2) and the low speed APB (APB1) domains. The AHB and the APB2 domains
maximum frequency is 72 MHz. The APB1 domains maximum allowed frequency is 36
MHz. The RCC feeds the Cortex System Timer (SysTick) external clock with the AHB clock
divided by 8. The SysTick can work either with this clock or with the Cortex clock (AHB),
configurable in the SysTick Control and Status Register. The ADCs are clocked by the clock
of the High Speed domain (APB2) divided by 2, 4, 6 or 8.

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The timer clock frequencies are twice the frequency of the APB domain which they are
connected to. Nevertheless, if the APB prescaler is 1, the clock frequency of the timer is the
same as the frequency of the APB domain which it is connected to.
FCLK acts as Cortex-M3 free running clock. For more details refer to the ARM Cortex-M3
Technical Reference Manual.

4.2.1 HSE clock

The High Speed External clock signal (HSE) can be generated from two possible clock
sources:
● HSE external crystal/ceramic resonator
● HSE user external clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.

Figure 8. HSE/ LSE clock sources

Hardware Configuration
External Clock

OSC_OUT

(HiZ)

EXTERNAL
SOURCE
Crystal/Ceramic Resonators

OSC_IN OSC_OUT

CL1 CL2
LOAD
CAPACITORS

External source (HSE bypass)

In this mode, an external clock source must be provided. It can have a frequency of up to 25
MHz. You select this mode by setting the HSEBYP and HSEON bits in the Clock control
register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty
cycle has to drive the OSC_IN pin while the OSC_OUT pin should be left hi-Z. See Figure 8.

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External crystal/ceramic resonator (HSE crystal)

The 4 to 16 MHz external oscillator has the advantage of producing a very accurate rate on
the main clock.
The associated hardware configuration is shown in Figure 8. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the Clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the Clock control
register (RCC_CR).

4.2.2 HSI clock

The HSI clock signal is generated from an internal 8 MHz RC Oscillator and can be used
directly as a system clock or divided by 2 to be used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.

Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at TA=25°C.
After Reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the Clock
control register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the Clock control register (RCC_CR).
The HSIRDY flag in the Clock control register (RCC_CR) indicates if the HSI RC is stable or
not. At startup, the HSI RC output clock is not released until this bit is set by hardware.
The HSI RC can be switched on and off using the HSION bit in the Clock control register
(RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 4.2.7: Clock security system (CSS) on page 51.

4.2.3 PLL
The internal PLL can be used to multiply the HSI RC output or HSE crystal output clock
frequency. Refer to Figure 7 and Clock control register (RCC_CR).
The PLL configuration (selection of HSI oscillator divided by 2 or HSE oscillator for PLL
input clock, and multiplication factor) must be done before enabling the PLL. Once the PLL
enabled, these parameters cannot be changed.
An interrupt can be generated when the PLL is ready if enabled in the Clock interrupt
register (RCC_CIR).

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If the USB interface is used in the application, the PLL must be programmed to output 48 or
72 MHz. This is needed to provide a 48 MHz USBCLK.

4.2.4 LSE clock

The LSE crystal is a 32.768 kHz Low Speed External crystal or ceramic resonator. It has the
advantage providing a low-power but highly accurate clock source to the Real-Time Clock
peripheral (RTC) for clock/calendar or other timing functions.
The LSE crystal is switched on and off using the LSEON bit in Backup domain control
register (RCC_BDCR).
The LSERDY flag in the Backup domain control register (RCC_BDCR) indicates if the LSE
crystal is stable or not. At startup, the LSE crystal output clock signal is not released until
this bit is set by hardware. An interrupt can be generated if enabled in the Clock interrupt
register (RCC_CIR).

External source (LSE bypass)

In this mode, an external clock source must be provided. It must have a frequency of 32.768
kHz. You select this mode by setting the LSEBYP and LSEON bits in the Backup domain
control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with
~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left hi-
Z. See Figure 8.

4.2.5 LSI clock

The LSI RC acts as an low-power clock source that can be kept running in STOP and
STANDBY mode for the independent watchdog (IWDG) and Auto-Wake-Up unit (AWU). The
clock frequency is around 32 kHz (between 30 kHz and 60 kHz). For more details, refer to
the electrical characteristics section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the Control/status register
(RCC_CSR).
The LSIRDY flag in the Control/status register (RCC_CSR) indicates if the low-speed
internal oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the Clock interrupt register
(RCC_CIR).

4.2.6 System clock (SYSCLK) selection

After a system Reset, the HSI oscillator is selected as system clock. When a clock source is
used directly or through the PLL as system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source which is not yet ready is
selected, the switch will occur when the clock source will be ready. Status bits in the Clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as system clock.

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4.2.7 Clock security system (CSS)

Clock Security System can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled, a
clock failure event is sent to the break input of the TIM1 Advanced control timer and an
interrupt is generated to inform the software about the failure (Clock Security System
Interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
Note: Once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is
automatically generated. The NMI will be executed indefinitely unless the CSS interrupt
pending bit is cleared. As a consequence, in the NMI ISR user must clear the CSS interrupt
by setting the CSSC bit in the Clock interrupt register (RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is
used as PLL input clock, and the PLL clock is used as system clock), a detected failure
causes a switch of the system clock to the HSI oscillator and the disabling of the external
HSE oscillator. If the HSE oscillator clock (divided or not) is the clock entry of the PLL used
as system clock when the failure occurs, the PLL is disabled too.

4.2.8 RTC clock

The RTCCLK clock source can be either the HSE/128, LSE or LSI clocks. This is selected
by programming the RTCSEL[1:0] bits in the Backup domain control register (RCC_BDCR).
This selection cannot be modified without resetting the Backup domain.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not.
Consequently:
● If LSE is selected as RTC clock:
– The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
● If LSI is selected as Auto-Wake-up unit (AWU) clock:
– The AWU state is not guaranteed if the VDD supply is powered off.
● If the HSE clock divided by 128 is used as RTC clock:
– The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.8 V domain).

4.2.9 Watchdog clock

If the Independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.

4.2.10 Clock-out capability

The microcontroller clock output (MCO) capability allows the clock to be output onto the
external MCO pin. The configuration registers of the corresponding GPIO port must be

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programmed in alternate function mode. One of 4 clock signals can be selected as the MCO
clock.
● SYSCLK
● HSI
● HSE
● PLL clock divided by 2
The selection is controlled by the MCO[2:0] bits of the Clock configuration register
(RCC_CFGR).

4.3 RCC register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

4.3.1 Clock control register (RCC_CR)

Address offset: 00h
Reset value: 0000 0083h
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL CSS HSE HSE HSE

Reserved PLLON Reserved
RDY ON BYP RDY ON

r rw rw rw r rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HSI
HSI CAL[7:0] HSI TRIM[4:0] Res. HSION
RDY

r r r r r r r r rw rw rw rw rw r rw

Bits 31:26 Reserved, always read as 0.

PLLRDY PLL clock ready flag
Set by hardware to indicate that the PLL is locked.
Bit 25
0: PLL unlocked
1: PLL locked
PLLON PLL enable
Set and reset by software to enable PLL.
Reset by hardware when entering STOP and STANDBY mode. This bit can not
Bit 24 be reset if the PLL clock is used as system clock or is selected to become the
system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, always read as 0.
CSSON Clock Security System enable
Set and reset by software to enable clock detector.
Bit 19
0: Clock detector OFF
1: Clock detector ON if external 1-25 MHz oscillator is ready.

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HSEBYP External High Speed clock Bypass

Set and reset by software in debug for bypassing oscillator with external clock.
Bit 18 This bit can be written only if the external 1-25 MHz oscillator is disabled.
0: external 1-25 MHz oscillator not bypassed
1: external 1-25 MHz oscillator bypassed with external clock
HSERDY External High Speed clock ready flag
Set by hardware to indicate that external 1-25 MHz oscillator is stable. This bit
needs 6 cycles of external 1-25 MHz oscillator clock to fall down after HSEON
Bit 17
reset.
0: external 1-25 MHz oscillator not ready
1: external 1-25 MHz oscillator ready
HSEON External High Speed clock enable
Set and reset by software.
Reset by hardware to stop the external 1-25MHz oscillator when entering in
STOP and STANDBY mode. This bit can not be reset if the external 1-25 MHz
Bit 16
oscillator is used directly or indirectly as system clock or is selected to become
the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
HSICAL[7:0] Internal High Speed clock Calibration
Bits 15:8
These bits are initialized automatically at startup.
HSITRIM[4:0] Internal High Speed clock trimming
Bits 7:3 These bits can be written by software to adjust calibration. They are added to the
value of the HSICAL[5:0] bits.
Bit 2 Reserved, always read as 0.
HSIRDY Internal High Speed clock ready flag
Set by hardware to indicate that internal 8 MHz RC oscillator is stable. This bit
needs 6 cycles of the internal 8 MHz RC oscillator clock to fall down after HSION
Bit 1
reset.
0: internal 8 MHz RC oscillator not ready
1: internal 8 MHz RC oscillator ready
HSION Internal High Speed clock enable
Set and reset by software.
Set by hardware to force the internal 8 MHz RC oscillator ON when leaving STOP
and STANDBY mode or in case of failure of the external 1-25 MHz oscillator used
Bit 0 directly or indirectly as system clock. This bit can not be reset if the internal 8
MHz RC is used directly or indirectly as system clock or is selected to become the
system clock.
0: internal 8 MHz RC oscillator OFF
1: internal 8 MHz RC oscillator ON

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4.3.2 Clock configuration register (RCC_CFGR)

Address offset: 04h
Reset value: 0000 0000h
Access: 0 <= wait state <= 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during clock source switch.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USB PLL PLL

Reserved MCO[2:0] Res. PLLMUL[3:0]
PRE XTPRE SRC

rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADC PRE[1:0] PPRE2[2:0] PPRE1[2:0] HPRE[3:0] SWS[1:0] SW[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw r r rw rw

Bits 31:26 Reserved, always read as 0.

MCO Microcontroller Clock Output
Set and reset by software.
0xx: No clock
100: System clock selected
101: Internal 8 MHz RC oscillator clock selected
Bits 26:24 110: External 1-25 MHz oscillator clock selected
111: PLL clock divided by 2 selected
Notes:
This clock is not glitch-free and should be used only for debug purposes.
When the System Clock is selected to output onto MCO, make sure that this clock
does not exceed 50 MHz (the maximum I/O speed).
USBPRE USB prescaler
Set and reset by software to generate 48 MHz USB clock. This bit must be valid
before enabling the USB clock in the RCC_APB1ENR register. This bit can’t be
Bit 22
reset if the USB clock is enabled.
0: PLL clock is divided by 1.5
1: PLL clock is not divided

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PLLMUL PLL Multiplication Factor

These bits are written by software to define the PLL multiplication factor. These
bits can be written only when PLL is disabled.
Caution: The PLL output frequency must not exceed 72 MHz.
0000: PLL input clock x 2
0001: PLL input clock x 3
0010: PLL input clock x 4
0011: PLL input clock x 5
0100: PLL input clock x 6
0101: PLL input clock x 7
Bits 21:18
0110: PLL input clock x 8
0111: PLL input clock x 9
1000: PLL input clock x 10
1001: PLL input clock x 11
1010: PLL input clock x 12
1011: PLL input clock x 13
1100: PLL input clock x 14
1101: PLL input clock x 15
1110: PLL input clock x 16
1111: PLL input clock x 16
PLLXTPRE HSE divider for PLL entry
Set and reset by software to divide HSE before PLL entry. This bit can be written
Bit 17 only when PLL is disabled.
0: HSE clock not divided
1: HSE clock divided by 2
PLLSRC PLL entry clock source
Set and reset by software to select PLL clock source. This bit can be written only
Bit 16 when PLL is disabled.
0: HSI oscillator clock / 2 selected as PLL input clock
1: HSE oscillator clock selected as PLL input clock
ADCPRE ADC prescaler
Set and reset by software to select the frequency of the clock to the ADCs.
00: PLCK2 divided by 2
Bits 14:12
01: PLCK2 divided by 4
10: PLCK2 divided by 6
11: PLCK2 divided by 8
PPRE2 APB High speed prescaler (APB2)
Set and reset by software to control APB High speed clocks division factor.
0xx: HCLK not divided
Bits 13:11 100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16

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PPRE1 APB Low speed prescaler (APB1)

Set and reset by software to control APB Low speed clocks division factor.
Warning: the software has to set correctly these bits to not exceed 36 MHz on this
domain.
Bits 10:8 0xx: HCLK not divided
100: HCLK divided by 2
101: HCLK divided by 4
110: HCLK divided by 8
111: HCLK divided by 16
HPRE AHB prescaler
Set and reset by software to control AHB clock division factor.
0xxx: SYSCLK not divided
1000: SYSCLK divided by 2
1001: SYSCLK divided by 4
Bits 7:4 1010: SYSCLK divided by 8
1011: SYSCLK divided by 16
1100: SYSCLK divided by 64
1101: SYSCLK divided by 128
1110: SYSCLK divided by 256
1111: SYSCLK divided by 512
SWS System Clock Switch Status
Set and reset by hardware to indicate which clock source is used as system clock.
00: HSI oscillator used as system clock
Bits 3:2
01: HSE oscillator used as system clock
10: PLL used as system clock
11: not applicable
SW System clock Switch
Set and reset by software to select SYSCLK source.
Set by hardware to force HSI selection when leaving STOP and STANDBY mode
or in case of failure of the HSE oscillator used directly or indirectly as system
Bits 1:0 clock (if the Clock Security System is enabled).
00: HSI selected as system clock
01: HSE selected as system clock
10: PLL selected as system clock
11: not allowed

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4.3.3 Clock interrupt register (RCC_CIR)

Address offset: 08h
Reset value: 0000 0000h
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PLL HSE HSI LSE LSI

Reserved CSSC Reserved
RDYC RDYC RDYC RDYC RDYC

w w w w w w

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PLL HSE HSI LSE LSI PLL HSE HSI LSE LSI
Reserved CSSF Reserved
RDYIE RDYIE RDYIE RDYIE RDYIE RDYF RDYF RDYF RDYF RDYF

rw rw rw rw rw r r r r r r

Bits 31:24 Reserved, always read as 0.

CSSC Clock Security System Interrupt Clear
Set by software to clear CSSF.
Bit 23 Reset by hardware when clear done.
0: CSSF not cleared
1: CSSF cleared
Bits 22:21 Reserved, always read as 0.
PLLRDYC PLL Ready Interrupt Clear
Set by software to clear PLLRDYF.
Bit 20 Reset by hardware when clear done.
0: PLLRDYF not cleared
1: PLLRDYF cleared
HSERDYC HSE Ready Interrupt Clear
Set by software to clear HSERDYF.
Bit 19 Reset by hardware when clear done.
0: HSERDYF not cleared
1: HSERDYF cleared
HSIRDYC HSI Ready Interrupt Clear
Set by software to clear HSIRDYF.
Bit 18 Reset by hardware when clear done.
0: HSIRDYF not cleared
1: HSIRDYF cleared
LSERDYC LSE Ready Interrupt Clear
Set by software to clear LSERDYF.
Bit 17 Reset by hardware when clear done.
0: LSERDYF not cleared
1: LSERDYF cleared

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LSIRDYC LSI Ready Interrupt Clear

Set by software to clear LSIRDYF.
Bit 16 Reset by hardware when clear done.
0: LSIRDYF not cleared
1: LSIRDYF cleared
Bits 15:13 Reserved, always read as 0.
PLLRDYIE PLL Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by PLL lock.
Bit 12
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
HSERDYIE HSE Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the external 1-25
Bit 11 MHz oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
HSIRDYIE HSI Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the internal 8
Bit 10 MHz RC oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
LSERDYIE LSE Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by the external 32
Bit 9 kHz oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
LSIRDYIE LSI Ready Interrupt Enable
Set and reset by software to enable/disable interrupt caused by internal RC 32
Bit 8 kHz oscillator stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
CSSF Clock Security System Interrupt flag
Reset by software by writing CSSC.
Bit 7 Set by hardware when a failure is detected in the external 1-25 MHz oscillator.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bits 6:5 Reserved, always read as 0.
PLLRDYF PLL Ready Interrupt flag
Reset by software by writing PLLRDYC.
Bit 4 Set by hardware when the PLL locks and PLLRDYDIE is set.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
HSERDYF HSE Ready Interrupt flag
Reset by software by writing HSERDYC.
Set by hardware when External Low Speed clock becomes stable and
Bit3
HSERDYDIE is set.
0: No clock ready interrupt caused by the external 1-25 MHz oscillator
1: Clock ready interrupt caused by the external 1-25 MHz oscillator

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HSIRDYF HSI Ready Interrupt flag

Reset by software by writing HSIRDYC.
Set by hardware when the Internal High Speed clock becomes stable and
Bit 2
HSIRDYDIE is set.
0: No clock ready interrupt caused by the internal 8 MHz RC oscillator
1: Clock ready interrupt caused by the internal 8 MHz RC oscillator
LSERDYF LSE Ready Interrupt flag
Reset by software by writing LSERDYC.
Set by hardware when the External Low Speed clock becomes stable and
Bit 1
LSERDYDIE is set.
0: No clock ready interrupt caused by the external 32 kHz oscillator
1: Clock ready interrupt caused by the external 32 kHz oscillator
LSIRDYF LSI Ready Interrupt flag
Reset by software by writing LSIRDYC.
Set by hardware when Internal Low Speed clock becomes stable and LSIRDYDIE
Bit 0
is set.
0: No clock ready interrupt caused by the internal RC 32 kHz oscillator
1: Clock ready interrupt caused by the internal RC 32 kHz oscillator

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4.3.4 APB2 Peripheral reset register (RCC_APB2RSTR)

Address offset: 0Ch
Reset value: 0000 0000h
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USART
SPI1 TIM1 ADC2 ADC1 IOPE IOPD IOPC IOPB IOPA AFIO
Res. 1 Res. Reserved Res.
RST RST RST RST RST RST RST RST RST RST
RST

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, always read as 0.

USART1RST USART1 reset
Set and reset by software.
Bit 14
0: No effect
1: Reset USART1
Bit 13 Reserved, always read as 0.
SPI1RST SPI 1 reset
Set and reset by software.
Bit 12
0: No effect
1: Reset SPI 1
TIM1RST TIM1 Timer reset
Set and reset by software.
Bit 11
0: No effect
1: Reset TIM1 timer
ADC2RST ADC 2 interface reset
Set and reset by software.
Bit 10
0: No effect
1: Reset ADC 2 interface
ADC1RST ADC 1 interface reset
Set and reset by software.
Bit 9
0: No effect
1: Reset ADC 1 interface
Bits 8:7 Reserved, always read as 0.
IOPERST IO port E reset
Set and reset by software.
Bit 6
0: No effect
1: Reset IO port E

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UM0306 Reset and clock control (RCC)

IOPDRST IO port D reset

Set and reset by software.
Bit 5
0: No effect
1: Reset I/O port D
IOPCRST IO port C reset
Set and reset by software.
Bit 4
0: No effect
1: Reset I/O port C
IOPBRST IO port B reset
Set and reset by software.
Bit 3
0: No effect
1:Reset I/O port B
IOPARST I/O port A reset
Set and reset by software.
Bit 2
0: No effect
1: Reset I/O port A
Bit 1 Reserved, always read as 0.
AFIORST Alternate Function I/O reset
Set and reset by software.
Bit 0
0: No effect
1: Reset Alternate Function

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Reset and clock control (RCC) UM0306

4.3.5 APB1 Peripheral reset register (RCC_APB1RSTR)

Address offset: 10h
Reset value: 0000 0000h
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

USART USART
PWR BKP CAN USB I2C2 I2C1
Reserved Res. Res. Reserved 3 2 Res.
RST RST RST RST RST RST
RST RST

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI2 WWD TIM4 TIM3 TIM2

Res. Reserved Reserved
RST GRST RST RST RST

rw rw rw rw rw

Bits 31:29 Reserved, always read as 0.

PWRRST Power interface reset
Set and reset by software.
Bit 28
0: No effect
1: Reset power interface
BKPRST Backup interface reset
Set and reset by software.
Bit 27
0: No effect
1: Reset backup interface
Bit 26 Reserved, always read as 0.
CANRST CAN reset
Set and reset by software.
Bit 25
0: No effect
1: Reset CAN
Bit 24 Reserved, always read as 0.
USBRST USB reset
Set and reset by software.
Bit 23
0: No effect
1: Reset USB
I2C2RST I2C 2 reset
Set and reset by software.
Bit 22
0: No effect
1: Reset I2C 2
I2C1RST I2C 1 reset
Set and reset by software.
Bit 21
0: No effect
1: Reset I2C 1

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UM0306 Reset and clock control (RCC)

Bits 20:19 Reserved, always read as 0.

USART3RST USART 3 reset
Set and reset by software.
Bit 18
0: No effect
1: Reset USART 3
USART2RST USART 2 reset
Set and reset by software.
Bit 17
0: No effect
1: Reset USART 2
Bits 16:15 Reserved, always read as 0.
SPI2RST SPI 2 reset
Set and reset by software.
Bit 14
0: No effect
1: Reset SPI 2
Bits 13:12 Reserved, always read as 0.
WWDGRST Window Watchdog reset
Set and reset by software.
Bit 11
0: No effect
1: Reset window watchdog
Bits 10:3 Reserved, always read as 0.
TIM4RST Timer 4 reset
Set and reset by software.
Bit 2
0: No effect
1: Reset timer 4
TIM3RST Timer 3 reset
Set and reset by software.
Bit 1
0: No effect
1: Reset timer 3
TIM2RST Timer 2 reset
Set and reset by software.
Bit 0
0: No effect
1: Reset timer 2

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Reset and clock control (RCC) UM0306

4.3.6 AHB Peripheral Clock enable register (RCC_AHBENR)

Address offset: 14h
Reset value: 0000 0014h
Access: no wait state, word, half-word and byte access

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FLITF SRAM DMA

Reserved Res. Res.
EN EN EN

rw rw rw

Bits 31:5 Reserved, always read as 0.

FLITFEN FLITF clock enable
Set and reset by software to disable/enable FLITF clock during sleep mode.
Bit 4
0: FLITF clock disabled during SLEEP mode
1: FLITF clock enabled during SLEEP mode
Bit 3 Reserved, always read as 0.
SRAMEN SRAM interface clock enable
Set and reset by software to disable/enable SRAM interface clock during SLEEP
Bit 2 mode.
0: SRAM interface clock disabled during SLEEP mode.
1: SRAM interface clock enabled during SLEEP mode
Bit 1 Reserved, always read as 0.
DMAEN DMA clock enable
Set and reset by software.
Bit 0
0: DMA clock disabled
1: DMA clock enabled

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UM0306 Reset and clock control (RCC)

4.3.7 APB2 Peripheral Clock enable register (RCC_APB2ENR)

Address: 18h
Reset value: 0000 0000h
Access: word, half-word and byte access
No wait states, except if the access occurs while an access to a peripheral in APB2 domain
is on going. In this case, wait states are inserted until this access to APB2 peripheral is
finished.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

USAR
SPI1 TIM1 ADC2 ADC1 IOPE IOPD IOPC IOPB IOPA AFIO
Res; T1 Res; Reserved Res.
EN EN EN EN EN EN EN EN EN EN
EN

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, always read as 0.

USART1EN USART1 clock enable
Set and reset by software.
Bit 14
0: USART1 clock disabled
1: USART1 clock enabled
Bit 13 Reserved, always read as 0.
SPI1EN SPI 1 clock enable
Set and reset by software.
Bit 12
0: SPI 1 clock disabled
1: SPI 1 clock enabled
TIM1EN TIM1 Timer clock enable
Set and reset by software.
Bit 11
0: TIM1 timer clock disabled
1: TIM1 timer clock enabled
ADC2EN ADC 2 interface clock enable
Set and reset by software.
Bit 10
0: ADC 2 interface clock disabled
1: ADC 2 interface clock enabled
ADC1EN ADC 1 interface clock enable
Set and reset by software.
Bit 9
0: ADC 1 interface disabled
1: ADC 1 interface clock enabled
Bits 8:7 Reserved, always read as 0.

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Reset and clock control (RCC) UM0306

IOPEEN I/O port E clock enable

Set and reset by software.
Bit 6
0: I/O port E clock disabled
1: I/O port E clock enabled
IOPDEN I/O port D clock enable
Set and reset by software.
Bit 5
0: I/O port D clock disabled
1: I/O port D clock enabled
IOPCEN I/O port C clock enable
Set and reset by software.
Bit 4
0: I/O port C clock disabled
1:I/O port C clock enabled
IOPBEN I/O port B clock enable
Set and reset by software.
Bit 3
0: I/O port B clock disabled
1:I/O port B clock enabled
IOPAEN I/O port A clock enable
Set and reset by software.
Bit 2
0: I/O port A clock disabled
1:I/O port A clock enabled
Bit 1 Reserved, always read as 0.
AFIOEN Alternate Function I/O clock enable
Set and reset by software.
Bit 0
0: Alternate Function I/O clock disabled
1:Alternate Function I/O clock enabled

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UM0306 Reset and clock control (RCC)

4.3.8 APB1 Peripheral Clock enable register (RCC_APB1ENR)

Address: 1Ch
Reset value: 0000 0000h
Access: word, half-word and byte access
No wait state, except if the access occurs while an access to a peripheral on APB1 domain
is on going. In this case, wait states are inserted until this access to APB1 peripheral is
finished.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

PWR BKP CAN USB I2C2 I2C1 USART3 USART2

Reserved Res. Res. Reserved Res.
EN EN EN EN EN EN EN EN

rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SPI2 WWD TIM4 TIM3 TIM2

Res. Reserved Reserved
EN GEN EN EN EN

rw rw rw rw rw

Bits 31:29 Reserved, always read as 0.

PWREN Power interface clock enable
Set and reset by software.
Bit 28
0: Power interface clock disabled
1: Power interface clock enable
BKPEN Backup interface clock enable
Set and reset by software.
Bit 27
0: Backup interface clock disabled
1: Backup interface clock enabled
Bit 26 Reserved, always read as 0.
CANEN CAN clock enable
Set and reset by software.
Bit 25
0: CAN clock disabled
1: CAN clock enabled
Bit 24 Reserved, always read as 0.
USBEN USB clock enable
Set and reset by software.
Bit 23
0: USB clock disabled
1: USB clock enabled
I2C2EN I2C 2 clock enable
Set and reset by software.
Bit 22
0: I2C 2 clock disabled
1: I2C 2 clock enabled

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Reset and clock control (RCC) UM0306

I2C1EN I2C 1 clock enable

Set and reset by software.
Bit 21
0: I2C 1 clock disabled
1: I2C 1 clock enabled
Bits 20:17 Reserved, always read as 0.
USART3EN USART 3 clock enable
Set and reset by software.
Bit 18
0: USART 3 clock disabled
1: USART 3 clock enabled
USART2EN USART 2 clock enable
Set and reset by software.
Bit 17
0: USART 2 clock disabled
1: USART 2 clock enabled
Bits 16:15 Reserved, always read as 0.
SPI2EN SPI 2 clock enable
Set and reset by software.
Bit 14
0: SPI 2 clock disabled
1: SPI 2 clock enabled
Bits 13:12 Reserved, always read as 0.
WWDGEN Window Watchdog clock enable
Set and reset by software.
Bit 11
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bits 10:3 Reserved, always read as 0.
TIM4EN Timer 4 clock enable
Set and reset by software.
Bit 2
0: Timer 4 clock disabled
1: Timer 4 clock enabled
TIM3EN Timer 3 clock enable
Set and reset by software.
Bit 1
0: Timer 3 clock disabled
1: Timer 3 clock enabled
TIM2EN Timer 2 clock enable
Set and reset by software.
Bit 0
0: Timer 2 clock disabled
1: Timer 2 clock enabled

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UM0306 Reset and clock control (RCC)

4.3.9 Backup domain control register (RCC_BDCR)

Address: 20h
Reset value: 0000 0000h, reset by Backup domain Reset.
Access: 0 <= wait state <= 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
Note: LSEON, LSEBYP, RTCSEL and RTCEN bits of the Backup domain control register
(RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are write
protected and the DBP bit in the Power control register (PWR_CR)has to be set before
these can be modified. Refer to Section 9.1 on page 133 for further information. These bits
are only reset after a Backup domain Reset and VBAT power on. Any internal or external
Reset will not have any effect on these bits.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved BDRST

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC LSE LSE

Reserved RTCSEL[1:0] Reserved LSEON
EN BYP RDY

rw rw rw rw r rw

Bits 31:17 Reserved, always read as 0.

BDRST Backup domain software reset
Set and reset by software.
Bit 16
0: Reset not activated
1: Resets the entire Backup domain
RTCEN RTC clock enable
Set and reset by software.
Bit 15
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, always read as 0.
RTCSEL[1:0] RTC clock source selection
Set by software to select the clock source for the RTC. These bits can be written
only once time. The BDRST bit can be used to reset them.
Bits 9:8 00: No clock
01: LSE oscillator clock used as RTC clock
10: LSI oscillator clock used as RTC clock
11: HSE oscillator clock divided by 128 used as RTC clock
Bits 7:3 Reserved, always read as 0.
LSEBYP External Low Speed oscillator Bypass
Set and reset by software to bypass oscillator in debug mode. This bit can be
Bit 2 written only when the external 32 kHz oscillator is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed

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Reset and clock control (RCC) UM0306

LSERDY External Low Speed oscillator Ready

Set and reset by hardware to indicate when the external 32 kHz oscillator is
stable. This bit needs 6 cycles of external Low Speed oscillator clock to fall down
Bit 1
after LSEON reset.
0: External 32 kHz oscillator not ready
1: External 32 kHz oscillator ready
LSEON External Low Speed oscillator enable
Set and reset by software.
Bit 0
0: External 32 kHz oscillator OFF
1: External 32 kHz oscillator ON

4.3.10 Control/status register (RCC_CSR)

Address: 24h
Reset value: 0C00 0000h, reset by system Reset, except reset flags by power Reset only.
Access: 0 <= wait state <= 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

LPWR WWDG IWDG SFT POR PIN

Res. RMVF Reserved
RSTF RSTF RSTF RSTF RSTF RSTF

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSI
Reserved LSION
RDY

r rw

LPWRRSTF Low-Power reset flag

Reset by software by writing the RMVF bit.
Set by hardware when a Low-power management reset occurs.
Bit 31 0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Section : Low-
power management Reset.
WWDGRSTF Window watchdog reset flag
Reset by software by writing the RMVF bit.
Bit 30 Set by hardware when a window watchdog reset occurs.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
IWDGRSTF Independent Watchdog reset flag
Reset by software by writing the RMVF bit.
Bit 29 Set by hardware when a watchdog reset from VDD domain occurs.
0: No watchdog reset occurred
1: Watchdog reset occurred

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UM0306 Reset and clock control (RCC)

SFTRSTF Software Reset flag

Reset by software by writing the RMVF bit.
Bit 28 Set by hardware when a software reset occurs.
0: No software reset occurred
1: Software reset occurred
PORRSTF POR/PDR reset flag
Reset by software by writing the RMVF bit.
Bit 27 Set by hardware when a POR/PDR reset occurs.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
PINRSTF PIN reset flag
Reset by software by writing the RMVF bit.
Bit 26 Set by hardware when a reset from the NRST pin occurs.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 Reserved, always read as 0.
RMVF Remove reset flag
Set and reset by software to reset the value of the reset flags.
Bit 24
0: Reset of the reset flags not activated
1: Reset the value of the reset flags
Bits 23:2 Reserved, always read as 0.
LSIRDY Internal Low Speed oscillator Ready
Set and reset by hardware to indicate when the internal RC 32 kHz oscillator is
stable. This bit needs 3 cycles of internal RC 32 kHz oscillator to fall down after
Bit 1
LSION reset.
0: Internal RC 32 kHz oscillator not ready
1: Internal RC 32 kHz oscillator ready
LSION Internal Low Speed oscillator enable
Set and reset by software.
Bit 0
0: Internal RC 32 kHz oscillator OFF
1: Internal RC 32 kHz oscillator ON

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 4.4

024h
020h
008h

018h
014h
010h
004h
000h

01Ch
00Ch

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Offset
Table 10.

RCC_CR

RCC_CIR

RCC_CSR
Register

Reset Value
Reset Value

Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value
Reset Value

RCC_CFGR

RCC_BDCR
RCC_AHBENR

RCC_APB1ENR
RCC_APB2ENR
RCC_APB2RSTR

RCC_APB1RSTR

0
LPWRSTF 31

0
WWDGRSTF 30

0
IWDGRSTF

Reserved
Reserved
29

0
0
0
SFTRSTF PWREN PWRRST
Reserved
28
Reserved

1
0
0
Reset and clock control (RCC)

PORRSTF BKPEN BKPRST 27

Reserved

1
0
PINRSTF Reserved Reserved 26

0
0
0
0

Reserved CANEN CANRST PLL RDY 25

RCC register map

0
0
0

RMVF Reserved Reserved PLL ON

MCO [2:0]

24

0
0
0
USBEN USBRST CSSC Reserved

Reserved
23

0
0
0

I2C2EN I2C2RST USBPRE

Reserved
Reserved
Reserved
22

0
0
0

I2C1EN I2C1RST 21
Reserved

0
0

PLLRDYC 20
Reserved Reserved
RCC - register map and reset values

0
0
0

HSERDYC CSSON 19

0
0
0
0
0

USART3EN USART3RST HSIRDYC HSEBYP

PLLMUL[3:0]

18

0
0
0
0
0

USART2EN USART2RST LSERDYC PLLXTPRE HSERDY

Reserved
17

0
0
0
0

BDRST LSIRDYC PLLSRC HSEON 16

Reserved Reserved

0
0
0

RTCEN 15
[1:0]
PRE
ADC

0
0
0
0
0
0

SPI2EN USART1EN SPI2RST USART1RST Reserved 14

0
0

Reserved Reserved 13
Reserved Reserved

0
0
0
0
0

SPI1EN SPI1RST PLLRDYIE 12

[2:0]

Reserved
PPRE2

0
0
0
0
0
0
0

WWDGEN TIM1EN WWDGRST TIM1RST HSERDYIE

Reserved
11
HSICAL[7:0]

0
0
0
0
0

ADC2EN ADC2RST HSIRDYIE

Refer to Table 1 on page 27 for the register boundary addresses.

10

0
0
0
0
0
0

ADC1EN ADC1RST LSERDYIE 9

[2:0]
PPRE1

SEL
[1:0]
RTC
LSIRDYIE

0
0
0
0

Reserved Reserved
8
0
0
1

CSSF 7

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0
0
0
0

IOPEEN IOPERST 6
Reserved

Reserved
Reserved

0
0
0
0

IOPDEN IOPDRST 5
HPRE[3:0]

0
1
0
0
0
0

IOPCEN FLITFEN IOPCRST PLLRDYF

Reserved
4
HSITRIM[4:0]

0
0
0
0
0

IOPBEN Reserved IOPBRST HSERDYF 3

[1:0]

0
0
0

0
1
0
0
0
SWS

LSEBYP TMI3EN IOPAEN SRAMEN TMI3RST IOPARST HSIRDYF Reserved 2

0
0
0
0
0
1

LSIRDY LSERDY TM2EN Reserved Reserved TM2RST Reserved LSERDYF HDIRDY 1

SW
[1:0]

LSIRDYF

0
0
0
0
0
0
0
0
1

LSION LSEON TMI1EN AFIOEN DMAEN TMI1RST AFIORST HDION

UM0306

0
UM0306 General purpose and alternate function I/O (GPIO and AFIO)

5 General purpose and alternate function I/O (GPIO and

AFIO)

5.1 GPIO functional description

Each of the General Purpose I/O Ports has two 32-bit configuration registers (GPIOx_CRL,
GPIOx_CRH, two 32-bit data registers (GPIOx_IDR, GPIOx_ODR), a 32-bit set/reset
register (GPIOx_BSRR), a 16-bit reset register (GPIOx_BRR) and a 32-bit locking register
(GPIOx_LCKR).
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
in several modes:
– Input floating
– Input Pull-up
– Input-Pull-down
– Analog Input
– Output Open-Drain
– Output Push-Pull
– Alternate Function Push-Pull
– Alternate Function Open-Drain
Each I/O port bit is freely programmable, however the I/O port registers have to be accessed
as 32-bit words (half-word or byte accesses are not allowed). The purpose of the
GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of
the GPIO registers. This way, there is no risk that an IRQ occurs between the read and the
modify access.
Figure 9 shows the basic structure of an I/O Port bit.

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Figure 9. Basic structure of an I/O port bit

Analog Input
TO ON-CHIP VDD_IO
PERIPHERAL Alternate Function Input

INPUT DATA REGISTER

ON/OFF PULL
ON/OFF
UP
READ VDD_IO
BIT SET/RESET REGISTERS

TTL SCHMITT ON/OFF PULL

PROTECTION
TRIGGER DOWN
DIODE
VSS
OUTPUT DATA REGISTER

INPUT DRIVER I/O PIN

WRITE

OUTPUT DRIVER VDD_IO

PROTECTION
DIODE
P-MOS
OUTPUT VSS
CONTROL
N-MOS
READ/WRITE
VSS
PUSH-PULL,
FROM ON-CHIP OPEN-DRAIN OR
PERIPHERAL Alternate Function Output DISABLED

Table 11. Port bit configuration table

PxODR
Configuration mode CNF1 CNF0 MODE1 MODE0
Register

General purpose Push-Pull 0 0 or 1

0 01
output Open-Drain 1 0 or 1
10
Push-Pull 0 11 don’t care
Alternate Function
1 see Table 12
output Open-Drain 1 don’t care
Analog input 0 don’t care
0
Input Floating 1 don’t care
Input 00
Input Pull-Down 0
1 0
Input Pull-Up 1

Table 12. Output Mode bits

MODE[1:0] Meaning

00 Reserved
01 Max. output speed 10 MHz
10 Max. output speed 2 MHz
11 Max. output speed 50 MHz

5.1.1 General purpose I/O (GPIO)

During and just after reset, the alternate functions are not active and the I/O ports are
configured in Input Floating mode (CNFx[1:0]=01b, MODE[1:0]=00b).

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UM0306 General purpose and alternate function I/O (GPIO and AFIO)

The JTAG pins are in input PU/PD after reset:

PA15: JTDI in PU
PA14: JTCK in PD
PA13: JTMS in PU
PB4: JNTRST in PU
When configured as output, the value written to the Output Data register (GPIOx_ODR) is
output on the I/O pin. It is possible to use the output driver in Push-Pull mode or Open-Drain
mode (only the N-MOS is activated when outputting 0).
The Input Data register (GPIOx_IDR) captures the data present on the I/O pin at every
APB2 clock cycle.
All GPIO pins have a internal weak pull-up and weak pull-down which can be activated or
not when configured as input.

5.1.2 Atomic bit set or bit reset

There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify only one or several bits in a single atomic APB2 write
access.
This is achieved by programming to ‘1’ the Bit Set/Reset Register (GPIOx_BSRR, or for
reset only GPIOx_BRR) to select the bits you want to modify. The unselected bits will not be
modified.

5.1.3 External interrupt/wake-up lines

All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. For more information on external interrupts, refer to:
● Section 6.2: External interrupt/event controller (EXTI) on page 101 and
● Section 6.2.3: Wake-up event management on page 102.

5.1.4 Alternate functions (AF)

It is necessary to program the Port Bit Configuration Register before using a default
alternate function.
● For alternate function inputs, the port can be configured either:
– in Input mode (floating, pull-up or pull-down)
– in Alternate Function Output mode. In this case the input driver is configured in
input floating mode
● For Alternate Function Outputs, the port must be configured in Alternate Function
Output mode (Push-Pull or Open-Drain).
● For bidirectional Alternate Functions, the port bit must be configured in Alternate
Function Output mode (Push-Pull or Open-Drain). In this case the input driver is
configured in input floating mode
If you configure a port bit as Alternate Function Output, this disconnects the output register
and connects the pin to the output signal of an on-chip peripheral.
If software configures a GPIO pin as Alternate Function Output, but peripheral is not
activated, its output is not specified.

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General purpose and alternate function I/O (GPIO and AFIO) UM0306

5.1.5 Software remapping of I/O alternate functions

To optimize the number of peripheral I/O functions for different device packages, it is
possible to remap some alternate functions to some other pins. This is achieved by
software, by programming the corresponding registers (refer to AFIO register description on
page 91. In that case, the alternate functions are no longer mapped to their original
assignations.

5.1.6 GPIO locking mechanism

The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
has been applied on a port bit, it is no longer possible to modify the value of the port bit until
the next reset.

5.1.7 Input configuration

When the I/O Port is programmed as Input:
● The Output Buffer is disabled
● The Schmitt Trigger Input is activated
● The weak pull-up and pull-down resistors are activated or not depending on input
configuration (pull-up, pull-down or floating):
● The data present on the I/O pin is sampled into the Input Data Register every APB2
clock cycle
● A read access to the Input Data Register obtains the I/O State.
The Figure 10 on page 76 shows the Input Configuration of the I/O Port bit.

Figure 10. Input floating/pull up/pull down configurations

VDD_IO
INPUT DATA REGISTER

ON/OFF PULL
ON
READ UP
VDD_IO
BIT SET/RESET REGISTERS

TTL SCHMITT ON/OFF PULL

TRIGGER PROTECTION
DOWN
OUTPUT DATA REGISTER

DIODE
WRITE VSS
INPUT DRIVER I/O PIN

OUTPUT DRIVER
PROTECTION
DIODE

VSS
READ/WRITE

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UM0306 General purpose and alternate function I/O (GPIO and AFIO)

5.1.8 Output configuration

When the I/O Port is programmed as Output:
● The Output Buffer is enabled:
– Open Drain Mode: A “0” in the Output register activates the N-MOS while a “1” in
the Output register leaves the port in Hi-Z. (the P-MOS is never activated)
– Push-Pull Mode: A “0” in the Output register activates the N-MOS while a “1” in the
Output register activates the P-MOS.
● The Schmitt Trigger Input is activated.
● The weak pull-up and pull-down resistors are disabled.
● The data present on the I/O pin is sampled into the Input Data Register every APB2
clock cycle
● A read access to the Input Data Register gets the I/O state in open drain mode
● A read access to the Output Data register gets the last written value in Push-Pull mode
The Figure 11 on page 77 shows the Output configuration of the I/O Port bit.

Figure 11. Output configuration

INPUT DATA REGISTER

ON
READ
VDD_IO
BIT SET/RESET REGISTERS

TTL SCHMITT
TRIGGER PROTECTION
DIODE
OUTPUT DATA REGISTER

WRITE
INPUT DRIVER I/O PIN

OUTPUT DRIVER VDD_IO

PROTECTION
DIODE
P-MOS
OUTPUT VSS
READ/WRITE CONTROL
N-MOS
PUSH-PULL OR
VSS OPEN-DRAIN

5.1.9 Alternate function configuration

When the I/O Port is programmed as Alternate Function:
● The Output Buffer is turned on in Open Drain or Push-Pull configuration
● The Output Buffer is driven by the signal coming from the peripheral (alternate function
out)
● The Schmitt Trigger Input is activated
● The weak pull-up and pull-down resistors are disabled.
● The data present on the I/O pin is sampled into the Input Data Register every APB2
clock cycle
● A read access to the Input Data Register gets the I/O state in open drain mode
● A read access to the Output Data register gets the last written value in Push-Pull mode
The Figure 12 on page 78 shows the Alternate Function Configuration of the I/O Port bit.
Also, refer to Section 5.4: AFIO register description on page 91 for further information.

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A set of Alternate Function I/O registers allow you to remap some alternate functions to
different pins. Refer to

Figure 12. Alternate function configuration

TO ON-CHIP Alternate Function Input

PERIPHERAL

INPUT DATA REGISTER

ON

READ VDD_IO
BIT SET/RESET REGISTERS

TTL SCHMITT
PROTECTION
TRIGGER
DIODE
OUTPUT DATA REGISTER

INPUT DRIVER I/O PIN

WRITE

OUTPUT DRIVER VDD_IO

PROTECTION
DIODE
P-MOS
OUTPUT VSS
CONTROL
N-MOS
READ/WRITE
VSS PUSH-PULL OR
OPEN-DRAIN
FROM ON-CHIP
PERIPHERAL Alternate Function Output

5.1.10 Analog input configuration

When the I/O Port is programmed as Analog Input Configuration:
● The Output Buffer is disabled.
● The Schmitt Trigger Input is de-activated providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt Trigger is forced to a constant value (0).
● The weak pull-up and pull-down resistors are disabled.
● Read access to the Input Data Register gets the value “0”.
The Figure 13 on page 79 shows the High impedance-Analog Input Configuration of the I/O
Port bit.

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Figure 13. High impedance-analog input configuration

Analog Input
TO ON-CHIP
PERIPHERAL

INPUT DATA REGISTER

READ OFF
BIT SET/RESET REGISTERS 0 VDD_IO

TTL SCHMITT
PROTECTION
OUTPUT DATA REGISTER TRIGGER
DIODE
WRITE
INPUT DRIVER I/O PIN

PROTECTION
DIODE

VSS
READ/WRITE

FROM ON-CHIP
PERIPHERAL

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5.2 GPIO register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

5.2.1 Port configuration register low (GPIOx_CRL) (x=A..E)

Address Offset: 00h
Reset value: 4444 4444h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CNF7[1:0] MODE7[1:0] CNF6[1:0] MODE6[1:0] CNF5[1:0] MODE5[1:0] CNF4[1:0] MODE4[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNF3[1:0] MODE3[1:0] CNF2[1:0] MODE2[1:0] CNF1[1:0] MODE1[1:0] CNF0[1:0] MODE0[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CNFx[1:0]: Port x configuration bits (x= 0 .. 7)

These bits are written by software to configure the corresponding I/O port.
Refer to Table 11: Port bit configuration table on page 74.
In input mode (MODE[1:0]=00):
00: Analog input mode
Bits 31:30, 27:26,
01: Floating input (reset state)
23:22, 19:18,
10: Input with pull-up / pull-down
15:14, 11:10, 7:6,
3:2 11: Reserved
In output mode (MODE[1:0] > 00):
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
MODEx[1:0]: Port x.x mode bits (x= 0 .. 7)
These bits are written by software to configure the corresponding I/O port.
Bits 29:28, 25:24, Refer to Table 11: Port bit configuration table on page 74.
21:20, 17:16, 00: Input mode (reset state)
13:12, 9:8, 5:4, 1:0 01: Output mode, max speed 10 MHz.
10: Output mode, max speed 2 MHz.
11: Output mode, max speed 50 MHz.

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5.2.2 Port configuration register high (GPIOx_CRH) (x=A..E)

Address Offset: 04h
Reset value: 4444 4444h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CNF15[1:0] MODE15[1:0] CNF14[1:0] MODE14[1:0] CNF13[1:0] MODE13[1:0] CNF12[1:0] MODE12[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNF11[1:0] MODE11[1:0] CNF10[1:0] MODE10[1:0] CNF9[1:0] MODE9[1:0] CNF8[1:0] MODE8[1:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CNFx[1:0]: Port x configuration bits (x= 8 .. 15)

These bits are written by software to configure the corresponding I/O port.
Refer to Table 11: Port bit configuration table on page 74.
In input mode (MODE[1:0]=00):
00: Analog input mode
Bits 31:30, 27:26,
01: Floating input (reset state)
23:22, 19:18,
10: Input with pull-up / pull-down
15:14, 11:10, 7:6,
3:2 11: Reserved
In output mode (MODE[1:0] > 00):
00: General purpose output push-pull
01: General purpose output Open-drain
10: Alternate function output Push-pull
11: Alternate function output Open-drain
MODEx[1:0]: Port x.x mode bits (x= 8 .. 15)
These bits are written by software to configure the corresponding I/O port.
Bits 29:28, 25:24, Refer to Table 11: Port bit configuration table on page 74.
21:20, 17:16, 00: Input mode (reset state)
13:12, 9:8, 5:4, 1:0 01: Output mode, max speed 2 MHz.
10: Output mode, max speed 10 MHz.
11: Output mode, max speed 50 MHz.

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5.2.3 Port input data register (GPIOx_IDR) (x=A..E)

Address Offset: 08h
Reset value: 00000000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

IDR15 IDR14 IDR13 IDR12 IDR11 IDR10 IDR9 IDR8 IDR7 IDR6 IDR5 IDR4 IDR3 IDR2 IDR1 IDR0

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, always read as 0.

IDRx[15:0]: Port input data (x= 0 .. 15)
Bits 31:0 These bits are read only and can be accessed in Word mode only. They
contain the input value of the corresponding I/O port.

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5.2.4 Port output data register (GPIOx_ODR) (x=A..E)

Address Offset: 0Ch
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ODR15 ODR14 ODR13 ODR12 ODR11 ODR10 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, always read as 0.

ODRx[15:0]: Port output data (x= 0 .. 15)
These bits can be read and written by software and can be accessed in Word
Bits 15:0 mode only.
Note: For atomic bit set/reset, the ODR bits can be individually set and reset by
writing to the GPIOx_BSRR register (x = A .. E).

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5.2.5 Port bit set/reset register (GPIOx_BSRR) (x=A..E)

Address Offset: 10h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0

w w w w w w w w w w w w w w w w

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0

w w w w w w w w w w w w w w w w

BRx: Reset bit x (x= 0 .. 15)

These bits are write-only and can be accessed in Word mode only.
Bits 31:16 0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
BSx: Set bit x (x= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
Bits 15:0
0: No action on the corresponding ODRx bit
1: Set the corresponding ODRx bit

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5.2.6 Port bit reset register (GPIOx_BRR) (x=A..E)

Address Offset: 14h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0

w w w w w w w w w w w w w w w w

Bits 31:16 Reserved

BRx: Reset bit x (x= 0 .. 15)
These bits are write-only and can be accessed in Word mode only.
Bits 15:0 0: No action on the corresponding ODRx bit
1: Reset the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.

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5.2.7 Port configuration lock register (GPIOx_LCKR) (x=A..E)

This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit it is no longer possible to modify the value of
the port bit until the next reset.
Each lock bit freezes the corresponding 4 bits of the control register (CRL, CRH).
Address Offset: 18h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved LCKK

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:17 Reserved

LCKK[15:0]: Lock key
This bit can be read anytime. It can only be modified using the Lock Key
Writing Sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. GPIOx_LCKR register is locked until an
MCU reset occurs.

LOCK Key Writing Sequence:

Bit 16 Write 1
Write 0
Write 1
Read 0
Read 1 (this read is optional but confirms that the lock is active)
Notes:
During the LOCK Key Writing sequence, the value of LCK[15:0] must not
change.
Any error in the lock sequence will abort the lock.
LCKx: Lock bit x (x= 0 .. 15)
These bits are read write but can only be written when the LCKK bit is 0.
Bits 15:0
0: Port configuration not locked
1: Port configuration locked.

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5.3 Alternate function I/O and debug configuration (AFIO)

To optimize the number of peripherals available for the 64-pin or the 100-pin package, it is
possible to remap some alternate functions to some other pins. This is achieved by
software, by programming the AF remap and debug I/O configuration register
(AFIO_MAPR) on page 92. In this case, the alternate functions are no longer mapped to
their original assignations.

5.3.1 Using OSC_IN/OSC_OUT pins as GPIO ports PD0/PD1

The external oscillator pins OSC_IN/OSC_OUT can be used as general purpose I/O
PD0/PD1 by programming the PD01_REMAP bit in the AF remap and debug I/O
configuration register (AFIO_MAPR).

5.3.2 BXCAN alternate function remapping

The BXCAN signal can be mapped on Port A, Port B or Port E as shown in Table 13.

Table 13. BXCAN alternate function remapping

CAN_REMAP[1:0] = CAN_REMAP[1:0] = CAN_REMAP[1:0] =
Alternate Function
“00” “10” (1) “11” (2)

CANRX PA11 PB8 PD0

CANTX PA12 PB9 PD1
1. Remap not available on 36-pin package
2. Remap available only on 100-pin package

5.3.3 JTAG/SWD alternate function remapping

The debug interface signals are mapped on the GPIO ports as shown in Table 14.

Table 14. Debug interface signals

Alternate function GPIO port

JTMS / SWDIO PA13

JTCK / SWCLK PA14
JTDI PA15
JTDO / TRACESWO PB3
JNTRST PB4
TRACECK PE2
TRACED0 PE3
TRACED1 PE4
TRACED2 PE5
TRACED3 PE6

To optimize the number of free GPIOs during debugging, this mapping can be configured in
different ways by programming the SWJ_CFG[1:0] bits in the AF remap and debug I/O
configuration register (AFIO_MAPR). Refer to Table 15

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Table 15. Debug port mapping

SWJ I/O pin assigned
SWJ
PB.3 /
_CFG Available Debug Ports PA.13 / PA.14 /
PA.15 / JTDO/ PB.4/
[2:0] JTMS/ JTCK/S
JTDI TRACE JNTRST
SWDIO WCLK
SWO

Full SWJ (JTAG-DP + SW-DP)

000 X X X X X
(Reset state)
Full SWJ (JTAG-DP + SW-DP)
001 X X X x free
but without JNTRST
JTAG-DP Disabled and
010 X X free free(1) free
SW-DP Enabled
JTAG-DP Disabled and
100 free free free free free
SW-DP Disabled
Other Forbidden
1. Released only if not using asynchronous trace.

5.3.4 Timer alternate function remapping

Timer 4 channels 1 to 4 can be remapped from Port B to Port D.
Other timer remapping possibilities are listed in Table 17 to Table 19.
Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

Table 16. Timer 4 alternate function remapping

Alternate Function TIM4_REMAP = 0 TIM4_REMAP = 1

TIM4_CH1 PB6 PD12

TIM4_CH2 PB7 PD13
(1)
TIM4_CH3 PB8 PD14
TIM4_CH4 PB9 (1) PD15

Table 17. Timer 3 alternate function remapping

TIM3_REMAP[1:0] = TIM3_REMAP[1:0] = TIM3_REMAP[1:0] =
Alternate Function
“00” (no remap) “10” (partial remap) “11” (full remap) (1)

TIM3_CH1 PA6 PB4 PC6

TIM3_CH2 PA7 PB5 PC7
TIM3_CH3 PB0 PC8
TIM3_CH4 PB1 PC9
1. Remap available only for 64 and 100 pin packages.

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Table 18. Timer 2 alternate function remapping

TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1: TIM2_REMAP[1:
Alternate Function 0] = “00” (no 0] = “01” (partial 0] = “10” (partial 0] = “11” (full
remap) remap) remap) (1) remap) (1)

TIM2_CH1/ETR PA0 PA15 PA0 PA15

TIM2_CH2 PA1 PB3 PA1 PB3
TIM2_CH3 PA2 PB10
TIM2_CH4 PA3 PB11
1. Remap available only for 64 and 100 pin packages.

Table 19. Timer 1 alternate function remapping

Alternate Functions TIM1_REMAP[1:0] = TIM1_REMAP[1:0] = TIM1_REMAP[1:0] =
Mapping “00” (no remap) “01” (partial remap) “11” (full remap) (1)

TIM1_ETR PA12 PE7

TIM1_CH1 PA8 PE9
TIM1_CH2 PA9 PE11
TIM1_CH3 PA10 PE13
TIM1_CH4 PA11 PE14
(2)
TIM1_BKIN PB12 PA6 PE15
TIM1_CH1N PB13 (2) PA7 PE8
(2)
TIM1_CH2N PB14 PB0 PE10
TIM1_CH3N PB15 (2) PB1 PE12
1. Remap available only for 100-pin package.
2. Remap not available on 36-pin package.

5.3.5 USART Alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

Table 20. USART3 remapping

USART3_REMAP[1:0]
USART3_REMAP[1:0] USART3_REMAP[1:0]
Alternate Function = “01” (partial remap)
= “00” (no remap) (1) = “11” (full remap) (2)

USART3_TX PB10 PC10 PD8

USART3_RX PB11 PC11 PD9
USART3_CK PB12 PC12 PD10
USART3_CTS PB13 PD11
USART3_RTS PB14 PD12
1. Remap available only for 64 and 100 pin packages
2. Remap available only for 100 pin package.

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Table 21. USART2 remapping

Alternate Functions USART2_REMAP = 0 USART2_REMAP = 1(1)

USART2_CTS PA0 PD3

USART2_RTS PA1 PD4
USART2_TX PA2 PD5
USART2_RX PA3 PD6
USART2_CK PA4 PD7
1. Remap available only for 100 pin package.

Table 22. USART1 remapping

Alternate Function USART1_REMAP = 0 USART1_REMAP = 1

USART1_TX PA9 PB6

USART1_RX PA10 PB7

5.3.6 I2C 1 alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

Table 23. I2C1 Remapping

Alternate Function I2C1_REMAP = 0 I2C1_REMAP = 1 (1)

I2C1_SCL PB6 PB8

I2C1_SDA PB7 PB9
1. Remap not available on 128K 36 pin.

5.3.7 SPI 1 alternate function remapping

Refer to AF remap and debug I/O configuration register (AFIO_MAPR)

Table 24. SPI1 Remapping

Alternate Function SPI1_REMAP = 0 SPI1_REMAP = 1

SPI1_NSS PA4 PA15

SPI1_SCK PA5 PB3
SPI1_MISO PA6 PB4
SPI1_MOSI PA7 PB5

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5.4 AFIO register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

Event control register (AFIO_EVCR)

Address Offset: 00h
Reset value: 0x0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved EVOE PORT[2:0] PIN[3:0]

rw rw rw rw rw rw rw rw

Bits 31:18
EVOE Event Output Enable
Bit 7 Set and cleared by software. When set the EVENTOUT Cortex output is
connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits.
PORT[2:0]: Port selection
Set and cleared by software. Select the port used to output the Cortex
EVENTOUT signal.
000: PA selected
Bits 6:4
001: PB selected
010: PC selected
011: PD selected
100: PE selected
PIN[3:0] Pin selection (x = A .. E)
Set and cleared by software. Select the pin used to output the Cortex
EVENTOUT signal.
0000: Px0 selected
Bits 3:0 0001: Px1 selected
0010: Px2 selected
0011: Px3 selected
...
1111: Px15 selected

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5.4.1 AF remap and debug I/O configuration register (AFIO_MAPR)

Address Offset: 04h
Reset value: 0x0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWJ_
Reserved Reserved
CFG[2:0]
rw rw rw
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
USART USART
PD01_ CAN_REMAP TIM4_ TIM3_REMAP TIM2_REMAP TIM1_REMAP USART3_ I2C1_ SPI1_
2_ 1_
REMAP [1:0] REMAP [1:0] [1:0] [1:0] REMAP[1:0] REMAP REMAP
REMAP REMAP
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:26 Reserved

SWJ_CFG[2:0] Serial Wire JTAG configuration
These bits are set and cleared by software. They are used to configure the
SWJ and trace alternate function I/Os. The SWJ (Serial Wire JTAG) supports
JTAG or SWD access to the Cortex debug port. The default state after reset is
SWJ ON without trace. This allows JTAG or SW mode to be enabled by
Bits 25:24 sending a specific sequence on the JTMS / JTCK pin.
000: Full SWJ (JTAG-DP + SW-DP): Reset State
001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST
010: JTAG-DP Disabled and SW-DP Enabled
100: JTAG-DP Disabled and SW-DP Disabled
Other combinations: Forbidden
Bits 23:15 Reserved
PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT
This bit is set and cleared by software. It controls the mapping of PD0 and
PD1 GPIO functionality. When the main oscillator is not used (application
running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
Bit 15
OSC_OUT. This is available only on 36, 48 and 64 pin packages (PD0 and
PD1 are available on TQFP100 package, no need for remapping).
0: No remapping of PD0 and PD1
1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT,
CAN_REMAP[1:0] CAN Alternate function remapping
These bits are set and cleared by software. They control the mapping of
Alternate Functions CANRX and CANTX.
00: CANRX mapped to PA11, CANTX mapped to PA12
Bits 14:13 01: Not used
10: CANRX mapped to PB8, CANTX mapped to PB9 (not available on 36-pin
package)
11: CANRX mapped to PD0, CANTX mapped to PD1 (available only on 100-
pin package)
TIM4_REMAP TIM4 remapping
This bit is set and cleared by software. It controls the mapping of TIM4
channels 1 to 4 on 100-pin packages only.
0: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8,
Bit 12
TIM4_CH4/PB9)
1: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14,
TIM4_CH4/PD15)
Note: TIM4_ETR on PE0 is not re-mapped.

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TIM3_REMAP[1:0] TIM3 remapping

These bits are set and cleared by software. They control the mapping of TIM3
channels 1 to 4 on the GPIO ports.
00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)
Bits 11:10
01: Not used
10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)
11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)
Note: TIM3_ETR on PE0 is not re-mapped.
TIM2_REMAP[1:0] TIM2 remapping
These bits are set and cleared by software. They control the mapping of TIM2
channels 1 to 4 and external trigger (ETR) on the GPIO ports.
Bits 9:8 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)
01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)
10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)
11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
TIM1_REMAP[1:0] TIM1 remapping
These bits are set and cleared by software. They control the mapping of TIM2
channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) on
the GPIO ports.
00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11,
Bits 7:6 BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11,
BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)
10: not used
11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14,
BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)
USART3_REMAP[1:0] USART3 remapping
These bits are set and cleared by software. They control the mapping of
USART3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports.
Bits 5:4 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
10: not used
11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)
USART2_REMAP USART2 remapping
This bit is set and cleared by software. It controls the mapping of USART2
Bit 3 CTS, RTS,CK,TX and RX alternate functions on the GPIO ports.
0: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA2, CK/PA3)
1: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
USART1_REMAP USART1 remapping
This bit is set and cleared by software. It controls the mapping of USART1 TX
Bit 2 and RX alternate functions on the GPIO ports.
0: No remap (TX/PA9, RX/PA10)
1: Remap (TX/PB6, RX/PB7)

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I2C1_REMAP I2C1 remapping

This bit is set and cleared by software. It controls the mapping of I2C1 SCL
Bit 1 and SDA alternate functions on the GPIO ports.
0: No remap (SCL/PB6, SDA/PB7)
1: Remap (SCL/PB8, SDA/PB9)
SPI1_REMAP SPI1 remapping
This bit is set and cleared by software. It controls the mapping of SPI1 NSS,
Bit 0 SCK, MISO, MOSI alternate functions on the GPIO ports.
0: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7)
1: Remap (NSS/PA15, SCK/PB3, MISO/PB3, MOSI/PB5)

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5.4.2 External interrupt configuration register 1 (AFIO_EXTICR1)

Address offset: 08h
Reset value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

EXTIx[3:0]: EXTI x configuration (x= 0 to 3)
These bits are written by software to select the source input for EXTIx external
interrupt. Refer to Section 6.2.5: External interrupt/event line mapping on
page 103
Bits 15:0 0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

5.4.3 External interrupt configuration register 2 (AFIO_EXTICR2)

Address offset: 0Ch
Reset value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

EXTIx[3:0]: EXTI x configuration (x= 4 to 7)
These bits are written by software to select the source input for EXTIx external
interrupt.
0000: PA[x] pin
Bits 15:0
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

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5.4.4 External interrupt configuration register 3 (AFIO_EXTICR3)

Address offset: 10h
Reset value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

EXTIx[3:0]: EXTI x configuration (x= 8 to 11)
These bits are written by software to select the source input for EXTIx external
interrupt.
0000: PA[x] pin
Bits 15:0
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

5.4.5 External interrupt configuration register 4 (AFIO_EXTICR4)

Address offset: 14h
Reset value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved

EXTIx[3:0]: EXTI x configuration (x= 12 to 15)
These bits are written by software to select the source input for EXTIx external
interrupt.
0000: PA[x] pin
Bits 15:0
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin

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5.5 GPIO and AFIO register maps

Refer to Table 1 on page 27 for the register boundary addresses.

5.5.1 GPIO register map

Table 25. GPIO register map and reset values
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE
GPIOx_CRL 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0
00h
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
Reset Value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE CNF MODE
GPIOx_CRH 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8
04h
[1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0]
Reset Value 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0

GPIOx_IDR IDR[15:0]l
08h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOx_ODR ODR[15:0]
0Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOx_BSRR BR[15:0] BSR[15:0]

10h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GPIOx_BRR BR[15:0]
14h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LCKK

GPIOx_LCKR LCK[15:0]
18h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

5.5.2 AFIO register map

Table 26. AFIO register map and reset values
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

Offset Register
9
8
7
6
5
4
3
2
1
0
EVOE

AFIO_EVCR PORT[2:0] PIN[2:0]

00h Reserved
Reset Value 0 0 0 0 0 0 0
USART3_REMAP[1]
USART3_REMAP[0]
TIM3_REMPAP[1]
TIM3_REMPAP[0]
TIM2_REMPAP[1]
TIM2_REMPAP[0]
TIM1_REMPAP[1]
TIM1_REMPAP[0]

USART2_REMAP
USART1_REMAP
CAN_REMAP[1]
CAN_REMAP[0]
TIM4_REMPAP
PD01_REMAP

SPI1_REMAP
I2C1_REMAP
SWJ_CFG[2]
SWJ_CFG[1]
SWJ_CFG[0]

AFIO_MAPR
04h Reserved Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFIO_EXTICR1 EXTI3[3:0] EXTI2[3:0] EXTI1[3:0] EXTI0[3:0]

08h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFIO_EXTICR2 EXTI7[3:0] EXTI6[3:0] EXTI5[3:0] EXTI4[3:0]

0Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFIO_EXTICR3 EXTI11[3:0] EXTI10[3:0] EXTI9[3:0] EXTI8[3:0]

10h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

AFIO_EXTICR4 EXTI15[3:0] EXTI14[3:0] EXTI13[3:0] EXTI12[3:0]

14h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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6 Interrupts and events

6.1 Nested vectored interrupt controller (NVIC)

Features
● 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3)
● 16 programmable priority levels
● Low-latency exception and interrupt handling
● Power management control
● Implementation of System Control Registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming see Chap 5 Exceptions & Chap 8 Nested Vectored
Interrupt Controller of the ARM Cortex-M3TM Technical Reference Manual.

6.1.1 SysTick calibration value register

The SysTick calibration value is fixed to 9000 which allows the generation of a time base of
1ms with the SysTick clock set to 9 MHz (max HCLK/8).

6.1.2 Interrupt and exception vectors

Table 27. Vector table

Position

Priority

Type of
Acronym Description Address
priority

- - - Reserved 0x0000_0000
-3 fixed Reset Reset 0x0000_0004
Non maskable interrupt. The RCC
-2 fixed NMI Clock Security System (CSS) is linked 0x0000_0008
to the NMI vector.
-1 fixed HardFault All class of fault 0x0000_000C
0 settable MemManage Memory management 0x0000_0010
1 settable BusFault Pre-fetch fault, memory access fault 0x0000_0014
2 settable UsageFault Undefined instruction or illegal state 0x0000_0018
0x0000_001C -
- - - Reserved
0x0000_002B
System service call via SWI
3 settable SVCall 0x0000_002C
instruction
4 settable Debug Monitor Debug Monitor 0x0000_0030
- - - Reserved 0x0000_0034
5 settable PendSV Pendable request for system service 0x0000_0038

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Table 27. Vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

6 settable SysTick System tick timer 0x0000_003C

0 7 settable WWDG Window Watchdog interrupt 0x0000_0040
PVD through EXTI Line detection
1 8 settable PVD 0x0000_0044
interrupt
2 9 settable TAMPER Tamper interrupt 0x0000_0048
3 10 settable RTC RTC global interrupt 0x0000_004C
4 11 settable FLASH Flash global interrupt 0x0000_0050
5 12 settable RCC RCC global interrupt 0x0000_0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000_0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000_005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000_0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000_0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000_0068
11 18 settable DMAChannel1 DMA Channel1 global interrupt 0x0000_006C
12 19 settable DMAChannel2 DMA Channel2 global interrupt 0x0000_0070
13 20 settable DMAChannel3 DMA Channel3 global interrupt 0x0000_0074
14 21 settable DMAChannel4 DMA Channel4 global interrupt 0x0000_0078
15 22 settable DMAChannel5 DMA Channel5 global interrupt 0x0000_007C
16 23 settable DMAChannel6 DMA Channel6 global interrupt 0x0000_0080
17 24 settable DMAChannel7 DMA Channel7 global interrupt 0x0000_0084
18 25 settable ADC ADC global interrupt 0x0000_0088
USB_HP_CAN_ USB High Priority or CAN TX
19 26 settable 0x0000_008C
TX interrupts
USB_LP_CAN_ USB Low Priority or CAN RX0
20 27 settable 0x0000_0090
RX0 interrupts
21 28 settable CAN_RX1 CAN RX1 interrupt 0x0000_0094
22 29 settable CAN_SCE CAN SCE interrupt 0x0000_0098
23 30 settable EXTI9_5 EXTI Line[9:5] interrupts 0x0000_009C
24 31 settable TIM1_BRK TIM1 Break interrupt 0x0000_00A0
25 32 settable TIM1_UP TIM1 Update interrupt 0x0000_00A4
TIM1 Trigger and Commutation
26 33 settable TIM1_TRG_COM 0x0000_00A8
interrupts
27 34 settable TIM1_CC TIM1 Capture Compare interrupt 0x0000_00AC
28 35 settable TIM2 TIM2 global interrupt 0x0000_00B0
29 36 settable TIM3 TIM3 global interrupt 0x0000_00B4

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Table 27. Vector table (continued)

Position

Priority
Type of
Acronym Description Address
priority

30 37 settable TIM4 TIM4 global interrupt 0x0000_00B8

31 38 settable I2C1_EV I2 C1 event interrupt 0x0000_00BC
2
32 39 settable I2C1_ER I C1 error interrupt 0x0000_00C0
2
33 40 settable I2C2_EV I C2 event interrupt 0x0000_00C4
34 41 settable I2C2_ER I2C2 error interrupt 0x0000_00C8
35 42 settable SPI1 SPI1 global interrupt 0x0000_00CC
36 43 settable SPI2 SPI2 global interrupt 0x0000_00D0
37 44 settable USART1 USART1 global interrupt 0x0000_00D4
38 45 settable USART2 USART2 global interrupt 0x0000_00D8
39 46 settable USART3 USART3 global interrupt 0x0000_00DC
40 47 settable EXTI15_10 EXTI Line[15:10] interrupts 0x0000_00E0
41 48 settable RTCAlarm RTC alarm through EXTI line interrupt 0x0000_00E4
USB wakeup from suspend through
42 49 settable USBWakeUp 0x0000_00E8
EXTI line interrupt

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UM0306 Interrupts and events

6.2 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of up to 19 edge detectors for generating
event/interrupt requests. Each input line can be independently configured to select the type
(pulse or pending) and the corresponding trigger event (rising or falling or both). Each line
can also masked independently. A pending register maintains the status line of the interrupt
requests

6.2.1 Main features

The EXTI controller main features are the following:
● Independent trigger and mask on each interrupt/event line
● Dedicated status bit for each interrupt line
● Generation of up to 19 software event/interrupt requests
● Detection of external signal with pulse width lower than APB2 clock period. Refer to the
electrical characteristics section of the datasheet for details on this parameter.

6.2.2 Block diagram

The block diagram is shown in Figure 14.

Figure 14. External interrupt/event controller block diagram

AMBA APB BUS

PCLK2 PERIPHERAL INTERFACE

19 19 19 19 19

INTERRUPT PENDING SOFTWARE RISING FALLING

MASK REQUEST INTERRUPT TRIGGER TRIGGER
REGISTER REGISTER EVENT SELECTION SELECTION
REGISTER REGISTER REGISTER

To NVIC Interrupt 19 19 19 19 19
Controller
.

19

PULSE EDGE DETECT

Input
19 GENERATOR 19 19 CIRCUIT Line

EVENT
MASK
REGISTER

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6.2.3 Wake-up event management

Cortex-M3 is able to handle external events or internal events in order to wake-up the core
(WFE). By configuring the external lines any I/O port, RTC Alarm and USB Wake-up Events
can be used to wake-up the CPU (exit from WFE).
To use an external line as a wake-up event, refer to Section 6.2.4: Functional description.

6.2.4 Functional description

To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
generated. The pending bit corresponding to the interrupt line is also set. This request is
reset by writing a ‘1’ in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse if generated. The pending bit
corresponding to the event line is not set
An interrupt/event request can also be generated by software by writing a ‘1’ in the software
interrupt/event register.

Hardware interrupt selection

To configure the 19 lines as interrupt sources, use the following procedure:
● Configure the mask bits of the 19 Interrupt lines (EXTI_IMR)
● Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and
EXTI_FTSR)
● Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
External Interrupt Controller (EXTI) so that an interrupt coming from one of the 19 lines
can be correctly acknowledged.

Hardware event selection

To configure the 19 lines as event sources, use the following procedure:
● Configure the mask bits of the 19 Event lines (EXTI_EMR)
● Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR)

Software interrupt/event selection

The 19 lines can be configured as software interrupt/event lines. The following is the
procedure to generate a software interrupt.
● Configure the mask bits of the 19 Interrupt/Event lines (EXTI_IMR, EXTI_EMR)
● Set the required bit of the software interrupt register (EXTI_SWIER)

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6.2.5 External interrupt/event line mapping

The 80 GPIOs are connected to the 16 external interrupt/event lines in the following manner:

Figure 15. External interrupt/event GPIO mapping

EXTI0[3:0] bits in AFIO_EXTICR1 register

PA0
PB0
EXTI0
PC0
PD0
PE0

EXTI1[3:0] bits in AFIO_EXTICR1 register

PA1
PB1
EXTI1
PC1
PD1
PE1

EXTI15[3:0] bits in AFIO_EXTICR4 register

PA15
PB15
EXTI15
PC15
PD15
PE15

The three other EXTI lines are connected as follows:

● EXTI line 16 is connected to the PVD output
● EXTI line 17 is connected to the RTC Alarm event
● EXTI line 18 is connected to the USB Wake-up event

6.3 EXTI register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

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Interrupt mask register (EXTI_IMR)

Address Offset: 00h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved MR18 MR17 MR16

rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value (0).

MRx: Interrupt Mask on line x
Bits 18:0 0: Interrupt request from Line x is masked
1: Interrupt request from Line x is not masked

Event mask register (EXTI_EMR)

Address Offset: 04h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved MR18 MR17 MR16

rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value (0).

MRx: Event Mask on line x
Bits 18:0 0: Event request from Line x is masked
1: Event request from Line x is not masked

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Rising Trigger selection register (EXTI_RTSR)

Address Offset: 08h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved TR18 TR17 TR16

rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value (0).

TRx: Rising trigger event configuration bit of line x
Bits 18:0 0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge triggered, no glitches must be generated on these
lines.
If a rising edge on external interrupt line occurs during writing of EXTI_RTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.

Falling Trigger selection register (EXTI_FTSR)

Address Offset: 0Ch
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved TR18 TR17 TR16

rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value (0).

TRx: Falling trigger event configuration bit of line x
Bits 18:0 0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.

Note: The external wake-up lines are edge triggered, no glitches must be generated on these
lines.
If a falling edge on external interrupt line occurs during writing of EXTI_FTSR register, the
pending bit will not be set.
Rising and Falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.

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Software interrupt event register (EXTI_SWIER)

Address Offset: 10h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SWIER SWIER SWIER

Reserved
18 17 16

rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:19 Reserved, must be kept at reset value (0).

SWIERx: Software Interrupt on line x
Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If
the interrupt is enabled on this line on the EXTI_IMR and EXTI_EMR, an interrupt
Bits 18:0
request is generated.
This bit is cleared by clearing the corresponding bit of EXTI_PR (by writing a 1 into the
bit).

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UM0306 Interrupts and events

Pending register (EXTI_PR)

Address Offset: 14h
Reset value: xxxx xxxxh

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved PR18 PR17 PR16

rc_w1 rc_w1 rc_w1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PR15 PR14 PR13 PR12 PR11 PR10 PR9 PR8 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0

rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1

Bits 31:19 Reserved, must be kept at reset value (0).

PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
Bits 18:0 This bit is cleared by writing a 1 into the bit or by changing the sensitivity of the edge
detector.
Note: If an interrupt request occurs one cycle before entering STOP mode, then the
EXTI_PR register will be updated only after exit from STOP mode, generating an
interrupt request if the corresponding bit in the EXTI_IMR register is set

6.3.1 EXTI register map

Table 28. External interrupt/event controller register map and reset values
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

Offset Register
9
8
7
6
5
4
3
2
1
0
EXTI_IMR MR[18:0]
00h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_EMR MR[18:0]
04h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_RTSR TR[18:0]
08h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_FTSR TR[18:0]
0Ch Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_SWIER SWIER[18:0]
10h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

EXTI_PR PR[18:0]
14h Reserved

Reset Value x x x x x x x x x x x x x x x x x x x

Refer to Table 1 on page 27 for the register boundary addresses.

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DMA controller (DMA) UM0306

7 DMA controller (DMA)

7.1 Introduction
Direct Memory Access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has 7 channels, each dedicated to managing memory access requests
from one or more peripherals. It has an arbiter for handling the priority between DMA
requests.

7.2 Main features

● 7 independently configurable channels (requests)
● Each of the 7 channels is connected to dedicated hardware DMA requests, software
trigger is also supported on each channel. This configuration is done by software.
● The priorities between the seven requests is software programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request 1
has priority over request 2, etc.)
● Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking.
● Support for circular buffer management
● 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error)
logically ORed together in a single interrupt request for each channel
● Memory-to-memory transfer
● Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers
● Access to Flash, SRAM, peripheral SRAM, APB1 and APB2 peripherals as source and
destination
● Programmable number of data to be transferred: up to 65536
The block diagram is shown in Figure 16.

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Figure 16. DMA block diagram

ICode
FLITF Flash
DCode
Cortex-M3
System

SRAM

DMA AHB System Bus Bridge 1

Ch.1
Bridge 2 APB2 APB1
Ch.2

Ch.7 USART2
USART1 USART3 TIM2
SPI2 TIM3
SPI1 TIM4
Arbiter I2C1
ADC1 I2C2
TIM1

AHB Slave

DMA Request

7.3 Functional description

The DMA controller performs direct memory transfer sharing the system bus with the
Cortex-M3 core. Thus, 1 DMA request stops the CPU accessing the system bus for at least
2 cycles. To guarantee a minimum bandwidth to the Cortex-M3 core the code execution, the
DMA controller always releases the system bus for at least one cycle between two
consecutive DMA requests.

7.3.1 DMA transactions

After an event, the peripheral sends a request signal to the DMA Controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA
Controller. The peripheral releases its request as soon as it gets the Acknowledge from the
DMA Controller. Once the request is deasserted by the peripheral, the DMA Controller
release the Acknowledge. If there are more requests, the peripheral can initiate the next
transaction.
In summary, each DMA transfer consists of three operations:
● A load from the peripheral data register or a location in memory addressed through the
DMA_CMARx register
● A store of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_CMARx register
● A post-decrement of the DMA_CNDTRx register, which contains the number of
transactions that have still to be performed.

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7.3.2 Arbiter
The arbiter manages the channel requests based on their priority and launches the
peripheral/memory access sequences.
The priorities are managed in two stages:
● Software: each channel priority can be configured in the DMA_CCRx register. There
are four levels:
– Very high priority
– High priority
– Medium priority
– Low priority
● Hardware: if 2 requests have the same software priority level, the channel with the
lowest number will get priority versus the channel with the highest number. For
example, channel 2 gets priority over channel 4.

7.3.3 DMA channels

Each channel can handle DMA transfer between a peripheral register located at a fixed
address and a memory address. The amount of data to be transferred (up to 65535) is
programmable. The register which contains the amount of data items to be transferred is
decremented after each transaction.

Programmable data sizes

Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE
and MSIZE bits in the DMA_CCRx register.

Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented after
each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If
incremented mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer
address will be the one programmed in the DMA_CPARx/DMA_CMARx registers.
If the channel is configured in non-circular mode, no DMA requests are served after the end
of the transfer (i.e. once the number of data to be transferred reaches zero).

Channel configuration procedure

The following sequence should be followed to configure a DMA channel (where x is the
channel number).

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1. Set the peripheral register address in the DMA_CPARx register. The data will be
moved from/ to this address to/ from the memory after the peripheral event.
2. Set the memory address in the DMA_CMARx register. The data will be written to or
read from this memory after the peripheral event.
3. Configure the total number of data to be transferred in the DMA_CNDTRx register.
After each peripheral event, this value will be decremented.
4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register
5. Configure data transfer direction, circular mode, peripheral & memory incremented
mode, peripheral & memory data size, and interrupt after half and/or full transfer in the
DMA_CCRx register
6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register.
As soon as the channel is enabled, it can serve any DMA request from the peripheral
connected on the channel.
Once half of the bytes are transferred, the Half-Transfer Flag (HTIF) is set and an interrupt is
generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer,
the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer
Complete Interrupt Enable bit (TCIE) is set.

Circular mode
Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC
scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register.
When circular mode is activated, the number of data to be transferred is automatically
reloaded with the initial value programmed during the channel configuration phase, and the
DMA requests continue to be served.

Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This mode is called Memory to Memory mode.
If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as
soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register.
The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory
mode may not be used at the same time as Circular mode.

7.3.4 Error management

In case of bus error during a DMA read or a write access, the faulty channel is automatically
disabled with through a hardware clear of its EN bit in the corresponding Channel
Configuration Register (DMA_CCRx). The channel's Transfer Error Interrupt Flag (TEIF) in
the DMA_IFR register is set and an interrupt is generated if the Transfer Error Interrupt
Enable bit (TEIE) in the DMA_CCRx register is set.

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7.3.5 DMA request mapping

The 7 requests from the peripherals (TIMx, ADC, SPIx, I2Cx and USARTx) are simply
logically ORed before entering to the DMA, this means that only one request must be
enabled at a time. Refer to Figure 17: DMA request mapping.
The peripheral DMA requests can be independently activated/de-activated by programming
the DMA control bit in the registers of the corresponding peripheral.

Figure 17. DMA request mapping

PERIPHERAL FIXED HARDWARE PRIORITY

REQUEST SIGNALS
HIGH PRIORITY
ADC1 HW REQUEST 1
CHANNEL 1
TIM2_CH3
TIM4_CH1
SW TRIGGER (MEM2MEM bit)

Channel 1 EN bit
USART3_TX
TIM1_CH1 HW REQUEST 2
CHANNEL 2
TIM2_UP
TIM3_CH3 SW TRIGGER (MEM2MEM bit)
SPI1_RX

Channel 2 EN bit
USART3_RX
TIM1_CH2 HW REQUEST 3
CHANNEL 3
TIM3_CH4
TIM3_UP
SW TRIGGER (MEM2MEM bit)
SPI1_TX
internal
USART1_TX Channel 3 EN bit
TIM1_CH4 DMA
TIM1_TRIG HW REQUEST 4 REQUEST
CHANNEL 4
TIM1_COM
TIM4_CH2
SW TRIGGER (MEM2MEM bit)
SPI2_RX
I2C2_TX
Channel 4 EN bit
USART1_RX
TIM1_UP
HW REQUEST 5
SPI2_TX CHANNEL 5
TIM2_CH1
TIM4_CH3 SW TRIGGER (MEM2MEM bit)
I2C2_RX
Channel 5 EN bit
USART2_RX
TIM1_CH3 HW REQUEST 6
CHANNEL 6
TIM3_CH1
TIM3_TRIG SW TRIGGER (MEM2MEM bit)
I2C1_TX

Channel 6 EN bit

USART2_TX HW REQUEST 7
TIM2_CH2 CHANNEL 7
TIM2_CH4 LOW PRIORITY
SW TRIGGER (MEM2MEM bit)
TIM4_UP
I2C1_RX
Channel 7 EN bit

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Table 29 lists the DMA requests for each channel.

Table 29. Summary of DMA requests for each channel

Peripherals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7

ADC ADC1

SPI SPI1_RX SPI1_TX SPI2_RX SPI2_TX

USART USART3_TX USART3_RX USART1_TX USART1_RX USART2_RX USART2_TX

I2C I2C2_TX I2C2_RX I2C1_TX I2C1_RX

TIM1_CH4
TIM1 TIM1_CH1 TIM1_CH2 TIM1_TRIG TIM1_UP TIM1_CH3
TIM1_COM

TIM2_CH2
TIM2 TIM2_CH3 TIM2_UP TIM2_CH1
TIM2_CH4

TIM3_CH4 TIM3_CH1
TIM3 TIM3_CH3
TIM3_UP TIM3_TRIG

TIM4 TIM4_CH1 TIM4_CH2 TIM4_CH3 TIM4_UP

7.4 DMA registers

Refer to Section 1.1 on page 23 for a list of abbreviations used in the register descriptions.

7.4.1 DMA interrupt status register (DMA_ISR)

Address Offset: 00h
Reset Value: 0000 0000 (00h)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5

r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1

r r r r r r r r r r r r r r r r

Bits 31:28 Reserved, always read as 0.

TEIFx: Channel x Transfer Error flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the
Bits 27, 23, 19,
corresponding bit in the DMA_IFCR register.
15, 11, 7, 3
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x

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HTIFx: Channel x Half Transfer flag (x = 1 ..7)

This bit is set by hardware. It is cleared by software writing 1 to the
Bits 26, 22, 18,
corresponding bit in the DMA_IFCR register.
14, 10, 6, 2
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
TCIFx: Channel x Transfer Complete flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the
Bits 25, 21, 17,
corresponding bit in the DMA_IFCR register.
13, 9, 5, 1
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
GIFx: Channel x Global interrupt flag (x = 1 ..7)
This bit is set by hardware. It is cleared by software writing 1 to the
Bits 24, 20, 16,
corresponding bit in the DMA_IFCR register.
12, 8, 4, 0
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x

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7.4.2 DMA interrupt flag clear register (DMA_IFCR)

Address Offset: 04h
Reset Value: 0000 0000 (00h)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF
Reserved
7 7 7 7 6 6 6 6 5 5 5 5

rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF CTEIF CHTIF CTCIF CGIF
4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:28 Reserved, always read as 0.

CTEIFx: Channel x Transfer Error clear (x = 1 ..7)
Bits 27, 23, 19, This bit is set and cleared by software.
15, 11, 7, 3 0: No effect
1: Clears the corresponding TEIF flag in the DMA_ISR register
CHTIFx: Channel x Half Transfer clear (x = 1 ..7)
Bits 26, 22, 18, This bit is set and cleared by software.
14, 10, 6, 2 0: No effect
1: Clears the corresponding HTIF flag in the DMA_ISR register
CTCIFx: Channel x Transfer Complete clear (x = 1 ..7)
Bits 25, 21, 17, This bit is set and cleared by software.
13, 9, 5, 1 0: No effect
1: Clears the corresponding TCIF flag in the DMA_ISR register
CGIFx: Channel x Global interrupt clear (x = 1 ..7)
Bits 24, 20, 16, This bit is set and cleared by software.
12, 8, 4, 0 0: No effect
1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register

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7.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1 ..7)

Address Offset: 08h + 20d x Channel number
Reset Value: 0000 0000 (00h)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MEM2
Res. PL[1:0] MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR TEIE HTIE TCIE EN
MEM

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, always read as 0.

MEM2MEM: Memory to memory mode
This bit is set and cleared by software.
Bit 14
0: Memory to memory mode disabled
1: Memory to memory mode enabled
PL[1:0]: Channel Priority level
These bits are set and cleared by software.
00: Low
Bits 13:12
01: Medium
10: High
11: Very high
MSIZE[1:0]: Memory size
These bits are set and cleared by software.
00: 8-bits
Bits 11:10
01: 16-bits
10: 32-bits
11: Reserved
PSIZE[1:0]: Peripheral size
These bits are set and cleared by software.
00: 8-bits
Bits 9:8
01: 16-bits
10: 32-bits
11: Reserved
MINC: Memory increment mode
This bit is set and cleared by software.
Bit 7
0: Memory increment mode disabled
1: Memory increment mode enabled
PINC: Peripheral increment mode
This bit is set and cleared by software.
Bit 6
0: Peripheral increment mode disabled
1: Peripheral increment mode enabled

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CIRC: Circular mode

This bit is set and cleared by software.
Bit 5
0: Circular mode disabled
1: Circular mode enabled
DIR: Data transfer direction
This bit is set and cleared by software.
Bit 4
0: Read from peripheral
1: Read from memory
TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
Bit 3
0: TE interrupt disabled
1: TE interrupt enabled
HTIE: Half Transfer interrupt enable
This bit is set and cleared by software.
Bit 2
0: HT interrupt disabled
1: HT interrupt enabled
TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
Bit 1
0: TC interrupt disabled
1: TC interrupt enabled
EN: Channel enable
This bit is set and cleared by software.
Bit 0
0: Channel disabled
1: Channel enabled

7.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1 ..7)

Address Offset: 0Ch + 20d x Channel number
Reset Value: 0000 0000 (00h)

Bits 31:16 Reserved, always read as 0.

NDT[15:0]: Number of data to Transfer
Number of data to be transferred (0 up to 65535). This register can only be written
when the channel is disabled. Once the channel is enabled, this register is read-only,
indicating the remaining bytes to be transmitted. This register decrements after each
DMA transfer.
Bits 15:0
Once the transfer is completed, this register can either stay at zero or be reloaded
automatically by the value previously programmed if the channel is configured in
auto-reload mode.
If this register is zero, no transaction can be served whether the channel is enabled or
not.

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7.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1 ..7)

Address Offset: 10h + 20d x Channel number
Reset Value: 0000 0000 (00h)

PA[31:0]: Peripheral Address

Bits 31:0 Base address of the peripheral data register from/to which the data will be
read/written.

7.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1 ..7)

Address Offset: 14h + 20d x Channel number
Reset Value: 0000 0000 (00h)

MA[31:0]: Memory Address

Bits 31:0
Base address of the memory area from/to which the data will be read/written.

7.5 DMA register map

Table 30. DMA - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
HTIF7

HTIF6

HTIF5

HTIF4

HTIF3

HTIF2

HTIF1
TCIF7

TCIF6

TCIF5

TCIF4

TCIF3

TCIF2

TCIF1
TEIF7

TEIF6

TEIF5

TEIF4

TEIF3

TEIF2

TEIF1
GIF7

GIF6

GIF5

GIF4

GIF3

GIF2

GIF1
DMA_ISR
000h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CHTIF7

CHTIF6

CHTIF5
CTCIF7

CHTIF4
CTCIF6

CHTIF3
CTCIF5

CHTIF2
CTCIF4

CHTIF1
CTCIF3

CTCIF2

CTCIF1
CTEIF7

CTEIF6

CTEIF5

CTEIF4

CTEIF3

CTEIF2

CTEIF1
CGIF7

CGIF6

CGIF5

CGIF4

CGIF3

CGIF2

CGIF1
DMA_IFCR
004h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MEM2MEM

M
MINC

CIRC
PINC

HTIE
TCIE
PL PSIZE
TEIE
DIR

EN
DMA_CCR1 SIZE
008h Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR1 NDT[15:0]
00Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CPAR1 PA[31:0]
010h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR1 MA[31:0]
014h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
018h Reserved
MEM2MEM

M
MINC

CIRC
PINC

HTIE
TCIE

PL PSIZE
TEIE
DIR

EN

DMA_CCR2 SIZE
01Ch Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR2 NDT[15:0]
020h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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UM0306 DMA controller (DMA)

Table 30. DMA - register map and reset values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
DMA_CPAR2 PA[31:0]
024h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR2 MA[31:0]
028h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
02Ch Reserved

MEM2MEM
M

MINC

CIRC
PINC

HTIE
TCIE
PL PSIZE

TEIE
DIR

EN
DMA_CCR3 SIZE
030h Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR3 NDT[15:0]
034h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CPAR3 PA[31:0]
038h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR3 MA[31:0]
03Ch
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
040h Reserved
MEM2MEM
M

MINC

CIRC
PINC

HTIE
TCIE
PL PSIZE

TEIE
DIR

EN
DMA_CCR4 SIZE
044h Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR4 NDT[15:0]
048h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CPAR4 PA[31:0]
04Ch
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR4 MA[31:0]
050h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
054h Reserved
MEM2MEM

M
MINC

CIRC
PINC

HTIE
TCIE

PL PSIZE
TEIE
DIR

EN

DMA_CCR5 SIZE
058h Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR5 NDT[15:0]
05Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CPAR5 PA[31:0]
060h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR5 MA[31:0]
064h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
068h Reserved

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Table 30. DMA - register map and reset values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
MEM2MEM
M

MINC

CIRC
PINC

HTIE
TCIE
PL PSIZE

TEIE
DIR

EN
DMA_CCR6 SIZE
06Ch Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR6 NDT[15:0]
070h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CPAR6 PA[31:0]
074h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR6 MA[31:0]
078h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
07Ch Reserved

MEM2MEM
M

MINC

CIRC
PINC

HTIE
TCIE
PL PSIZE

TEIE
DIR

EN
DMA_CCR7 SIZE
080h Reserved [1:0] [1:0]
[1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CNDTR7 NDT[15:0]
084h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CPAR7 PA[31:0]
088h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DMA_CMAR7 MA[31:0]
08Ch
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
090h Reserved

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 Real-Time Clock (RTC)

8 Real-Time Clock (RTC)

8.1 Introduction
The Real-Time Clock is an independent timer. The RTC provides a set of continuously-
running counters which can be used, with suitable software, to provide a clock-calendar
function. The counter values can be written to set the current time/date of the system.

8.2 Main features

● Programmable prescaler: division factor up to 220
● 32-bit programmable counter for long-term measurement
● Two separate clocks: PCLK1 for the APB1 interface and RTC clock (must be at least
four times slower than the PCLK1 clock)
● Two separate reset types:
– The APB1 interface is reset by system reset
– The RTC Core (Prescaler, Alarm, Counter and Divider) is reset only by a Backup
domain reset (see Section 4.1.3: Backup domain Reset on page 46).
● Three dedicated maskable interrupt lines:
– Alarm interrupt, for generating a software programmable alarm interrupt.
– Seconds interrupt, for generating a periodic interrupt signal with a programmable
period length (up to 1 second).
– Overflow interrupt, to detect when the internal programmable counter rolls over to
zero.

8.3 Functional description

8.3.1 Overview
The RTC consists of two main units (see Figure 18 on page 122). The first one (APB1
Interface) is used to interface with the APB1 bus. This unit also contains a set of 16-bit
registers accessible from the APB1 bus in read or write mode (for more information refer to
Section 8.4: RTC register description on page 125). The APB1 interface is clocked by the
APB1 bus clock in order to interface with the APB1 bus.
The other unit (RTC Core) consists of a chain of programmable counters made of two main
blocks. The first block is the RTC prescaler block, which generates the RTC time base
TR_CLK that can be programmed to have a period of up to 1 second. It includes a 20-bit
programmable divider (RTC Prescaler). Every TR_CLK period, the RTC generates an
interrupt (Second Interrupt) if it is enabled in the RTC_CR register. The second block is a
32-bit programmable counter that can be initialized to the current system time. The system
time is incremented at the TR_CLK rate and compared with a programmable date (stored in
the RTC_ALR register) in order to generate an alarm interrupt, if enabled in the RTC_CR
control register.

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Figure 18. RTC simplified block diagram

APB1 bus
PCLK1

APB1 interface not powered in STANDBY

RTCCLK
Backup domain
RTC_CR
RTC_PRL
RTC_Second
SECF
Reload 32-bit programmable
counter SECIE
TR_CLK RTC_Overflow
RTC_DIV RTC_CNT OWF
rising OWIE
edge RTC_Alarm
RTC prescaler = ALRF
ALRIE
RTC_ALR
not powered in STANDBY
powered in STANDBY

NVIC INTERRUPT
powered in STANDBY CONTROLLER

not powered in STANDBY

WKUP pin RTC_Alarm EXIT FROM

WKP_STDBY STANDBY MODE
powered in STANDBY

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8.3.2 Resetting RTC registers

All system registers are asynchronously reset by a System Reset or Power Reset, except for
RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV.
The RTC_PRL, RTC_ALR, RTC_CNT, and RTC_DIV registers are reset only by a Backup
Domain reset. Refer to Section 4.1.3 on page 46.

8.3.3 Reading RTC registers

The RTC core is completely independent from the RTC APB1 interface.
Software accesses the RTC prescaler, counter and alarm values through the APB1 interface
but the associated readable registers are internally updated at each rising edge of the RTC
clock resynchronized by the RTC APB1 clock. This is also true for the RTC flags.
This means that the first read to the RTC APB1 registers may be corrupted (generally read
as 0) if the APB1 interface has previously been disabled and the read occurs immediately
after the APB1 interface is enabled but before the first internal update of the registers. This
can occur if:
● A system reset or power reset has occurred
● The MCU has just woken up from STANDBY mode (see Section 3.3: Low-power
modes)
● The MCU has just woken up from STOP mode (see Section 3.3: Low-power modes)
In all the above cases, the RTC core has been kept running while the APB1 interface was
disabled (reset, not clocked or unpowered).
Consequently when reading the RTC registers, after having disabled the RTC APB1
interface, the software must first wait for the RSF bit (Register Synchronized Flag) in the
RTC_CRL register to be set by hardware.
Note that the RTC APB1 interface is not affected by WFI and WFE low-power modes.

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8.3.4 Configuring RTC registers

To write in the RTC_PRL, RTC_CNT, RTC_ALR registers, the peripheral must enter
Configuration Mode. This is done by setting the CNF bit in the RTC_CRL register.
In addition, writing to any RTC register is only enabled if the previous write operation is
finished. To enable the software to detect this situation, the RTOFF status bit is provided in
the RTC_CR register to indicate that an update of the registers is in progress. A new value
can be written to the RTC registers only when the RTOFF status bit value is ’1’.

Configuration procedure:
1. Poll RTOFF, wait until its value goes to ‘1’
2. Set the CNF bit to enter configuration mode
3. Write to one or more RTC registers
4. Clear the CNF bit to exit configuration mode
5. Poll RTOFF, wait until its value goes to ‘1’ to check the end of the write operation.
The write operation only executes when the CNF bit is cleared; it takes at least three
RTCCLK cycles to complete.

8.3.5 Asserting RTC flags

The RTC Second flag (SECF) is asserted on each RTC Core clock cycle before the update
of the RTC Counter.
The RTC Overflow flag (OWF) is asserted on the last RTC Core clock cycle before the
counter reaches 0x0000.
The RTC_Alarm and RTC Alarm flag (ALRF) (see Figure 19) are asserted on the last RTC
Core clock cycle before the counter reaches the RTC Alarm value stored in the Alarm
register increased by one (RTC_ALR + 1). The write operation in the RTC Alarm and RTC
Second flag must be synchronized by using one of the following sequences:
● Use the RTC Alarm interrupt and inside the RTC interrupt routine, the RTC Alarm
and/or RTC Counter registers are updated.
● Wait for SECF bit to be set in the RTC Control register. Update the RTC Alarm and/or
the RTC Counter register.

Figure 19. RTC second and alarm waveform example with PR=0003, ALARM=00004
RTCCLK

RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003

RTC_Second

RTC_CNT 0000 0001 0002 0003 0004 0005

RTC_ALARM
1 RTCCLK

ALRF can be cleared by software

(not powered
in STANDBY)

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Figure 20. RTC Overflow waveform example with PR=0003

RTCCLK

RTC_PR 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003 0002 0001 0000 0003

RTC_Second

RTC_CNT FFFFFFFB FFFFFFFC FFFFFFFD FFFFFFFE FFFFFFFF 0000

RTC_Overflow
1 RTCCLK

OWF can be cleared by software

(not powered
in STANDBY)

8.4 RTC register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

8.4.1 RTC control register High (RTC_CRH)

Address Offset: 00h
Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved OWIE ALRIE SECIE

rw rw rw

Bits 15:3 Reserved, forced by hardware to 0.

OWIE: OverfloW Interrupt Enable
Bit 2 0: Overflow interrupt is masked.
1: Overflow interrupt is enabled.
ALRIE: Alarm Interrupt Enable
Bit 1 0: Alarm interrupt is masked.
1: Alarm interrupt is enabled.
SECIE: Second Interrupt Enable
Bit 0 0: Second interrupt is masked.
1: Second interrupt is enabled.

These bits are used to mask interrupt requests. Note that at reset all interrupts are disabled,
so it is possible to write to the RTC registers to ensure that no interrupt requests are pending
after initialization. It is not possible to write to the RTC_CRH register when the peripheral is
completing a previous write operation (flagged by RTOFF=0, see Section 8.3.4 on page
124).
The RTC functions are controlled by this control register. Some bits must be written using a
specific configuration procedure (see Configuration procedure:).

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8.4.2 RTC control register low (RTC_CRL)

Address Offset: 04h
Reset value: 0020h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RTOFF CNF RSF OWF ALRF SECF

r rw rc_w0 rc_w0 rc_w0 rc_w0

Bits 15:6 Reserved, forced by hardware to 0.

RTOFF: RTC operation OFF
With this bit the RTC reports the status of the last write operation performed on its
registers, indicating if it has been completed or not. If its value is ‘0’ then it is not
Bit 5
possible to write to any of the RTC registers. This bit is read only.
0: Last write operation on RTC registers is still ongoing.
1: Last write operation on RTC registers terminated.
CNF: Configuration Flag
This bit must be set by software to enter in configuration mode so as to allow new
values to be written in the RTC_CNT, RTC_ALR or RTC_PRL registers. The write
Bit 4
operation is only executed when the CNF bit is reset by software after has been set.
0: Exit configuration mode (start update of RTC registers).
1: Enter configuration mode.
RSF: Registers Synchronized Flag
This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are
updated and cleared by software. Before any read operation after an APB1 reset or
Bit 3 an APB1 clock stop, this bit must be cleared by software, and the user application
must wait until it is set to be sure that the RTC_CNT, RTC_ALR or RTC_PRL
registers are synchronized.
0: Registers not yet synchronized.
1: Registers synchronized.
OWF: OverfloW Flag
This bit is set by hardware when the 32-bit programmable counter overflows. An
interrupt is generated if OWIE=1 in the RTC_CRH register. It can be cleared only by
Bit 2
software. Writing ‘1’ has no effect.
0: Overflow not detected
1: 32-bit programmable counter overflow occurred.
ALRF: Alarm Flag
This bit is set by hardware when the 32-bit programmable counter reaches the
threshold set in the RTC_ALR register. An interrupt is generated if ALRIE=1 in the
Bit 1
RTC_CRH register. It can be cleared only by software. Writing ‘1’ has no effect.
0: Alarm not detected
1: Alarm detected
SECF: Second Flag
This bit is set by hardware when the 32-bit programmable prescaler overflows, thus
incrementing the RTC counter. Hence this flag provides a periodic signal with a
Bit 0 period corresponding to the resolution programmed for the RTC counter (usually
one second). An interrupt is generated if SECIE=1 in the RTC_CRH register. It can
be cleared only by software. Writing ‘1’ has no effect.
0: Second flag condition not met.
1: Second flag condition met.

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The functions of the RTC are controlled by this control register. It is not possible to write to
the RTC_CR register while the peripheral is completing a previous write operation (flagged
by RTOFF=0, see Section 8.3.4 on page 124).
Note: 1 Any flag remains pending until the appropriate RTC_CR request bit is reset by software,
indicating that the interrupt request has been granted.
2 At reset the interrupts are disabled, no interrupt requests are pending and it is possible to
write to the RTC registers.
3 The OWF, ALRF, SECF and RSF bits are not updated when the APB1 clock is not running.
4 The OWF, ALRF, SECF and RSF bits can only be set by hardware and only cleared by
5 If ALRF = 1 and ALRIE = 1, the RTC global interrupt is enabled. If EXTI Line 17 is also
enabled through the EXTI Controller, both the RTC global interrupt and the RTC Alarm
interrupt are enabled.
6 If ALRF = 1, the RTC Alarm interrupt is enabled if EXTI Line 17 is enabled through the EXTI
Controller in interrupt mode. When the EXTI Line 17 is enabled in event mode, a pulse is
generated on this line (no RTC Alarm interrupt generation).

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8.4.3 RTC prescaler load register (RTC_PRLH / RTC_PRLL)

The Prescaler Load registers keep the period counting value of the RTC prescaler. They are
write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if
the RTOFF value is ‘1’.

RTC prescaler load register high (RTC_PRLH)

Address Offset: 08h
Write only (see Section 8.3.4 on page 124)
Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved PRL[19:16]

w w w w

Bits 15:4 Reserved, forced by hardware to 0.

PRL[19:16]: RTC Prescaler Reload Value High
These bits are used to define the counter clock frequency according to the following
formula:
Bits 3:0
fTR_CLK = fRTCCLK/(PRL[19:0]+1)
Caution: The zero value is not recommended. RTC interrupts and flags cannot be
asserted correctly.

RTC prescaler load register low (RTC_PRLL)

Address Offset: 0Ch
Write only (see Section 8.3.4 on page 124)
Reset value: 8000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRL[15:0]

w w w w w w w w w w w w w w w w

PRL[15:0]: RTC Prescaler Reload Value Low

These bits are used to define the counter clock frequency according to the following
Bits 15:0
formula:
fTR_CLK = fRTCCLK/(PRL[19:0]+1)

Note: If the input clock frequency (fRTCCLK) is 32.768 kHz, write 7FFFh in this register to get a
signal period of 1 second.

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8.4.4 RTC prescaler divider register (RTC_DIVH / RTC_DIVL)

During each period of TR_CLK, the counter inside the RTC prescaler is reloaded with the
value stored in the RTC_PRL register. To get an accurate time measurement it is possible to
read the current value of the prescaler counter, stored in the RTC_DIV register, without
stopping it. This register is read-only and it is reloaded by hardware after any change in the
RTC_PRL or RTC_CNT registers.

RTC prescaler divider register high (RTC_DIVH)

Address Offset: 10h
Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RTC_DIV[19:16]

r r r r

Bits 15:4 Reserved

Bits 3:0 RTC_DIV[19:16]: RTC Clock Divider High

RTC prescaler divider register low (RTC_DIVL)

Address Offset: 14h
Reset value: 8000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC_DIV[15:0]

r r r r r r r r r r r r r r r r

Bits 15:0 RTC_DIV[15:0]: RTC Clock Divider Low

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8.4.5 RTC counter register (RTC_CNTH / RTC_CNTL)

The RTC core has one 32-bit programmable counter, accessed through two 16-bit registers;
the count rate is based on the TR_CLK time reference, generated by the prescaler.
RTC_CNT registers keep the counting value of this counter. They are write-protected by bit
RTOFF in the RTC_CR register, and a write operation is allowed if the RTOFF value is ‘1’. A
write operation on the upper (RTC_CNTH) or lower (RTC_CNTL) registers directly loads the
corresponding programmable counter and reloads the RTC Prescaler. When reading, the
current value in the counter (system date) is returned.

RTC counter register high (RTC_CNTH)

Address Offset: 18h
Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC_CNT[31:16]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RTC_CNT[31:16]: RTC Counter High

Reading the RTC_CNTH register, the current value of the high part of the RTC
Bits 15:0
Counter register is returned. To write to this register it is necessary to enter
configuration mode using the RTOFF bit in the RTC_CR register.

RTC counter register low (RTC_CNTL)

Address Offset: 1Ch
Reset value: 0000h

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC_CNT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

RTC_CNT[15:0]: RTC Counter Low

Reading the RTC_CNTL register, the current value of the lower part of the RTC
Bits 15:0
Counter register is returned. To write to this register it is necessary to enter
configuration mode using the RTOFF bit in the RTC_CR register.

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8.4.6 RTC alarm register high (RTC_ALRH / RTC_ALRL)

When the programmable counter reaches the 32-bit value stored in the RTC_ALR register,
an alarm is triggered and the RTC_alarmIT interrupt request is generated. This register is
write-protected by the RTOFF bit in the RTC_CR register, and a write operation is allowed if
the RTOFF value is ‘1’.

RTC alarm register high (RTC_ALRH)

Address Offset: 20h
Write only (see Section 8.3.4 on page 124)
Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC_ALR[31:16]

w w w w w w w w w w w w w w w w

RTC_ALR[31:16]: RTC Alarm High

The high part of the alarm time is written by software in this register. To write to this
Bits 15:0
register it is necessary to enter configuration mode using the RTOFF bit in the
RTC_CR register.

RTC alarm register low (RTC_ALRL)

Address Offset: 24h
Write only (see Section 8.3.4 on page 124)
Reset value: FFFFh

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RTC_ALR[15:0]

w w w w w w w w w w w w w w w w

RTC_ALR[15:0]: RTC Alarm Low

The low part of the alarm time is written by software in this register. To write to this
Bits 15:0
register it is necessary to enter configuration mode using the RTOFF bit in the
RTC_CR register.

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8.5 RTC register map

RTC registers are mapped as 16-bit addressable registers as described in the table below:
Table 31. RTC - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0 SECIE
ALRIE
OWIE
RTC_CRH
000h Reserved
Reset Value 0 0 0

RTOFF

SECF
ALRF
OWF
CNF
RSF
RTC_CRL
004h Reserved
Reset Value 1 0 0 0 0 0

RTC_PRLH PRL[19:16]
008h Reserved
Reset Value 0 0 0 0

RTC_PRLL PRL[15:0]
00Ch Reserved
Reset Value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_DIVH DIV[31:16]
010h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_DIVL DIV[15:0]
014h Reserved
Reset Value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

018h RTC_CNTH CNT[13:16]

Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_CNTL CNT[15:0]
01Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RTC_ALRH ALR[31:16]
020h Reserved
Reset Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RTC_ALRL ALR[15:0]
024h Reserved
Reset Value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 Backup registers (BKP)

9 Backup registers (BKP)

9.1 Introduction
The backup registers are ten 16-bit registers for storing 20 bytes of user application data.
They are implemented in the backup domain that remains powered on by VBAT when the
VDD power is switched off. They are not reset when the device wakes up from STANDBY
mode or by a system reset or power reset.
In addition, the BKP control registers are used to manage the Tamper detection feature and
RTC calibration.
After reset, the access to Backup registers and RTC is disabled and the Backup domain is
protected against possible parasitic write access.
The DBP bit must be set in the Power control register (PWR_CR) to enable access to the
Backup registers and RTC.

9.2 Features
● Ten 16-bit data registers.
● Status/control register for managing the anti-Tamper feature
● Calibration register for storing the RTC calibration value

9.3 Tamper detection

The ANTI_TAMP pin generates a Tamper detection event when the pin changes from 0 to 1
or from 1 to 0 depending on the TPAL bit in the Backup control register (BKP_CR). A tamper
detection event resets all data backup registers.
However to avoid losing Tamper events, the signal used for edge detection is logically
ANDed with the Tamper enable in order to detect a Tamper event in case it occurs before
the Tamper pin is enabled.
● When TPAL=0: If the Tamper pin is already high before it is enabled (by setting TPE
bit), an extra Tamper event is detected as soon as the Tamper pin is enabled (while
there was no rising edge on the Tamper pin after TPE was set)
● When TPAL=1: If the Tamper pin is already low before it is enabled (by setting the TPE
bit), an extra Tamper event is detected as soon as the Tamper pin is enabled (while
there was no falling edge on the Tamper pin after TPE was set)
After a Tamper event has been detected and cleared, the Tamper pin should be disabled
and then re-enabled with TPE before writing to the backup data registers (BKP_DRx) again.
This prevents software from writing to the backup data registers (BKP_DRx), while the
Tamper pin value still indicates a Tamper detection. This is equivalent to a level detection on
the Tamper pin.
Note: Tamper detection is still active when VDD power is switched off. To avoid unwanted resetting
of the data backup registers, the ANTI_TAMP pin should be externally tied to the correct
level.

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9.4 RTC calibration

For measurement purposes, the 32.768 kHZ RTC clock can be output on the Tamper pin.
This is enabled by setting the CCO bit in the RTC clock calibration register (BKP_RTCCR).
The clock can be slowed down by up to 121 ppm by configuring CAL[6:0] bits.

9.5 BKP register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

9.5.1 Backup data register x (BKP_DRx) (x = 1 ..10)

Address Offset: 04h to 28h
Reset Value: 0000 0000 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

D[15:0] Backup data.

These bits can be written with user data.
Bits 15:0 Note: The BKP_DRx registers are not reset by a System reset or Power reset or when
the device wakes up from STANDBY mode.
They are reset by a Backup Domain reset or by a Tamper pin event (if the Tamper pin
function is activated).

9.5.2 RTC clock calibration register (BKP_RTCCR)

Address Offset: 2Ch
Reset Value: 0000 0000 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved CCO CAL[6:0]

rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, always read as 0.

CCO Calibration Clock Output
0: No effect
1: Setting this bit outputs the RTC clock with frequency divided by 64 on the Tamper
Bit 7
pin. The Tamper pin must not be enabled while the CCO bit is set in order to avoid
unwanted Tamper detection.
Note: This bit is reset when the VDD supply is powered off.
CAL[6:0] Calibration value
This value indicates the number of clock pulses that will be ignored every 2^20 clock
Bit 6:0 pulses. This allows the calibration of the RTC, slowing down the clock by steps of
1000000/2^20 PPM.
The clock of the RTC can be slowed down from 0 to 121PPM.

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9.5.3 Backup control register (BKP_CR)

Address Offset: 30h
Reset Value: 0000 0000 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TPAL TPE

rw rw

Bits 15:2 Reserved, always read as 0.

TPAL Tamper pin active level
Bit 1 0: A high level on the Tamper pin resets all data backup registers (if TPE bit is set).
1: A low level on the Tamper pin resets all data backup registers (if TPE bit is set).
TPE Tamper pin enable
Bit 0 0: The Tamper pin is free for general purpose I/O
1: Tamper alternate I/O function is activated.

Note: Setting the TPAL and TPE bits at the same time is always safe, however resetting both at
the same time can generate a spurious Tamper event. For this reason it is recommended to
change the TPAL bit only when the TPE bit is reset.

9.5.4 Backup control/status register (BKP_CSR)

Address Offset: 34h
Reset Value: 0000 0000 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TIF TEF Reserved TPIE CTI CTE

r r rw w w

Bits 15:10 Reserved, always read as 0.

TIF Tamper Interrupt Flag
This bit is set by hardware when a Tamper event is detected and the TPIE bit is set.
It is cleared by writing 1 to the CTI bit (also clears the interrupt). It is also cleared if
Bit 9 the TPIE bit is reset.
0: No Tamper interrupt
1: A Tamper interrupt occurred
Note: This bit is reset only by a system reset and wake-up from STANDBY mode.
TEF Tamper Event Flag
This bit is set by hardware when a Tamper event is detected. It is cleared by writing
1 to the CTE bit.
0: No Tamper event
Bit 8
1: A Tamper event occurred
Note: A Tamper event resets all the BKP_DRx registers. They are held in reset as
long as the TEF bit is set. If a write to the BKP_DRx registers is performed while this
bit is set, the value will not be stored.
Bits 7:3 Reserved, always read as 0.

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Backup registers (BKP) UM0306

TPIE Tamper Pin interrupt enable

0: Tamper interrupt disabled
Bit 2 1: Tamper interrupt enabled (the TPE bit must also be set in the BKP_CR register
Note 1: A Tamper interrupt does not wake up the core from low-power modes.
Note 2: This bit is reset only by a system reset and wake-up from STANDBY mode.
CTI Clear Tamper Interrupt
This bit is write only, and is always read as 0.
Bit 1
0: No effect
1: Clear the Tamper interrupt and the TIF Tamper interrupt flag.
CTE Clear Tamper event
This bit is write only, and is always read as 0.
Bit 0
0: No effect
1: Reset the TEF Tamper event flag (and the Tamper detector)

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9.6 BKP register map

BKP registers are mapped as 16-bit addressable registers as described in the table below:

Table 32. BKP - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
00h Reserved

BKP_DR1 D[15:0]
04h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR2 D[15:0]
08h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR3 D[15:0]
0Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR4 D[15:0]
10h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR5 D[15:0]
14h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR6 D[15:0]
18h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR7 D[15:0]
1Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR8 D[15:0]
20h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR9 D[15:0]
24h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BKP_DR10 D[15:0]
28h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CCO

BKP_RTCCR CAL[6:0]
2C Reserved
Reset Value 0 0 0 0 0 0 0 0
TPAL
TPE

BKP_CR
30h Reserved
Reset Value 0 0
TPIE

CTE
TEF

CTI
TIF

BKP_CSR
34h Reserved Reserved
Reset Value 0 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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10 Independent watchdog (IWDG)

The STM32F10x has two embedded watchdog peripherals which offer a combination of
high safety level, timing accuracy and flexibility of use. Both Watchdog peripherals
(Independent and Window) serve to detect and resolve malfunctions due to software failure,
and triggering an interrupt or system reset when the counter reaches a given time-out value.
The Independent Watchdog (IWDG) is clocked by its own dedicated low-speed clock (32
kHz) and thus stays active even if the main clock fails. The Window Watchdog (WWDG)
clock is prescaled from the APB1 clock and has a configurable time-window that can be
programmed to detect abnormally late or early application behavior.
The IWDG is best suited to applications which require the watchdog to run as a totally
independent process outside the main application, but have lower timing accuracy
constraints. The WWDG is best suited to applications which require the watchdog to react
within an accurate timing window.
For further information on the Window Watchdog, refer to Section 11 on page 145.

10.1 Introduction
Figure 21 shows the functional blocks of the independent Watchdog module.
When the independent watchdog is started by writing the value CCCCh in the Key Register
(IWDG_KR), the counter starts counting down from the reset value of FFFh. When it
reaches the end of count value (000h) a reset signal is generated (IWDG RESET).
Whenever the key value AAAAh is written in the IWDG_KR register, the IWDG_RLR value is
re-loaded in the counter and the watchdog reset is prevented.

10.1.1 Hardware watchdog

If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog
is automatically enabled at power on, and will generate a reset unless the Key register is
written by the software before the counter reaches end of count.

10.1.2 Register access protection

Write access to the IWDG_PR and IWDG_RLR registers is protected. To modify them, you
must first write the code 5555h in the IWDG_KR register. A write access to this register with
a different value will break the sequence and register access will be protected again. This
implies that it is the case of the reload operation (writing AAAAh)
A status register is available to indicate that an update of the prescaler or the down-counter
reload value is on going.

10.1.3 Debug mode

When the microcontroller enters debug mode (Cortex-M3 core halted), the IWDG counter
either continues to work normally or stops, depending on DBG_IWDG_STOP configuration
bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and
watchdog and bxCAN.

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UM0306 Independent watchdog (IWDG)

Figure 21. Independent watchdog block diagram

1.8 V voltage domain
Prescaler Register Status Register Reload Register Key Register
IWDG_PR IWDG_SR IWDG_RLR IWDG_KR

8-bit 12-bit reload value

LSI
(32 kHz) Prescaler
IWDG RESET
12-bit Down-counter
VDD voltage domain

Note: The watchdog function is implemented in the VDD voltage domain that is still functional in
STOP and STANDBY modes.

Table 33. Watchdog time-out period (with 32 kHz input clock)

Min Time-out Max Time-out
Prescaler Divider PR[2:0] bits
RL[11:0]= 000h RL[11:0]= FFFh

/4 0 0.125 ms 512.5 ms
/8 1 0.25 ms 1025 ms
/16 2 0.50 ms 2050 ms
/32 3 1 ms 4100 ms
/64 4 2 ms 8200 ms
/128 5 4 ms 16400 ms
/256 6 (or 7) 8 ms 32800 ms

Note: These timings are given for a 32 kHz clock but the microcontroller’s internal RC frequency
can vary from 30 to 90 kHz. Moreover, given an exact RC oscillator frequency, the exact
timings still depend on the phasing of the APB interface clock versus the RC oscillator 32
kHz clock so that there is always a full RC period of uncertainty.

10.2 IWDG register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

10.2.1 Key register (IWDG_KR)

Address Offset: 00h
Reset value: 00000000h (reset by STANDBY mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

KEY[15:0]

w w w w w w w w w w w w w w w w

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Bits 31:16 Reserved, read as 0.

KEY[15:0]: Key value (write only, read 0000h)
These bits must be written by software at regular intervals with the key value
AAAAh, otherwise the watchdog generates a reset when the counter reaches
0.
Bits 15:0
Writing the key value 5555h to enables access to the IWDG_PR and
IWDG_RLR registers (see Section 10.1.2)
Writing the key value CCCCh starts the watchdog (except if the hardware
watchdog option is selected)

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10.2.2 Prescaler register (IWDG_PR)

Address Offset: 04h
Reset value: 00000000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved PR[2:0]

rw rw rw

Bits 31:3 Reserved, read as 0.

PR[2:0]: Prescaler divider
These bits are write access protected seeSection 10.1.2. They are written by
software to select the prescaler divider feeding the counter clock. PVU bit of
IWDG_SR must be reset in order to be able to change the prescaler divider.
000: divider /4
001: divider /8
010: divider /16
011: divider /32
Bits 2:0
100: divider /64
101: divider /128
110: divider /256
111: divider /256
Note: Reading this register returns the prescaler value from the VDD voltage
domain. This value may not be up to date/valid if a write operation to this register
is ongoing. For this reason the value read from this register is valid only when
the PVU bit in the IWDG_SR register is reset.

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10.2.3 Reload register (IWDG_RLR)

Address Offset: 08h
Reset value: 00000FFFh (reset by STANDBY mode)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RL[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, read as 0.

RL[11:0]: Watchdog counter reload value
These bits are write access protected see Section 10.1.2. They are written by
software to define the value to be loaded in the watchdog counter each time
the value AAAAh is written in the IWDG_KR register. The watchdog counter
counts down from this value. The time-out period is a function of this value and
the clock prescaler. Refer to Table 33.
Bits11:0
The RVU bit in the IWDG_SR register must be reset in order to be able to
change the reload value.
Note: reading this register returns the reload value from the VDD voltage
domain. This value may not be up to date/valid if a write operation to this register
is ongoing on this register. For this reason the value read from this register is
valid only when the RVU bit in the IWDG_SR register is reset.

10.2.4 Status register (IWDG_SR)

Address Offset: 0Ch
Reset value: 00000000h (not reset by STANDBY mode)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RVU PVU

r r

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Bits 31:2 Reserved

RVU: Watchdog counter reload value update
This bit is set by hardware to indicate that an update of the reload value is
Bit 1 ongoing. It is reset by hardware when the reload value update operation is
completed in the VDD voltage domain (takes up to 5 RC 32 kHz cycles).
Reload value can be updated only when RVU bit is reset.
PVU: Watchdog prescaler value update
This bit is set by hardware to indicate that an update of the prescaler value is
Bit 0 ongoing. It is reset by hardware when the prescaler update operation is
completed in the VDD voltage domain (takes up to 5 RC 32 kHz cycles).
Prescaler value can be updated only when PVU bit is reset.

Note: If several reload values or prescaler values are used by application, it is mandatory to wait
until RVU bit is reset before changing the reload value and to wait until PVU bit is reset
before changing the prescaler value. However, after updating the prescaler and/or the
reload value it is not necessary to wait until RVU or PVU is reset before continuing code
execution (even in case of low-power mode entry, the write operation is taken into account
and will complete)

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10.3 IWDG register map

Table 34. IWDG register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
IWDG_KR KEY[15:0]
00h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

IWDG_PR PR[2:0]
04h Reserved

Reset Value 0 0 0

IWDG_RLR RL[11:0]
08h Reserved

Reset Value 1 1 1 1 1 1 1 1 1 1 1 1

RVU
PVU
IWDG_SR
0Ch Reserved

Reset Value 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 Window watchdog (WWDG)

11 Window watchdog (WWDG)

11.1 Introduction
The Window Watchdog is used to detect the occurrence of a software fault, usually
generated by external interference or by unforeseen logical conditions, which causes the
application program to abandon its normal sequence. The Watchdog circuit generates an
MCU reset on expiry of a programmed time period, unless the program refreshes the
contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also
generated if the 7-bit downcounter value (in the control register) is refreshed before the
downcounter has reached the window register value. This implies that the counter must be
refreshed in a limited window.

11.2 Main features

● Programmable free-running downcounter
● Conditional reset
– Reset (if watchdog activated) when the downcounter value becomes less than 40h
– Reset (if watchdog activated) if the downcounter is reloaded outside the window
(see Figure 23)

11.3 Functional description

If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the
7-bit downcounter (T[6:0] bits) rolls over from 40h to 3Fh (T6 becomes cleared), it initiates a
reset. If the software reloads the counter while the counter is greater than the value stored in
the window register, then a reset is generated.

Figure 22. Watchdog block diagram

RESET WATCHDOG CONFIGURATION REGISTER (WWDG_CFR)

- W6 W5 W4 W3 W2 W1 W0

comparator
= 1 when
T6:0 > W6:0 CMP

Write WWDG_CR
WATCHDOG CONTROL REGISTER (WWDG_CR)

WDGA T6 T5 T4 T3 T2 T1 T0
6-BIT DOWNCOUNTER (CNT)
PCLK1
(from RCC clock controller)
WDG PRESCALER
(WDGTB)

The application program must write in the WWDG_CR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter

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Window watchdog (WWDG) UM0306

value is lower than the window register value. The value to be stored in the WWDG_CR
register must be between FFh and C0h:
● Enabling the watchdog:
he watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in
the WWDG_CR register, then it cannot be disabled again except by a reset.
● Controlling the downcounter:
This downcounter is free-running: It counts down even if the watchdog is disabled.
When the watchdog is enabled, the T6 bit must be set to prevent generating an
immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset. The timing varies between a minimum and a
maximum value due to the unknown status of the prescaler when writing to the
WWDG_CR register (see Figure 23).

The Configuration register (WWDG_CFR) contains the high limit of the window: To
prevent a reset, the downcounter must be reloaded when its value is lower than the
window register value and greater than 3Fh. Figure 23 describes the window watchdog
process.
Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).

11.4 How to program the watchdog timeout

Figure 23 shows the linear relationship between the 6-bit value to be loaded in the
Watchdog Counter (CNT) and the resulting timeout duration in milliseconds. This can be
used for a quick calculation without taking the timing variations into account. If more
precision is needed, use the formulae in Figure 23.

Warning: When writing to the WWDG_CR register, always write 1 in the

T6 bit to avoid generating an immediate reset.

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UM0306 Window watchdog (WWDG)

Figure 23. Window watchdog timing diagram

T[6:0] CNT downcounter

W[6:0]

3Fh

time
Refresh not allowed Refresh Window

T6 bit

Reset

The formula to calculate the timeout value is given by:

WDGTB
T WWDG = T PCLK1 × 4096 × 2 × ( T [ 5:0 ] + 1 ) ;( ms )

where:
TWWDG: WWDG timeout
TPCLK1: APB1 Clock period measured in ms

Min-max timeout value @36MHz (PCLK1)

WDGTB Min Timeout Value Max Timout Value

0 113 µs 7.28 ms
1 227 µs 14.56 ms
2 455 µs 29.12 ms
3 910 µs 58.25 ms

11.5 Debug mode

When the microcontroller enters debug mode (Cortex-M3 core halted), the WWDG counter
either continues to work normally or stops, depending on DBG_WWDG_STOP configuration
bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and
watchdog and bxCAN.

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11.6 Register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

11.6.1 Control Register (WWDG_CR)

Address Offset: 00h
Reset Value: 0111 1111 (7Fh)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved WDGA T6 T5 T4 T3 T2 T1 T0

rs rw rw rw rw rw rw rw

Bits 31:8 Reserved

WDGA: Activation bit
This bit is set by software and only cleared by hardware after a reset. When
Bit 7 WDGA = 1, the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled

T[6:0]: 7-bit counter (MSB to LSB).

Bits 6:0 These bits contain the value of the watchdog counter. It is decremented every
(4096 x 2WDGTB) PCLK1 cycles. A reset is produced when it rolls over from 40h
to 3Fh (T6 becomes cleared).

11.6.2 Configuration register (WWDG_CFR)

Address Offset: 04h
Reset Value: 0111 1111 (7Fh)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

WDG WDG
Reserved EWI W6 W5 W4 W3 W2 W1 W0
TB1 TB0

rs rw rw rw rw rw rw rw rw rw

Bit 31:10 Reserved

EWI: Early Wakeup Interrupt
Bit 9 When set, an interrupt occurs whenever the counter reaches the value 40h.
This interrupt is only cleared by hardware after a reset.

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WDGTB[1:0]: Timer Base

The time base of the prescaler can be modified as follows:
00: CK Counter Clock (PCLK1 div 4096) div 1
Bits 8:7
01: CK Counter Clock (PCLK1 div 4096) div 2
10: CK Counter Clock (PCLK1 div 4096) div 4
11: CK Counter Clock (PCLK1 div 4096) div 8
W[6:0] 7-bit window value
Bits 6:0
These bits contain the window value to be compared to the downcounter.

11.6.3 Status register (WWDG_SR)

Address Offset: 08h
Reset Value: 0000 0000 (00h)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved EWIF

rc_w0

Bit 31:1 Reserved

EWIF: Early Wakeup Interrupt Flag
Bit 0 This bit is set by hardware when the counter has reached the value 40h. It
must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit
is also set if the interrupt is not enabled.

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11.7 WWDG register map

Table 35. WWDG register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
WDGA
WWDG_CR T[6:0]
00h Reserved

Reset Value 0 1 1 1 1 1 1 1

WDGTB1
WDGTB0
EWI
WWDG_CFR W[6:0]
04h Reserved

Reset Value 0 0 0 1 1 1 1 1 1 1

EWIF
WWDG_SR
08h Reserved

Reset Value 0

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 Advanced control timer (TIM1)

12 Advanced control timer (TIM1)

12.1 Introduction
The Advanced Control Timer (TIM1) consists of a 16-bit auto-reload counter driven by a
programmable prescaler.
It may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare, PWM,
complementary PWM with dead-time insertion...).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The advanced control (TIM1) and general purpose (TIMx) timers are completely
independent, and do not share any resources. They can be synchronized together as
described in Section 12.4.20.

12.2 Main features

TIM1 timer features include:
● 16-bit up, down, up/down auto-reload counter.
● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65535.
● Up to 4 independent channels for:
– Input Capture
– Output Compare
– PWM generation (Edge and Center-aligned Mode)
– One Pulse Mode output
– Complementary Outputs with programmable dead-time
● Synchronization circuit to control the timer with external signals and to interconnect
several timers together.
● Repetition counter to update the timer registers only after a given number of cycles of
the counter.
● Break input to put the timer’s output signals in reset state or in a known state.
● Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger
– Input capture
– Output compare
– Break input

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12.3 Block diagram

Figure 24. Advanced control timer (TIM1) block diagram

TIM1CLK from RCC Internal Clock (CK_INT)

ETRF
Trigger
ETRP Controller
ETR Polarity Selection & Edge
TIM1_ETR Input Filter TRGO
Detector & Prescaler
to other timers
from TIM2 (ITR1)
TGI
ITR
from TIM3 (ITR2) Slave
TRC Mode Reset, Enable, Up/Down, Count
from TIM4 (ITR3) TRGI
Controller

TI1F_ED

TI1FP1 Encoder
TI2FP2 Interface

REP Register
UI
U AutoReload Register
Repetition
counter U
Stop, Clear or Up/Down

CK_PSC PSC CK_CNT +/- CNT

Prescaler COUNTER
DTG registers
CC1I CC1I TIM1_CH1
TI1FP1 IC1 IC1PS U
XOR TI1
Input Filter & OC1REF
TI1FP2 Prescaler Capture/Compare 1 Register DTG output OC1
EdgeDetector
control TIM1_CH1N
TIM1_CH1 TRC OC1N
CC2I
CC2I TIM1_CH2
TI2 TI2FP1 IC2 IC2PS U
TIM1_CH2 Input Filter & Prescaler OC2REF output OC2
EdgeDetector TI2FP2 Capture/Compare 2 Register DTG
control TIM1_CH2N
TRC OC2N
CC3I
CC3I TIM1_CH3
TI3FP3 IC3 U
TIM1_CH3
TI3 Input Filter & IC3PS OC3REF output OC3
EdgeDetector
TI3FP4 Prescaler Capture/Compare 3 Register DTG
control TIM1_CH3N
TRC OC3N
CC4I
CC4I
U TIM1_CH4
TI4FP3 IC4 IC4PS
TI4 Input Filter & OC4REF output
TIM1_CH4 TI4FP4 Prescaler Capture/Compare 4 Register
EdgeDetector control OC4
TRC

ETRF

BRK BI
TIM1_BKIN Polarity Selection

Clock failure event from clock controller

CSS (Clock Security system

Notes:
Reg Preload registers transferred
to active registers on U event
according to control bit

event

interrupt & DMA output

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UM0306 Advanced control timer (TIM1)

12.4 Functional description

12.4.1 Time base unit

The main block of the programmable advanced control timer is a 16-bit counter with its
related auto-reload register. The counter can count up, down or both up and down. The
counter clock can be divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.
The Time Base Unit includes:
● Counter Register (TIM1_CNT)
● Prescaler Register (TIM1_PSC):
● Auto-Reload Register (TIM1_ARR)
● Repetition Counter Register (TIM1_RCR)
The auto-reload register is preloaded. Writing or reading the auto-reload register access the
preload register. The content of the preload register is transferred in the shadow register
permanently or at each update event UEV, depending on the auto-reload preload enable bit
(ARPE) in TIM1_CR1 register. The update event is sent when the counter reaches the
overflow (or underflow when down-counting) and if the UDIS bit equals 0 in the TIM1_CR1
register. It can also be generated by software. The generation of the update event is
described in detailed for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIM1_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIM1_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken into account at the next update event.
Figure 25 and Figure 26 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

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Figure 25. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F7 F8 F9 FA FB FC 00 01 02 03

UPDATE EVENT (UEV)

PRESCALER CONTROL REGISTER 0 1

Write a new value in TIM1_PSC

PRESCALER BUFFER 0 1

PRESCALER COUNTER 0 0 1 0 1 0 1 0 1

Figure 26. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F7 F8 F9 FA FB FC 00 01

UPDATE EVENT (UEV)

PRESCALER CONTROL REGISTER 0 3

Write a new value in TIM1_PSC

PRESCALER BUFFER 0 3

PRESCALER COUNTER 0 0 1 2 3 0 1 2 3

12.4.2 Counter modes

Up-counting mode
In up-counting mode, the counter counts from 0 to the auto-reload value (content of the
TIM1_ARR register), then restarts from 0 and generates a counter overflow event.
If the repetition counter is used, the update event (UEV) is generated after up-counting is
repeated for the number of times programmed in the repetition counter register
(TIM1_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIM1_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the

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preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate doesn’t change). In addition, if the URS bit (update request selection) in
TIM1_CR1 register is set, setting the UG bit generates an update event UEV but without
setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating
both update and capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIM1_RCR register,
The auto-reload shadow register is updated with the preload value (TIM1_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIM1_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIM1_ARR=0x36.

Figure 27. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 28. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0034 0035 0036 0000 0001 0002 0003

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

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Figure 29. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0035 0036 0000 0001

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 30. Counter timing diagram, internal clock divided by N

CK_PSC

TIMER CLOCK = CK_CNT

COUNTER REGISTER 1F 20 00

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 31. Counter timing diagram, Update event when ARPE=0 (TIM1_ARR not
preloaded)

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD REGISTER FF 36

Write a new value in TIM1_ARR

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UM0306 Advanced control timer (TIM1)

Figure 32. Counter timing diagram, Update event when ARPE=1 (TIM1_ARR
preloaded)

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD PRELOAD REGISTER F5 36

AUTO-RELOAD SHADOW REGISTER F5 36

Write a new value in TIM1_ARR

Down-counting mode
In down-counting mode, the counter counts from the auto-reload value (content of the
TIM1_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
If the repetition counter is used, the update event (UEV) is generated after up-counting is
repeated for the number of times programmed in the repetition counter register
(TIM1_RCR). Else the update event is generated at each counter overflow.
Setting the UG bit in the TIM1_EGR register (by software or by using the slave mode
controller) also generates an update event.
The UEV update event can be disabled by software by setting the UDIS bit in TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIM1_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR register) is set (depending on the URS bit):
● The repetition counter is reloaded with the content of TIM1_RCR register,
● The auto-reload active register is updated with the preload value (content of the
TIM1_ARR register). Note that the auto-reload is updated before the counter is
reloaded, so that the next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIM1_ARR=0x36.

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Figure 33. Counter timing diagram, internal clock divided by 1

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

COUNTER UNDERFLOW (cnt_udf)

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 34. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0002 0001 0000 0036 0035 0034 0033

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 35. Counter timing diagram, internal clock divided by 4

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0001 0000 0036 0035

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

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Figure 36. Counter timing diagram, internal clock divided by N

CK_PSC

TIMER CLOCK = CK_CNT

COUNTER REGISTER 20 1F 00 36

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 37. Counter timing diagram, Update event when repetition counter is not
used

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD REGISTER FF 36

Write a new value in TIM1_ARR

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIM1_ARR register), generates an counter overflow event, then counts down to 0 and
generates a counter underflow event. Then it restarts counting from 0.
In this mode, the DIR direction bit in the TIM1_CR1 register cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIM1_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in the TIM1_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.

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In addition, if the URS bit (update request selection) in TIM1_CR1 register is set, setting the
UG bit generates an UEV update event but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIM1_SR register) is set (depending on the URS bit):
The repetition counter is reloaded with the content of TIM1_RCR register,
The auto-reload active register is updated with the preload value (content of the TIM1_ARR
register). Note that if the update source is a counter overflow, the auto-reload is updated
before the counter is reloaded, so that the next period is the expected one (the counter is
loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 38. Counter timing diagram, internal clock divided by 1, TIM1_ARR=0x6

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 04 03 02 01 00 01 02 03 04 05 06 05 04 03

COUNTER UNDERFLOW

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Note: Here, center-aligned mode 1 is used

Figure 39. Counter timing diagram, internal clock divided by 2

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0003 0002 0001 0000 0001 0002 0003

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

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Figure 40. Counter timing diagram, internal clock divided by 4, TIM1_ARR=0x36

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0034 0035 0036 0035

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow

Figure 41. Counter timing diagram, internal clock divided by N

CK_PSC

TIMER CLOCK = CK_CNT

COUNTER REGISTER 20 1F 01 00

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 42. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 06 05 04 03 02 01 00 01 02 03 04 05 06 07

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD PRELOAD REGISTER FD 36

Write a new value in TIM1_ARR

AUTO-RELOAD ACTIVE REGISTER FD 36

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Figure 43. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD PRELOAD REGISTER FD 36

Write a new value in TIM1_ARR

AUTO-RELOAD ACTIVE REGISTER FD 36

12.4.3 Repetition down-counter

Section 12.4.1: Time base unit describes how the update event (UEV) is generated with
respect to the counter overflows/underflows. It is actually generated only when the repetition
down-counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIM1_ARR auto-reload register, TIM1_PSC prescaler register, but also TIM1_CCRx
capture/compare registers in compare mode) every N counter overflows or underflows,
where N is the value in the TIM1_RCR repetition counter register.
The repetition down-counter is decremented:
● At each counter overflow in up-counting mode,
● At each counter underflow in down-counting mode,
● At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 128 PWM cycles, it makes it
possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xTck, due to the symmetry of the pattern.
The repetition down-counter is an auto-reload type; the repetition rate is maintained as
defined by the TIM1_RCR register value (refer to Figure 44). When the update event is
generated by software (by setting the UG bit in TIM1_EGR register) or by hardware through
the slave mode controller, it occurs immediately whatever the value of the repetition down-
counter is and the repetition down-counter is reloaded with the content of the TIM1_RCR
register.

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Figure 44. Update rate examples depending on mode and TIM1_RCR register
settings

Center-aligned mode Edge-aligned mode

Up-Counting Down-Counting
Counter
TIM1_CNT

TIM1_RCR = 0 UEV

TIM1_RCR = 1 UEV

TIM1_RCR = 2 UEV

TIM1_RCR = 3 UEV

TIM1_RCR = 3
and
re-synchronization
UEV
(by SW) (by SW) (by SW)

UEV Update Event: Preload registers transferred to active registers and update interrupt generated
Update Event if the repetition down-counter underflow occurs when the counter is equal to
to the auto-reload value.

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12.4.4 Clock selection

The counter clock can be provided by the following clock sources:
● Internal clock (CK_INT)
● External clock mode1: external input pin
● External clock mode2: external trigger input ETR
● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to Section :
Using one timer as prescaler for another timer on page 255 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000), then the CEN, DIR (in the TIM1_CR1
register) and UG bits (in the TIM1_EGR register) are actual control bits and can be changed
only by software (except UG which remains cleared automatically). As soon as the CEN bit
is written to 1, the prescaler is clocked by the internal clock CK_INT.
Figure 45 shows the behavior of the control circuit and the up-counter in normal mode,
without prescaler.

Figure 45. Control circuit in normal mode, internal clock divided by 1

Internal clock

CEN=CNT_EN

UG

CNT_INIT

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07

External clock source mode 1

This mode is selected when SMS=111 in the TIM1_SMCR register. The counter can count
at each rising or falling edge on a selected input.

Figure 46. TI2 external clock connection example

TIM1_SMCR
TS[2:0]

ti2f or
or
ti1f or encoder
ITR1 001 mode
ti1f_ed 100
ti1fp1 trgi external clock
ti2f_rising 0 101 mode 1 ck_psc
TI2 Filter Edge ti2fp2 110
Detector ti2f_falling etrf external clock
1 etrf 111 mode 2
ICF[3:0] CC2P CK_INT internal clock
TIM1_CCMR1 TIM1_CCER mode
(internal clock)

ECE SMS[2:0]
TIM1_SMCR

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For example, to configure the up-counter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01’ in the
TIM1_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIM1_CCMR1
register (if no filter is needed, keep IC2F=0000).
3. Select rising edge polarity by writing CC2P=0 in the TIM1_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIM1_SMCR
register.
5. Select TI2 as the trigger input source by writing TS=110 in the TIM1_SMCR register.
6. Enable the counter by writing CEN=1 in the TIM1_CR1 register.
Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.
The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 47. Control circuit in external clock mode 1

TI2

CNT_EN

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 34 35 36

TIF

Write TIF=0

External clock source mode 2

This mode is selected by writing ECE=1 in the TIM1_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 48 gives an overview of the external trigger input block.

Figure 48. External trigger input block

ti2f or
or
ti1f or encoder
mode

trgi external clock

mode 1 ck_psc
ETR
ETR pin 0 ETRP
divider filter ETRF external clock
down-counter mode 2
/1, /2, /4, /8 fDTS
1
CK_INT internal clock
mode
(internal clock)
ETP ETPS[1:0] ETF[3:0]
TIM1_SMCR TIM1_SMCR TIM1_SMCR ECE SMS[2:0]
TIM1_SMCR

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For example, to configure the up-counter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIM1_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIM1_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIM1_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIM1_SMCR register.
5. Enable the counter by writing CEN=1 in the TIM1_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

Figure 49. Control circuit in external clock mode 2

fCK_INT

CNT_EN

ETR

ETRP

ETRF

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 34 35 36

12.4.5 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
Figure 50 to Figure 53 give an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

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Figure 50. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
to the slave mode controller

TI1F_rising 0
TI1 TI1F
filter Edge TI1FP1
01
fDTS down-counter Detector TI1F_falling
1
TI2FP1 IC1 divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P TRC
11
TIM1_CCMR1 TIM1_CCER (from slave mode
controller)
TI2F_rising 0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_falling
1
(from channel 2) TIM1_CCMR1 TIM1_CCER

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

Figure 51. Capture/compare channel 1 main circuit

APB Bus

MCU-PERIPHERAL INTERFACE
(if 16-bit)

8 8
high

low

S write CCR1H
read CCR1H S write_in_progress
read_in_progress
Capture/Compare Preload Register write CCR1L
read CCR1L R
R CC1S[1]
output
capture_transfer compare_transfer mode
CC1S[0]
CC1S[1] input
mode OC1PE
Capture/Compare Shadow Register OC1PE
CC1S[0] UEV
TIM1_CCMR1
comparator (from time
ic1ps capture base unit)
CC1E CNT>CCR1
Counter
CNT=CCR1
CC1G
TIM1_EGR

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Figure 52. Output stage of capture/compare channel (channel 1 to 3)

ETR 0
Output OC1
‘0’ Enable
x0 1 Circuit
10
oc1_dt CC1P
CNT>CCR1 11
Output Mode oc1ref Dead-Time TIM1_CCER
CNT=CCR1 Controller Generator
oc1n_dt
11
10 0 OC1N
Output
‘0’ 0x Enable
1 Circuit

CC1NE CC1E TIM1_CCER

OC1CE OC1M[2:0] DTG[7:0] CC1NE CC1E CC1NP MOE OSSI OSSR TIM1_BDTR
TIM1_CCMR1 TIM1_BDTR TIM1_CCER TIM1_CCER

Figure 53. Output stage of capture/compare channel (channel 4)

ETR To the master mode 0

controller Output OC1
Enable
1 Circuit

CC1P
CNT > CCR1
Output Mode oc1ref TIM1_CCER
CNT = CCR1 Controller

CC1E TIM1_CCER

OC1M[2:0] MOE OSSI TIM1_BDTR

TIM1_CCMR1
OIS1 TIM1_CR2

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

12.4.6 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIM1_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIM1_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIM1_SR register) is set. CCxIF can be
cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIM1_CCRx register (when you read the low byte in case of 16-bit register). CCxOF is
cleared when you write it to ‘0’.

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The following example shows how to capture the counter value in TIM1_CCR1 when TI1
input rises. To do this, use the following procedure:
● Select the active input: TIM1_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIM1_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIM1_CCR1 register becomes read-only.
● Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIM1_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIM1_CCMR1 register.
● Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIM1_CCER register (rising edge in this case).
● Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the
TIM1_CCMR1 register).
● Enable capture from the counter into the capture register by setting the CC1E bit in the
TIM1_CCER register.
● If needed, enable the related interrupt request by setting the CC1IE bit in the
TIM1_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIM1_DIER register.
When an input capture occurs:
● The TIM1_CCR1 register gets the value of the counter on the active transition.
● CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
● An interrupt is generated depending on the CC1IE bit.
● A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIM1_EGR register.

12.4.7 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
● Two ICx signals are mapped on the same TIx input.
● These 2 ICx signals are active on edges with opposite polarity.
● One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

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For example, you can measure the period (in TIM1_CCR1 register) and the duty cycle (in
TIM1_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
● Select the active input for TIM1_CCR1: write the CC1S bits to 01 in the TIM1_CCMR1
register (TI1 selected).
● Select the active polarity for TI1FP1 (used both for capture in TIM1_CCR1 and counter
clear): write the CC1P bit to ‘0’ (active on rising edge).
● Select the active input for TIM1_CCR2: write the CC2S bits to 10 in the TIM1_CCMR1
register (TI1 selected).
● Select the active polarity for TI1FP2 (used for capture in TIM1_CCR2): write the CC2P
bit to ‘1’ (active on falling edge).
● Select the valid trigger input: write the TS bits to 101 in the TIM1_SMCR register
(TI1FP1 selected).
● Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIM1_SMCR register.
● Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIM1_CCER register.

Figure 54. PWM input mode timing.

TI1

TIM1_CNT 0004 0000 0001 0002 0003 0004 0000

TIM1_CCR1 0004

TIM1_CCR2 0002

IC1 Capture IC2 Capture

period measurement pulse width measurement
reset counter

12.4.8 Forced output mode

In output mode (CCxS bits = 00 in the TIM1_CCMRx register), each output compare signal
(OCxREF and then OCx/OCxN) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (OCXREF/OCx) to its active level, you just need to write
101 in the OCxM bits in the corresponding TIM1_CCMRx register. Thus OCXREF is forced
high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
For example: CCxP=0 (OCx active high) => OCx is forced to high level.
The OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIM1_CCMRx
register.
Anyway, the comparison between the TIM1_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section below.

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12.4.9 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
● Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIM1_CCMRx register) and the output polarity
(CCxP bit in the TIM1_CCER register). The output pin can keep its level (OCXM=000),
be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on
match.
● Sets a flag in the interrupt status register (CCxIF bit in the TIM1_SR register).
● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIM1_DIER register).
● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIM1_DIER register, CCDS bit in the TIM1_CR2 register for the DMA request
selection).
The TIM1_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIM1_CCMRx register.
In output compare mode, the update event UEV has no effect on OCxREF and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse Mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIM1_ARR and TIM1_CCRx registers.
3. Set the CCxIE bit if an interrupt request is to be generated.
4. Select the output mode. For example:
– Write OCxM = 011 to toggle OCx output pin when CNT matches CCRx
– Write OCxPE = 0 to disable preload register
– Write CCxP = 0 to select active high polarity
– Write CCxE = 1 to enable the output
5. Enable the counter by setting the CEN bit in the TIM1_CR1 register.
The TIM1_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIM1_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 55.

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Figure 55. Output compare mode, toggle on OC1.

Write B201h in the OC1R register

TIM1_CNT 0039 003A 003B B200 B201

TIM1_CCR1 003A B201

oc1ref=OC1

Match detected on OCR1

Interrupt generated if enabled

12.4.10 PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIM1_ARR register and a duty cycle determined by the value of the
TIM1_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIM1_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIM1_CCMRx register, and eventually the auto-reload preload register (in
up-counting or center-aligned modes) by setting the ARPE bit in the TIM1_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIM1_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIM1_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIM1_CCER register when the break feature is not implemented, else by a combination
of CCxE, CCxNE, MOE, OSSI and OSSR bits (TIM1_CCER and TIM1_BDTR registers).
Refer to the TIM1_CCERx register description for more details.
In PWM mode (1 or 2), TIM1_CNT and TIM1_CCRx are always compared to determine
whether TIM1_CCRx≤TIM1_CNT or TIM1_CNT≤TIM1_CCRx (depending on the direction
of the counter).
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIM1_CR1 register.

PWM edge-aligned mode

Up-counting configuration
Up-counting is active when the DIR bit in the TIM1_CR1 register is low. Refer to the Up-
counting mode on page 154.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIM1_CNT <TIM1_CCRx else it becomes low. If the compare value in
TIM1_CCRx is greater than the auto-reload value (in TIM1_ARR) then OCxREF is held at

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‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 56 shows some edge-aligned
PWM waveforms in an example where TIM1_ARR=8.

Figure 56. Edge-aligned PWM waveforms (ARR=8)

COUNTER REGISTER 0 1 2 3 4 5 6 7 8 0 1

ocxref
CCRx=4
CCxIF

ocxref
CCRx=8
CCxIF

ocxref ‘1’
CCRx>8
CCxIF

ocxref ‘0’
CCRx=0
CCxIF

Down-counting configuration
Down-counting is active when DIR bit in TIM1_CR1 register is high. Refer to the Down-
counting mode on page 157
In PWM mode 1, the reference signal OCxRef is low as long as TIM1_CNT>TIM1_CCRx
else it becomes high. If the compare value in TIM1_CCRx is greater than the auto-reload
value in TIM1_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIM1_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals).
The compare flag is set when the counter counts up, when it counts down or both when it
counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIM1_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 159.
Figure 57 shows some center-aligned PWM waveforms in an example where:
● TIM1_ARR=8,
● PWM mode is the PWM mode 1,
● The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIM1_CR1 register.

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Figure 57. Center-aligned PWM waveforms (ARR=8)

COUNTER REGISTER 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

ocxref
CCRx=4
CCxIF

ocxref
CCRx=7
CCxIF

ocxref ‘1’
CCRx>=8
CCxIF

ocxref ‘0’
CCRx=0
CCxIF

Hints on using center-aligned mode:

● When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIM1_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
● Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIM1_CNT>TIM1_ARR). For example, if the counter was
counting up, it continues to count up.
– The direction is updated if you write 0 or write the TIM1_ARR value in the counter
but no Update Event UEV is generated.
● The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIM1_EGR register) just before starting the counter and not to
write the counter while it is running.

12.4.11 Complementary outputs and dead-time insertion

The Advanced Control Timer TIM1 can output two complementary signals and manage the
switching-off and the switching-on instants of the outputs.
This time is generally known as dead-time and you have to adjust it depending on the
devices you have connected to the outputs and their characteristics (intrinsic delays of level-
shifters, delays due to power switches...)
You can select the polarity of the outputs (main output OCx or complementary OCxN)
independently for each output. This is done by writing to the CCxP and CCxNP bits in the
TIM1_CCER register.
The complementary signals OCx and OCxN are activated by a combination of several
control bits: the CCxE and CCxNE bits in the TIM1_CCER register and the MOE, OISx,
OISxN, OSSI and OSSR bits in the TIM1_BDTR and TIM1_CR2 registers. Refer to
Table 37: Output control bits for complementary OCx and OCxN channels with break feature
on page 211 for more details. In particular, the dead-time is activated when switching to the
IDLE state (MOE falling down to 0).

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Dead-time insertion is enabled by setting both CCxE and CCxNE bits, and the MOE bit if the
break circuit is present. There is one 10-bit dead-time generator for each channel. From a
reference waveform OCxREF, it generates 2 outputs OCx and OCxN. If OCx and OCxN are
active high:
● The OCx output signal is the same as the reference signal except for the rising edge,
which is delayed relative to the reference rising edge.
● The OCxN output signal is the opposite of the reference signal except for the rising
edge, which is delayed relative to the reference falling edge.
If the delay is greater than the width of the active output (OCx or OCxN) then the
corresponding pulse is not generated.
The following figures show the relationships between the output signals of the dead-time
generator and the reference signal OCxREF. (we suppose CCxP=0, CCxNP=0, MOE=1,
CCxE=1 and CCxNE=1 in these examples)

Figure 58. Complementary output with dead-time insertion.

OCxREF

OCx
delay
OCxN
delay

Figure 59. Dead-Time waveforms with delay greater than the negative pulse.

OCxREF

OCx
delay
OCxN

Figure 60. Dead-Time waveforms with delay greater than the positive pulse.

OCxREF

OCx

OCxN

delay

The dead-time delay is the same for each of the channels and is programmable with the
DTG bits in the TIM1_BDTR register. Refer to Section 12.5.18: Break and dead-time
register (TIM1_BDTR) on page 216 for delay calculation.

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Re-directing OCxREF to OCx or OCxN

In output mode (forced, output compare or PWM), OCxREF can be re-directed to the OCx
output or to OCxN output by configuring the CCxE and CCxNE bits in the TIM1_CCER
register.
This allows you to send a specific waveform (such as PWM or static active level) on one
output while the complementary remains at its inactive level. Other alternative possibilities
are to have both outputs at inactive level or both outputs active and complementary with
dead-time.
Note: When only OCxN is enabled (CCxE=0, CCxNE=1), it is not complemented and becomes
active as soon as OCxREF is high. For example, if CCxNP=0 then OCxN=OCxRef. On the
other hand, when both OCx and OCxN are enabled (CCxE=CCxNE=1) OCx becomes
active when OCxREF is high whereas OCxN is complemented and becomes active when
OCxREF is low.

12.4.12 Using the break function

When using the break function, the output enable signals and inactive levels are modified
according to additional control bits (MOE, OSSI and OSSR bits in the TIM1_BDTR register,
OISx and OISxN bits in the TIM1_CR2 register). In any case, the OCx and OCxN outputs
cannot be set both to active level at a given time. Refer to Table 37: Output control bits for
complementary OCx and OCxN channels with break feature on page 211 for more details.
The break source can be either the break input pin or a clock failure event, generated by the
Clock Security System (CSS), from the Reset Clock Controller. For further information on
the Clock Security System, refer to Section 4.2.7: Clock security system (CSS) on page 51.
When exiting from reset, the break circuit is disabled and the MOE bit is low. You can enable
the break function by setting the BKE bit in the TIM1_BDTR register. The break input
polarity can be selected by configuring the BKP bit in the same register. BKE and BKP can
be modified at the same time.
Because MOE falling edge can be asynchronous, a resynchronization circuit has been
inserted between the actual signal (acting on the outputs) and the synchronous control bit
(accessed in the TIM1_BDTR register). It results in some delays between the asynchronous
and the synchronous signals. In particular, if you write MOE to 1 whereas it was low, you
must insert a delay (dummy instruction) before reading it correctly. This is because you write
the asynchronous signal and read the synchronous signal.
When a break occurs (selected level on the break input):
● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state
or in reset state (selected by the OSSI bit). This feature functions even if the MCU
oscillator is off.
● Each output channel is driven with the level programmed in the OISx bit in the
TIM1_CR2 register as soon as MOE=0. If OSSI=0 then the timer releases the enable
output else the enable output remains high.
● When complementary outputs are used:
– The outputs are first put in reset state inactive state (depending on the polarity).
This is done asynchronously so that it works even if no clock is provided to the
timer.
– If the timer clock is still present, then the dead-time generator is reactivated in
order to drive the outputs with the level programmed in the OISx and OISxN bits

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after a dead-time. Even in this case, OCx and OCxN cannot be driven to their
active level together. Note that because of the resynchronization on MOE, the
dead-time duration is a bit longer than usual (around 2 ck_tim clock cycles).
– If OSSI=0 then the timer releases the enable outputs else the enable outputs
remain or become high as soon as one of the CCxE or CCxNE bits is high.
● The break status flag (BIF bit in the TIM1_SR register) is set. An interrupt can be
generated if the BIE bit in the TIM1_DIER register is set. A DMA request can be sent if
the BDE bit in the TIM1_DIER register is set.
● If the AOE bit in the TIM1_BDTR register is set, the MOE bit is automatically set again
at the next update event UEV. This can be used to perform a regulation, for instance.
Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for
security and you can connect the break input to an alarm from power drivers, thermal
sensors or any security components.
Note: The break inputs is acting on level. Thus, the MOE cannot be set while the break input is
active (neither automatically nor by software). In the meantime, the status flag BIF cannot be
cleared.
The break can be generated by the BRK input which has a programmable polarity and an
enable bit BKE in the TIM1_BDTR Register.
In addition to the break input and the output management, a write protection has been
implemented inside the break circuit to safeguard the application. It allows you to freeze the
configuration of several parameters (dead-time duration, OCx/OCxN polarities and state
when disabled, OCxM configurations, break enable and polarity). You can choose from 3
levels of protection selected by the LOCK bits in the TIM1_BDTR register. Refer to
Section 12.5.18: Break and dead-time register (TIM1_BDTR) on page 216. The LOCK bits
can be written only once after an MCU reset.
The Figure 61 shows an example of behavior of the outputs in response to a break.

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Figure 61. Output behavior in response to a break.

BREAK (MOE )

OCxREF

OCx
(OCxN not implemented, CCxP=0, OISx=1)

OCx
(OCxN not implemented, CCxP=0, OISx=0)

OCx
(OCxN not implemented, CCxP=1, OISx=1)

OCx
(OCxN not implemented, CCxP=1, OISx=0)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=0, CCxNE=1, CCxNP=0, OISxN=1)

OCx

OCxN delay delay delay

(CCxE=1, CCxP=0, OISx=1, CCxNE=1, CCxNP=1, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=0, CCxNE=0, CCxNP=0, OISxN=1)

OCx

OCxN delay
(CCxE=1, CCxP=0, OISx=1, CCxNE=0, CCxNP=0, OISxN=0)

OCx

OCxN
(CCxE=1, CCxP=0, CCxNE=0, CCxNP=0, OISx=OISxN=0 or OISx=OISxN=1)

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12.4.13 Clearing the OCxREF signal on an external event

The OCxREF signal for a given channel can be driven Low by applying a High level to the
ETRF input (OCxCE enable bit of the corresponding TIM1_CCMRx register set to ‘1’). The
OCxREF signal remains Low until the next update event, UEV, occurs.
This function can only be used in output compare and PWM modes, and does not work in
forced mode.
For example, the OCxREF signal) can be connected to the output of a comparator to be
used for current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIM1_SMCR
register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIM1_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 62 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIM1 is programmed in
PWM mode.

Figure 62. Clearing TIM1 OCxREF

(CCRx)
counter (CNT)

ETRF

OCxREF
(OCxCE=’0’)

OCxREF
(OCxCE=’1’)

OCREF_CLR OCREF_CLR
becomes high still high

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12.4.14 6-step PWM generation

When complementary outputs are used on a channel, preload bits are available on the
OCxM, CCxE and CCxNE bits. The preload bits are transferred to the shadow bits at the
COM commutation event. Thus you can program in advance the configuration for the next
step and change the configuration of all the channels at the same time. COM can be
generated by software by setting the COM bit in the TIM1_EGR register or by hardware (on
TRGI rising edge).
A flag is set when the COM event occurs (COMIF bit in the TIM1_SR register), which can
generate an interrupt (if the COMIE bit is set in the TIM1_DIER register) or a DMA request
(if the COMDE bit is set in the TIM1_DIER register).
The Figure 63 describes the behavior of the OCx and OCxN outputs when a COM event
occurs, in 3 different examples of programmed configurations.

Figure 63. 6-step generation, COM example (OSSR=1)

(CCRx)
counter (CNT)

OCxREF

Write COM to 1

COM event

CCxE=1 Write CCxE to 0 CCxE=1

CCxNE=0 CCxNE=0
OCxM=110 (PWM1) OCxM=100
OCx
EXAMPLE 1
OCxN

CCxE=1 Write CCxNE to 1 CCxE=0

CCxNE=0 CCxNE=1
OCxM=100 (forced active) OCxM=101
OCx
EXAMPLE 2
OCxN

CCxE=1 Write CCxE and CxNE to 0 CCxE=1

CCxNE=1 CCxNE=0
OCxM=110 (PWM1) OCxM=100
OCx
EXAMPLE 3
OCxN

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12.4.15 One pulse mode

One Pulse Mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One Pulse Mode
by setting the OPM bit in the TIM1_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
In up-counting: CNT<CCRx≤ARR (in particular, 0<CCRx),
In down-counting: CNT>CCRx.

Figure 64. Example of one pulse mode.

TI2

OC1Ref

OC1

TIM1_ARR
COUNTER

TIM1_CCR1

0
tDELAY t
tPULSE

For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
● Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIM1_CCMR1 register.
● TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIM1_CCER register.
● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIM1_SMCR register.
● TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIM1_SMCR register
(trigger mode).

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The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
● The tDELAY is defined by the value written in the TIM1_CCR1 register.
● The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIM1_ARR - TIM1_CCR1).
● Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIM1_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIM1_CCMR1 register and ARPE in the TIM1_CR1 register. In this case you have to
write the compare value in the TIM1_CCR1 register, the auto-reload value in the
TIM1_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIM1_CR1 register should be low.
You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIM1_CR1 register to stop the
counter at the next update event (when the counter rolls over from the auto-reload value
back to 0).
Particular case: OCx fast enable:
In One Pulse Mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the
output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIM1_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

12.4.16 Encoder interface mode

To select Encoder Interface mode write SMS=‘001’ in the TIM1_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIM1_CCER
register. When needed, you can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 36. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIM1_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIM1_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIM1_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIM1_ARR before starting. in the same way, the capture, compare, prescaler,

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repetition counter, trigger output features continue to work as normal. Encoder mode and
External clock mode 2 are not compatible and must not be selected together.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.

Table 36. Counting direction versus encoder signals

Level on TI1FP1 signal TI2FP2 signal
opposite
Active Edge signal (TI1FP1
for TI2, TI2FP2 Rising Falling Rising Falling
for TI1)

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
The Figure 65 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are
selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
● CC1S=’01’ (TIMx_CCMR1 register, TI1FP1 mapped on TI1).
● CC2S=’01’ (TIMx_CCMR2 register, TI1FP2 mapped on TI2).
● CC1P=’0’ (TIMx_CCER register, TI1FP1 non-inverted, TI1FP1=TI1).
● CC2P=’0’ (TIMx_CCER register, TI1FP2 non-inverted, TI1FP2= TI2).
● SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
● CEN=’1’ (TIMx_CR1 register, Counter enabled).

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Figure 65. Example of counter operation in encoder interface mode.

forward jitter backward jitter forward

TI1

TI2

COUNTER

up down up

Figure 66 gives an example of counter behavior when TI1FP1 polarity is inverted (same
configuration as above except CC1P=’1’).

Figure 66. Example of encoder interface mode with TI1FP1 polarity inverted.
forward jitter backward jitter forward

TI1

TI2

COUNTER

down up down

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read
at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

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12.4.17 Timer input XOR function

The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1, TIMx_CH2 and
TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture. An example of this feature used to interface Hall sensors is given in Section 12.4.18
below.

12.4.18 Interfacing with Hall sensors

This is done using the Advanced Control Timer TIM1 timer to generate PWM signals to drive
the motor and another TIMx timer referred to as “interfacing timer” in Figure 67. The
“interfacing timer” captures the 3 timer input pins (CC1, CC2, CC3) connected through a
XOR to the TI1 input channel (selected by setting the TI1S bit in the TIMx_CR2 register).
The slave mode controller is configured in reset mode; the slave input is TI1F_ED. Thus,
each time one of the 3 inputs toggles, the counter restarts counting from 0. This creates a
time base triggered by any change on the Hall inputs.
On the “interfacing timer”, capture/compare channel 1 is configured in capture mode,
capture signal is TRC (See Figure 50: Capture/compare channel (example: channel 1 input
stage) on page 167). The captured value, which corresponds to the time elapsed between 2
changes on the inputs, gives information about motor speed.
The “interfacing timer” can be used in output mode to generate a pulse which changes the
configuration of the channels of the TIM1 timer (by triggering a COM event). The TIM1 timer
is used to generate PWM signals to drive the motor. To do this, the interfacing timer channel
must be programmed so that a positive pulse is generated after a programmed delay (in
output compare or PWM mode). This pulse is sent to the TIM1 timer through the TRGO
output.
Example: you want to change the PWM configuration of your Advanced Control Timer TIM1
timer after a programmed delay each time a change occurs on the Hall inputs connected to
one of the TIMx timers.
● Configure 3 timer inputs ORed to the TI1 input channel by writing the TI1S bit in the
TIMx_CR2 register to ‘1’,
● Program the time base: write the TIMx_ARR to the max value (the counter must be
cleared by the TI1 change. Set the prescaler to get a maximum counter period longer
than the time between 2 changes on the sensors,
● Program the channel 1 in capture mode (TRC selected): write the CC1S bits in the
TIMx_CCMR1 register to ‘01’. You can also program the digital filter if needed,
● Program the channel 2 in PWM 2 mode with the desired delay: write the OC2M bits to
‘111’ and the CC2S bits to ‘00’ in the TIM1_CCMR1 register,
● Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
register to ‘101’,
In the Advanced Control Timer TIM1 timer, the right ITR input must be selected as trigger
input, the timer is programmed to generate PWM signals, the capture/compare control
signals are preloaded (CCPC=1 in the TIM1_CR2 register) and the COM event is controlled
by the trigger input (CCUS=1 in the TIM1_CR2 register). The PWM control bits (CCxE,
OCxM) are written after a COM event for the next step (this can be done in an interrupt
subroutine generated by the rising edge of OC2REF).

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The Figure 67 describes this example.

Figure 67. Example of Hall sensor interface

TIH1

TIH2

TIH3
Interfacing Timer

counter (CNT)

(CCR2)

CCR1 C7A3 C7A8 C794 C7A5 C7AB C796

TRGO=OC2REF

COM

OC1

OC1N
TIM1 Timer

OC2

OC2N

OC3

OC3N

Write CCxE, CCxNE

and OCxM for next step

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12.4.19 Timers and external trigger synchronization

The TIM timers can be synchronized with an external trigger in several modes: Reset mode,
Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIM1_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIM1_ARR, TIM1_CCRx) are updated.
In the following example, the up-counter is cleared in response to a rising edge on TI1 input:
● Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIM1_CCMR1 register. Write
CC1P=0 in TIM1_CCER register to validate the polarity (and detect rising edges only).
● Configure the timer in reset mode by writing SMS=100 in TIM1_SMCR register. Select
TI1 as the input source by writing TS=101 in TIM1_SMCR register.
● Start the counter by writing CEN=1 in the TIM1_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIM1_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIM1_DIER register).
The following figure shows this behavior when the auto-reload register TIM1_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 68. Control circuit in reset mode

TI1

UG

COUNTER CLOCK = ck_cnt = ck_psc

COUNTER REGISTER 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the up-counter counts only when TI1 input is low:
● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIM1_CCMR1 register. Write
CC1P=1 in TIM1_CCER register to validate the polarity (and detect low level only).
● Configure the timer in gated mode by writing SMS=101 in TIM1_SMCR register. Select
TI1 as the input source by writing TS=101 in TIM1_SMCR register.
● Enable the counter by writing CEN=1 in the TIM1_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIM1_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 69. Control circuit in gated mode

TI1

cnt_en

COUNTER CLOCK = ck_cnt = ck_psc

COUNTER REGISTER 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

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UM0306 Advanced control timer (TIM1)

Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the up-counter starts in response to a rising edge on TI2 input:
● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are
configured to select the input capture source only, CC2S=01 in TIM1_CCMR1 register.
Write CC2P=1 in TIM1_CCER register to validate the polarity (and detect low level
only).
● Configure the timer in trigger mode by writing SMS=110 in TIM1_SMCR register.
Select TI2 as the input source by writing TS=110 in TIM1_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 70. Control circuit in trigger mode

TI2

cnt_en

COUNTER CLOCK = ck_cnt = ck_psc

COUNTER REGISTER 34 35 36 37 38

TIF

Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input (in reset mode, gated mode or
trigger mode). It is recommended not to select ETR as TRGI through the TS bits of
TIM1_SMCR register.
In the following example, the up-counter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:

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Advanced control timer (TIM1) UM0306

1. Configure the external trigger input circuit by programming the TIM1_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS=00: prescaler disabled
– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01in TIM1_CCMR1 register to select only the input capture source
– CC1P=0 in TIM1_CCER register to validate the polarity (and detect rising edge
only).
3. Configure the timer in trigger mode by writing SMS=110 in TIM1_SMCR register.
Select TI1 as the input source by writing TS=101 in TIM1_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 71. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 34 35 36

TIF

12.4.20 Timer synchronization

The TIM timers are linked together internally for timer synchronization or chaining. Refer to
Section 13.4.15: Timer synchronization on page 251 for details.

12.4.21 Debug mode

When the microcontroller enters debug mode (Cortex-M3 core halted), the TIM1 counter
either continues to work normally or stops, depending on DBG_TIM1_STOP configuration
bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and
watchdog and bxCAN.

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UM0306 Advanced control timer (TIM1)

12.5 TIM1 register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

12.5.1 Control register 1 (TIM1_CR1)

Address offset: 00h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved CKD[1:0] ARPE CMS[1:0] DIR OPM URS UDIS CEN

rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, always read as 0

CKD[1:0]: Clock division.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency
and the dead-time and sampling clock used by the dead-time generators and the
digital filters (ETR, TIx),
Bits 9:8 00: tDTS=tCK_INT
01: tDTS=2*tCK_INT
10: tDTS=4*tCK_INT
11: Reserved, do not program this value.
ARPE: Auto-reload preload enable.
Bit 7 0: TIM1_ARR register is not buffered.
1: TIM1_ARR register is buffered.
CMS[1:0]: Center-aligned mode selection.
00: Edge-aligned mode. The counter counts up or down depending on the direction
bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIM1_CCMRx
register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output
Bits 6:5
compare interrupt flags of channels configured in output (CCxS=00 in TIM1_CCMRx
register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIM1_CCMRx
register) are set both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as
long as the counter is enabled (CEN=1)
DIR: Direction.
0: Counter used as up-counter.
Bit 4 1: Counter used as down-counter.
Note: This bit is read only when the timer is configured in Center-aligned mode or
Encoder mode.
OPM: One pulse mode.
Bit 3 0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN).

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URS: Update request source.

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if
enabled. These events can be:
Bit 2 – Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
UDIS: Update disable.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following
events:
– Counter overflow/underflow
Bit 1 – Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their
value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if
the UG bit is set or if a hardware reset is received from the slave mode controller.
CEN: Counter enable.
0: Counter disabled
1: Counter enabled
Bit 0
Note: External clock, gated mode and encoder mode can work only if the CEN bit has
been previously set by software. However trigger mode can set the CEN bit
automatically by hardware.

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UM0306 Advanced control timer (TIM1)

12.5.2 Control register 2 (TIM1_CR2)

Address offset: 04h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Res. OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Res. CCPC

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, always read as 0

OIS4: Output Idle state 4 (OC4 output).
Bit 14
refer to OIS1 bit
OIS3N: Output Idle state 3 (OC3N output).
Bit 13
refer to OIS1N bit
OIS3: Output Idle state 3 (OC3 output).
Bit 12
refer to OIS1 bit
OIS2N: Output Idle state 2 (OC2N output).
Bit 11
refer to OIS1N bit
OIS2: Output Idle state 2 (OC2 output).
Bit 10
refer to OIS1 bit
OIS1N: Output Idle state 1 (OC1N output).
0: OC1N=0 after a dead-time when MOE=0
Bit 9 1: OC1N=1 after a dead-time when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIM1_BKR register).
OIS1: Output Idle state 1 (OC1 output).
0: OC1=0 (after a dead-time if OC1N is implemented) when MOE=0
Bit 8 1: OC1=1 (after a dead-time if OC1N is implemented) when MOE=0
Note: This bit can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIM1_BKR register).
TI1S: TI1 Selection.

Bit 7 0: The TIM1_CH1 pin is connected to TI1 input.

1: The TIM1_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR
combination)

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MMS[1:0]: Master Mode Selection.

These bits allow to select the information to be sent in master mode to slave timers
for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIM1_EGR register is used as trigger output
(TRGO). If the reset is generated by the trigger input (slave mode controller
configured in reset mode) then the signal on TRGO is delayed compared to the
actual reset.
001: Enable - the Counter Enable signal CNT_EN is used as trigger output (TRGO).
It is useful to start several timers at the same time or to control a window in which a
slave timer is enable. The Counter Enable signal is generated by a logic OR between
CEN control bit and the trigger input when configured in gated mode. When the
Bits 6:4 Counter Enable signal is controlled by the trigger input, there is a delay on TRGO,
except if the master/slave mode is selected (see the MSM bit description in
TIM1_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag
is to be set (even if it was already high), as soon as a capture or a compare match
occurred. (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
CCDS: Capture/Compare DMA Selection.
Bit 3 0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
CCUS: Capture/Compare Control Update Selection.
0: When capture/compare control bits are preloaded (CCPC=1), they are updated by
setting the COM bit only.
Bit 2
1: When capture/compare control bits are preloaded (CCPC=1), they are updated by
setting the COM bit or when an rising edge occurs on TRGI.
Note: This bit acts only on channels that have a complementary output.
Bit 1 Reserved, always read as 0
CCPC: Capture/Compare Preloaded Control.
0: CCxE, CCxNE and OCxM bits are not preloaded
Bit 0 1: CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are
updated only when COM bit is set.
Note: This bit acts only on channels that have a complementary output.

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UM0306 Advanced control timer (TIM1)

12.5.3 Slave mode control register (TIM1_SMCR)

Address offset: 08h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ETP: External trigger polarity.

Bit 15 This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
ECE: External clock enable.
This bit enables External clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge on the
ETRF signal.
Bit 14 Note 1: Setting the ECE bit has the same effect as selecting external clock mode 1
with TRGI connected to ETRF (SMS=111 and TS=111).
Note 2: It is possible to simultaneously use external clock mode 2 with the following
slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not
be connected to ETRF in this case (TS bits must not be 111).
Note 3: If external clock mode 1 and external clock mode 2 are enabled at the same
time, the external clock input is ETRF.
ETPS[1:0]: External trigger prescaler.
External trigger signal ETRP frequency must be at most 1/4 of TIM1CLK frequency.
A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting
fast external clocks.
Bits 13:12
00: Prescaler OFF.
01: ETRP frequency divided by 2.
10: ETRP frequency divided by 4.
11: ETRP frequency divided by 8.

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ETF[3:0]: External trigger filter.

This bit-field then defines the frequency used to sample ETRP signal and the length
of the digital filter applied to ETRP. The digital filter is made of an event counter in
which N events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS.
0001: fSAMPLING=fCK_INT, N=2.
0010: fSAMPLING=fCK_INT, N=4.
0011: fSAMPLING=fCK_INT, N=8.
0100: fSAMPLING=fDTS/2, N=6.
0101: fSAMPLING=fDTS/2, N=8.
Bits 11:8
0110: fSAMPLING=fDTS/4, N=6.
0111: fSAMPLING=fDTS/4, N=8.
1000: fSAMPLING=fDTS/8, N=6.
1001: fSAMPLING=fDTS/8, N=8.
1010: fSAMPLING=fDTS/16, N=5.
1011: fSAMPLING=fDTS/16, N=6.
1100: fSAMPLING=fDTS/16, N=8.
1101: fSAMPLING=fDTS/32, N=5.
1110: fSAMPLING=fDTS/32, N=6.
1111: fSAMPLING=fDTS/32, N=8.

MSM: Master/slave mode.

0: No action
Bit 7 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful
if we want to synchronize several timers on a single external event.
TS[2:0]: Trigger selection.
This bit-field selects the trigger input to be used to synchronize the counter. Refer to
the product specification to see the connection of the internal inputs.
000: Reserved
001: TIM2 (ITR1)
010: TIM3 (ITR2)
Bits 6:4 011: TIM4 (ITR3)
100: TI1 Edge Detector (TI1F_ED)
101: Filtered Timer Input 1 (TI1FP1)
110: Filtered Timer Input 2 (TI2FP2)
111: External Trigger input (ETRF)
Note: These bits must be changed only when they are not used (e.g. when SMS=000)
to avoid wrong edge detections at the transition.

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Bit 3 Reserved, always read as 0.

SMS Slave mode selection.
When external signals are selected the active edge of the trigger signal (TRGI) is
linked to the polarity selected on the external input (see Input Control register and
Control Register description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the
internal clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on
TI1FP1 level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on
TI2FP2 level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
Bits 2:0
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the
counter and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is
high. The counter stops (but is not reset) as soon as the trigger becomes low. Both
start and stop of the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is
not reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the
counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.

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12.5.4 DMA/Interrupt enable register (TIM1_DIER)

Address offset: 0Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COMD CC4D CC3D CC2D CC1D COMI
Res. TDE UDE BIE TIE CC4IE CC3IE CC2IE CC1IE UIE
E E E E E E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, always read as 0.

TDE: Trigger DMA request enable.
Bit 14 0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
COMDE: COM DMA request enable.
Bit 13 0: COM DMA request disabled.
1: COM DMA request enabled.
CC4DE: Capture/Compare 4 DMA request enable.
Bit 12 0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
CC3DE: Capture/Compare 3 DMA request enable.
Bit 11 0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
CC2DE: Capture/Compare 2 DMA request enable.
Bit 10 0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
CC1DE: Capture/Compare 1 DMA request enable.
Bit 9 0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
UDE: Update DMA request enable.
Bit 8 0: Update DMA request disabled.
1: Update DMA request enabled.
BIE: Break interrupt enable.
Bit 7 0: Break interrupt disabled.
1: Break interrupt enabled.
TIE: Trigger interrupt enable.
Bit 6 0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
COMIE: COM interrupt enable.
Bit 5 0: COM interrupt disabled.
1: COM interrupt enabled.
CC4IE: Capture/Compare 4 interrupt enable.
Bit 4 0: CC4 interrupt disabled.
1: CC4 interrupt enabled.

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CC3IE: Capture/Compare 3 interrupt enable.

Bit 3 0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
CC2IE: Capture/Compare 2 interrupt enable.
Bit 2 0: CC2 interrupt disabled.
1: CC2 interrupt enabled.
CC1IE: Capture/Compare 1 interrupt enable.
Bit 1 0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
UIE: Update interrupt enable.
Bit 0 0: Update interrupt disabled.
1: Update interrupt enabled.

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12.5.5 Status register (TIM1_SR)

Address offset: 10h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4O CC3O CC2O CC1O
Reserved Res. BIF TIF COMIF CC4IF CC3IF CC2IF CC1IF UIF
F F F F
rc rc rc rc rc rc rc rc rc rc rc rc

Bit 15:13 Reserved, always read as 0.

CC4OF: Capture/Compare 4 Overcapture Flag.
Bit 12
refer to CC1OF description
CC3OF: Capture/Compare 3 Overcapture Flag.
Bit 11
refer to CC1OF description
CC2OF: Capture/Compare 2 Overcapture Flag.
Bit 10
refer to CC1OF description
CC1OF: Capture/Compare 1 Overcapture Flag.
This flag is set by hardware only when the corresponding channel is configured in
Bit 9 input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIM1_CCR1 register while CC1IF flag
was already set
Bit 8 Reserved, always read as 0.
BIF: Break interrupt Flag.
This flag is set by hardware as soon as the break input goes active. It can be cleared
Bit 7 by software if the break input is not active.
0: No break event occurred.
1: An active level has been detected on the break input.
TIF: Trigger interrupt Flag.
This flag is set by hardware on trigger event (active edge detected on TRGI input
Bit 6 when the slave mode controller is enabled in all modes but gated mode, both edges
in case gated mode is selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.
COMIF: COM interrupt Flag.
This flag is set by hardware on COM event (when Capture/compare Control bits -
Bit 5 CCxE, CCxNE, OCxM - have been updated). It is cleared by software.
0: No COM event occurred.
1: COM interrupt pending.
CC4IF: Capture/Compare 4 interrupt Flag.
Bit 4
refer to CC1IF description
CC3IF: Capture/Compare 3 interrupt Flag.
Bit 3
refer to CC1IF description
CC2IF: Capture/Compare 2 interrupt Flag.
Bit 2
refer to CC1IF description

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CC1IF: Capture/Compare 1 interrupt Flag.

If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with
some exception in center-aligned mode (refer to the CMS bits in the TIM1_CR1
register description). It is cleared by software.
0: No match.
1: The content of the counter TIM1_CNT has matched the content of the
Bit 1
TIM1_CCR1 register.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIM1_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIM1_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity).
UIF: Update interrupt Flag.
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are
updated:
Bit 0 – At overflow or underflow regarding the repetition down-counter value (update if
REP_CNT=0) and if the UDIS=0 in the TIM1_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIM1_EGR register, if
URS=0 and UDIS=0 in the TIM1_CR1 register.
– When CNT is reinitialized by a trigger event (refer to Section 12.5.3: Slave mode
control register (TIM1_SMCR)), if URS=0 and UDIS=0 in the TIM1_CR1 register.

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12.5.6 Event generation register (TIM1_EGR)

Address offset: 14h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved BG TG COM CC4G CC3G CC2G CC1G UG

w w w w w w w w

Bits 15:8 Reserved, always read as 0.

BG: Break Generation.
This bit is set by software in order to generate an event, it is automatically cleared by
Bit 7 hardware.
0: No action.
1: A break event is generated. MOE bit is cleared and BIF flag is set. Related
interrupt or DMA transfer can occur if enabled.
TG: Trigger Generation.
This bit is set by software in order to generate an event, it is automatically cleared by
Bit 6 hardware.
0: No action.
1: The TIF flag is set in TIM1_SR register. Related interrupt or DMA transfer can
occur if enabled.
COM: Capture/Compare Control Update Generation.
This bit can be set by software, it is automatically cleared by hardware
Bit 5 0: No action
1: When CCPC bit is set, it allows to update CCxE, CCxNE and OCxM bits
Note: This bit acts only on channels having a complementary output.
CC4G: Capture/Compare 4 Generation.
Bit 4
refer to CC1G description
CC3G: Capture/Compare 3 Generation.
Bit 3
refer to CC1G description
CC2G: Capture/Compare 2 Generation.
Bit 2
refer to CC1G description

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CC1G: Capture/Compare 1 Generation.

This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
Bit 1 If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIM1_CCR1 register. The CC1IF flag
is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF
flag is set if the CC1IF flag was already high.
UG: Update Generation.
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
Bit 0 1: Re-initialize the counter and generates an update of the registers. Note that the
prescaler counter is cleared too (anyway the prescaler ratio is not affected). The
counter is cleared if the center-aligned mode is selected or if DIR=0 (up-counting),
else it takes the auto-reload value (TIM1_ARR) if DIR=1 (down-counting).

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12.5.7 Capture/compare mode register 1 (TIM1_CCMR1)

Address offset: 18h
Reset value: 0000h
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2 OC2 OC2 OC1 OC1 OC1
OC2M[2:0] OC1M[2:0]
CE PE FE CC2S[1:0] CE PE FE CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode:

Bit 15 OC2CE: Output Compare 2 Clear Enable
Bits 14:12 OC2M[2:0]: Output Compare 2 Mode.
Bit 11 OC2PE: Output Compare 2 Preload enable.
Bit 10 OC2FE: Output Compare 2 Fast enable.
CC2S[1:0]: Capture/Compare 2 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
Bits 9:8 10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in
TIM1_CCER).
OC1CE: Output Compare 1Clear Enable
OC1CE: Output Compare 1 Clear Enable
Bit 7
0: OC1Ref is not affected by the ETRF Input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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UM0306 Advanced control timer (TIM1)

OC1M: Output Compare 1 Mode.

These bits define the behavior of the output reference signal OC1REF from which
OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active
level depends on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIM1_CCR1 and
the counter TIM1_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIM1_CNT matches the capture/compare register 1 (TIM1_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIM1_CNT matches the capture/compare register 1 (TIM1_CCR1).
011: Toggle - OC1REF toggles when TIM1_CNT=TIM1_CCR1.
100: Force inactive level - OC1REF is forced low.
Bits 6:4 101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In up-counting, channel 1 is active as long as
TIM1_CNT<TIM1_CCR1 else inactive. In down-counting, channel 1 is inactive
(OC1REF=‘0’) as long as TIM1_CNT>TIM1_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In up-counting, channel 1 is inactive as long as
TIM1_CNT<TIM1_CCR1 else active. In down-counting, channel 1 is active as long
as TIM1_CNT>TIM1_CCR1 else inactive.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIM1_BDTR register) and CC1S=’00’ (the channel is configured in
output).
Note 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
OC1PE: Output Compare 1 Preload enable.
0: Preload register on TIM1_CCR1 disabled. TIM1_CCR1 can be written at anytime,
the new value is taken in account immediately.
1: Preload register on TIM1_CCR1 enabled. Read/Write operations access the
preload register. TIM1_CCR1 preload value is loaded in the active register at each
Bit 3 update event.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIM1_BDTR register) and CC1S=’00’ (the channel is configured in
output).
Note 2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIM1_CR1 register). Else the behavior is not guaranteed.

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OC1FE: Output Compare 1 Fast enable.

This bit is used to accelerate the effect of an event on the trigger in input on the CC
output.
0: CC1 behaves normally depending on counter and CCR1 values even when the
trigger is ON. The minimum delay to activate CC1 output when an edge occurs on
Bit 2 the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output.
Then, OC is set to the compare level independently from the result of the
comparison. Delay to sample the trigger input and to activate CC1 output is reduced
to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2
mode.
CC1S: Capture/Compare 1 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
Bits 1:0 10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in
TIM1_CCER).

Input capture mode

Bits 15:12 IC2F: Input Capture 2 Filter.
Bits 11:10 IC2PSC[1:0]: Input Capture 2 Prescaler.
CC2S: Capture/Compare 2 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
Bits 9:8 10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in
TIM1_CCER).

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IC1F[3:0]: Input Capture 1 Filter.

This bit-field defines the frequency used to sample TI1 input and the length of the
digital filter applied to TI1. The digital filter is made of an event counter in which N
events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS.
0001: fSAMPLING=fCK_INT, N=2.
0010: fSAMPLING=fCK_INT, N=4.
0011: fSAMPLING=fCK_INT, N=8.
0100: fSAMPLING=fDTS/2, N=6.
0101: fSAMPLING=fDTS/2, N=8.
Bits 7:4
0110: fSAMPLING=fDTS/4, N=6.
0111: fSAMPLING=fDTS/4, N=8.
1000: fSAMPLING=fDTS/8, N=6.
1001: fSAMPLING=fDTS/8, N=8.
1010: fSAMPLING=fDTS/16, N=5.
1011: fSAMPLING=fDTS/16, N=6.
1100: fSAMPLING=fDTS/16, N=8.
1101: fSAMPLING=fDTS/32, N=5.
1110: fSAMPLING=fDTS/32, N=6.
1111: fSAMPLING=fDTS/32, N=8.

IC1PSC: Input Capture 1 Prescaler.

This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIM1_CCER register).
Bits 3:2 00: no prescaler, capture is done each time an edge is detected on the capture input.
01: capture is done once every 2 events.
10: capture is done once every 4 events.
11: capture is done once every 8 events.
CC1S: Capture/Compare 1 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
Bits 1:0 10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in
TIM1_CCER).

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12.5.8 Capture/compare mode register 2 (TIM1_CCMR2)

Address offset: 1Ch
Reset value: 0000h
Refer to the above CCMR1 register description.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4 OC4 OC4 OC3 OC3 OC3
OC4M[2:0] OC3M[2:0]
CE PE FE CC4S[1:0] CE. PE FE CC3S[1:0]
IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output Compare mode

Bit 15 OC4CE: Output Compare 4 Clear Enable
Bits 14:12 OC4M: Output Compare 4 Mode.
Bit 11 OC4PE: Output Compare 4 Preload enable.
Bit 10 OC4FE: Output Compare 4 Fast enable.
CC4S: Capture/Compare 4 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
Bits 9:8 10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in
TIM1_CCER).
Bit 7 OC3CE: Output Compare 3 Clear Enable
Bits 6:4 OC3M: Output Compare 3 Mode.
Bit 3 OC3PE: Output Compare 3 Preload enable.
Bit 2 OC3FE: Output Compare 3 Fast enable.
CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
Bits 1:0 10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in
TIM1_CCER).

Input capture mode

Bits 15:12 IC4F: Input Capture 4 Filter.
Bits 11:10 IC4PSC: Input Capture 4 Prescaler.

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CC4S: Capture/Compare 4 Selection.

This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
Bits 9:8 10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in
TIM1_CCER).
Bits 7:4 IC3F: Input Capture 3 Filter.
Bits 3:2 IC3PSC: Input Capture 3 Prescaler.
CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
Bits 1:0 10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIM1_SMCR
register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in
TIM1_CCER).

12.5.9 Capture/compare enable register (TIM1_CCER)

Address offset: 20h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC3N CC3N CC2N CC2N CC1N CC1N
Reserved CC4P CC4E CC3P CC3E CC2P CC2E CC1P CC1E
P E P E P E
rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:14 Reserved, always read as 0.

CC4P: Capture/Compare 4 output Polarity.
Bit 13
refer to CC1P description
CC4E: Capture/Compare 4 output enable.
Bit 12
refer to CC1E description
CC3NP: Capture/Compare 3 Complementary output Polarity.
Bit 11
refer to CC1NP description
CC3NE: Capture/Compare 3 Complementary output enable.
Bit 10
refer to CC1NE description
CC3P: Capture/Compare 3 output Polarity.
Bit 9
refer to CC1P description
CC3E: Capture/Compare 3 output enable.
Bit 8
refer to CC1E description

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CC2NP: Capture/Compare 2 Complementary output Polarity.

Bit 7
refer to CC1NP description
CC2NE: Capture/Compare 2 Complementary output enable.
Bit 6
refer to CC1NE description
CC2P: Capture/Compare 2 output Polarity.
Bit 5
refer to CC1P description
CC2E: Capture/Compare 2 output enable.
Bit 4
refer to CC1E description
CC1NP: Capture/Compare 1 Complementary output Polarity.
0: OC1N active high.
1: OC1N active low.
Bit 3
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed
(LOCK bits in TIM1_BDTR register) and CC1S=”00” (the channel is configured in
output).
CC1NE: Capture/Compare 1 Complementary output enable.
0: Off - OC1N is not active. OC1N level is then function of MOE, OSSI, OSSR, OIS1,
Bit 2 OIS1N and CC1E bits.
1: On - OC1N signal is output on the corresponding output pin depending on MOE,
OSSI, OSSR, OIS1, OIS1N and CC1E bits.
CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
CC1 channel configured as input:
This bit selects whether IC1 or IC1 is used for trigger or capture operations.
Bit 1
0: non-inverted: capture is done on a rising edge of IC1. When used as external
trigger, IC1 is non-inverted.
1: inverted: capture is done on a falling edge of IC1. When used as external trigger,
IC1 is inverted.
Note: This bit is not writable as soon as LOCK level 2 or 3 has been programmed
(LOCK bits in TIM1_BDTR register).
CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active. OC1 level is then function of MOE, OSSI, OSSR, OIS1,
OIS1N and CC1NE bits.
1: On - OC1 signal is output on the corresponding output pin depending on MOE,
Bit 0 OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the
input capture/compare register 1 (TIM1_CCR1) or not.
0: Capture disabled.
1: Capture enabled.

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Table 37. Output control bits for complementary OCx and OCxN channels with
break feature
Control bits Output states
MOE OSSI OSSR CCxE CCxNE
OCx Output State OCxN Output State
bit bit bit bit bit
Output Disabled (not Output Disabled (not
0 0 0 driven by the timer) driven by the timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0

Output Disabled (not OCxREF + Polarity

0 0 1 driven by the timer) OCxN=OCxREF xor CCxNP,
OCx=CCxP, OCx_EN=0 OCxN_EN=1

OCxREF + Polarity Output Disabled (not

0 1 0 OCx=OCxREF xor CCxP, driven by the timer)
OCx_EN=1 OCxN=CCxNP, OCxN_EN=0

Complementary to
OCREF + Polarity +
OCREF (not OCREF) +
0 1 1 dead-time
Polarity + dead-time
OCx_EN=1
OCxN_EN=1

1 X Output Disabled (not Output Disabled (not

1 0 0 driven by the timer) driven by the timer)
OCx=CCxP, OCx_EN=0 OCxN=CCxNP, OCxN_EN=0

Off-State (output
enabled with inactive OCxREF + Polarity
1 0 1 OCxN=OCxREF xor CCxNP,
state)
OCxN_EN=1
OCx=CCxP, OCx_EN=1

Off-State (output
OCxREF + Polarity
enabled with inactive
1 1 0 OCx=OCxREF xor CCxP,
state)
OCx_EN=1
OCxN=CCxNP, OCxN_EN=1

Complementary to
OCREF + Polarity +
OCREF (not OCREF) +
1 1 1 dead-time
Polarity + dead-time
OCx_EN=1
OCxN_EN=1

0 0 0
Output Disabled (not driven by the timer)
0 0 1
Asynchronously: OCx=CCxP, OCx_EN=0, OCxN=CCxNP,
0 1 0 OCxN_EN=0
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
0 1 1 dead-time, assuming that OISx and OISxN don’t correspond to
OCX and OCxN both to active state.
0 1 X 0 0
1 0 1 Off-State (output enabled with inactive state)
Asynchronously: OCx=CCxP, OCx_EN=1, OCxN=CCxNP,
1 1 0 OCxN_EN=1
Then if the clock is present: OCx=OISx and OCxN=OISxN after a
1 1 1 dead-time, assuming that OISx and OISxN don’t correspond to
OCX and OCxN both to active state

Note: The state of the external I/O pins connected to the complementary OCx and
OCxN channels depends on the OCx and OCxN channel state and the GPIO and
AFIO registers.

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Advanced control timer (TIM1) UM0306

12.5.10 Counter (TIM1_CNT)

Address offset: 24h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter Value.

12.5.11 Prescaler (TIM1_PSC)

Address offset: 28h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PSC[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

PSC[15:0]: Prescaler Value.

The counter clock frequency (CK_CNT) is equal to fCK_PSC / (PSC[15:0] + 1).
Bits 15:0 PSC contains the value to be loaded in the active prescaler register at each update
event (including when the counter is cleared through UG bit of TIM1_EGR register or
through trigger controller when configured in “reset mode”).

12.5.12 Auto-reload register (TIM1_ARR)

Address offset: 2Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ARR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ARR[15:0]: Prescaler Value.

ARR is the value to be loaded in the actual auto-reload register.
Bits 15:0 Refer to the Section 12.4.1: Time base unit on page 153 for more details about ARR
update and behavior.
The counter is blocked while the auto-reload value is null.

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UM0306 Advanced control timer (TIM1)

12.5.13 Repetition counter register (TIM1_RCR)

Address offset: 30h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved REP[7:0]

rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, always read as 0.

REP[7:0]: Repetition Counter Value.
These bits allow the user to set-up the update rate of the compare registers (i.e.
periodic transfers from preload to active registers) when preload registers are enable,
as well as the update interrupt generation rate, if this interrupt is enable.
Each time the REP_CNT related down-counter reaches zero, an update event is
Bits 7:0 generated and it restarts counting from REP value. As REP_CNT is reloaded with REP
value only at the repetition update event U_RC, any write to the TIM1_RCR register is
not taken in account until the next repetition update event.
It means in PWM mode (REP+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode.

12.5.14 Capture/compare register 1 (TIM1_CCR1)

Address offset: 34h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR1[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR1[15:0]: Capture/Compare 1 Value).

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIM1_CCMR1
Bits 15:0 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM1_CNT and signaled on OC1 output.

If channel CC1 is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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12.5.15 Capture/compare register 2 (TIM1_CCR2)

Address offset: 38h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR2[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR2[15:0]: Capture/Compare 2 Value.

If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIM1_CCMR2
Bits 15:0 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM1_CNT and signalled on OC2 output.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (IC2).

12.5.16 Capture/compare register 3 (TIM1_CCR3)

Address offset: 3Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR3[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR3[15:0]: Capture/Compare Value.

If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIM1_CCMR3
Bits 15:0 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM1_CNT and signalled on OC3 output.

If channel CC3 is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (IC3).

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12.5.17 Capture/compare register 4 (TIM1_CCR4)

Address offset: 40h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR4[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR4[15:0]: Capture/Compare Value.

If channel CC4 is configured as output:
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIM1_CCMR4
Bits 15:0 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIM1_CNT and signalled on OC4 output.

If channel CC4 is configured as input:

CCR4 is the counter value transferred by the last input capture 4 event (IC4).

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12.5.18 Break and dead-time register (TIM1_BDTR)

Address offset: 44h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MOE AOE BKP BKE OSSR OSSI LOCK[1:0] DTG[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

MOE: Main Output enable.

This bit is cleared asynchronously by hardware as soon as the break input is active.
It is set by software or automatically depending on the AOE bit. It is acting only on
the channels which are configured in output.
Bit 15 0: OC and OCN outputs are disabled or forced to idle state.
1: OC and OCN outputs are enabled if their respective enable bits are set (CCxE,
CCxNE in TIM1_CCER register).
See OC/OCN enable description for more details (Section 12.5.9: Capture/compare
enable register (TIM1_CCER) on page 209).
AOE: Automatic Output enable.
0: MOE can be set only by software
1: MOE can be set by software or automatically at the next update event (if the break
Bit 14
input is not be active)
Note: This bit can not be modified as long as LOCK level 1 has been programmed
(LOCK bits in TIM1_BDTR register).
BKP: Break Polarity.
0: Break input BRK is active low
Bit 13 1: Break input BRK is active high
Note: This bit can not be modified as long as LOCK level 1 has been programmed
(LOCK bits in TIM1_BDTR register).
BKE: Break enable.
0: Break inputs (BRK and BRK_ACTH) disabled
Bit 12 1; Break inputs (BRK and BRK_ACTH) enabled
Note: This bit can not be modified as long as LOCK level 1 has been programmed
(LOCK bits in TIM1_BDTR register).
OSSR: Off-State Selection for Run mode.
This bit is used when MOE=1 on channels having a complementary output which are
configured as outputs. OSSR is not implemented if no complementary output is
implemented in the timer.
See OC/OCN enable description for more details (Section 12.5.9: Capture/compare
Bit 11 enable register (TIM1_CCER) on page 209).
0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are enabled with their inactive level as soon as
CCxE=1 or CCxNE=1. Then, OC/OCN enable output signal=1
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed
(LOCK bits in TIM1_BDTR register).

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OSSI: Off-State Selection for Idle mode.

This bit is used when MOE=0 on channels configured as outputs.
See OC/OCN enable description for more details (Section 12.5.9: Capture/compare
enable register (TIM1_CCER) on page 209).
Bit 10 0: When inactive, OC/OCN outputs are disabled (OC/OCN enable output signal=0).
1: When inactive, OC/OCN outputs are forced first with their idle level as soon as
CCxE=1 or CCxNE=1. OC/OCN enable output signal=1)
Note: This bit can not be modified as soon as the LOCK level 2 has been programmed
(LOCK bits in TIM1_BDTR register).
LOCK[1:0]: Lock Configuration.
These bits offer a write protection against software errors.
00: LOCK OFF - No bit is write protected.
01: LOCK Level 1 = DTG bits in TIM1_BDTR register, OISx and OISxN bits in
TIM1_CR2 register and BKE/BKP/AOE bits in TIM1_BDTR register can no longer be
written.
10: LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in
Bits 9:8
TIM1_CCER register, as long as the related channel is configured in output through
the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
11: LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in
TIM1_CCMRx registers, as long as the related channel is configured in output
through the CCxS bits) can no longer be written.
Note: The LOCK bits can be written only once after the reset. Once the TIM1_BDTR
register has been written, their content is frozen until the next reset.
DTG[7:0]: Dead-Time Generator set-up.
This bit-field defines the duration of the dead-time inserted between the
complementary outputs. DT correspond to this duration.
DTG[7:5]=0xx => DT=DTG[7:0]x tdtg with tdtg=tDTS.
DTG[7:5]=10x => DT=(64+DTG[5:0])xtdtg with Tdtg=2xtDTS.
DTG[7:5]=110 => DT=(32+DTG[4:0])xtdtg with Tdtg=8xtDTS.
Bits 7:0 DTG[7:5]=111 => DT=(32+DTG[4:0])xtdtg with Tdtg=16xtDTS.
Example if TDTS=125ns (8MHz), dead-time possible values are:
0 to 15875 ns by 125 ns steps,
16 us to 31750 ns by 250 ns steps,
32 us to 63us by 1 us steps,
64 us to 126 us by 2 us steps
Note: This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
programmed (LOCK bits in TIM1_BDTR register).

Note: As the bits AOE, BKP, BKE, OSSI, OSSR and DTG[7:0] can be write-locked depending on
the LOCK configuration, it can be necessary to configure all of them during the first write
access to the TIM1_BDTR register.

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12.5.19 DMA control register (TIM1_DCR)

Address offset: 48h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved DBL[4:0] Reserved DBA[4:0]

rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, always read as 0

DBL[4:0]: DMA Burst Length.
This 5-bit vector defines the length of DMA transfers in burst mode (the timer
recognizes a burst transfer when a read or a write access is done to the TIM1_DMAR
address), i.e. the number of bytes to be transferred.
Bits 12:8 00000: 1 byte,
00001: 2 bytes,
00010: 3 bytes,
...
10001: 18 bytes.
Bits 7:5 Reserved, always read as 0
DBA[4:0]: DMA Base Address.
This 5-bits vector defines the base-address for DMA transfers in burst mode (when
read/write access are done through the TIM1_DMAR address). DBA is defined as an
offset starting from the address of the TIM1_CR1 register.
Bits 4:0 Example:
00000: TIM1_CR1,
00001: TIM1_CR2,
00010: TIM1_SMCR,
...

12.5.20 DMA address for burst mode (TIM1_DMAR)

Address offset: 4Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMAB[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

DMAB[15:0]: DMA register for burst accesses.

A read or write access to the DMAR register accesses the register located at the
address:
“(TIM1_CR1 address) + DBA + (DMA index)” in which:
Bits 15:0
TIM1_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in TIM1_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on
the length of the transfer DBL in the TIM1_DCR register.

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UM0306 Advanced control timer (TIM1)

12.6 TIM1 register map

TIM1 registers are mapped as 16-bit addressable registers as described in the table below:
Table 38. TIM1 - Register Map and Reset Values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
ARPE

UDIS
OPM
CKD CMS

CEN
URS
DIR
TIM1_CR1
00h Reserved [1:0] [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0

Reserved
OIS3N

OIS2N

OIS1N

CCPC
CCDS
CCUS
OIS4

OIS3

OIS2

OIS1
TI1S
TIM1_CR2 MMS[2:0]
04h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC3IE Reserved
MSM
ETPS

ECE
ETP
TIM1_SMCR ETF[3:0] TS[2:0] SMS[2:0]
08h Reserved [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

COMDE
CC4DE
CC3DE
CC2DE
CC1DE

COMIE
CC4IE

CC2IE
CC1IE
UDE
TDE

UIE
BIE
TIE
TIM1_DIER
0Ch Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC4OF
CC3OF
CC2OF
CC1OF

COMIF
Reserved

CC4IF
CC3IF
CC2IF
CC1IF
UIF
BIF
TIF
TIM1_SR
10h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

CC4G
CC3G
CC2G
CC1G
COM

UG
BG
TG
TIM1_EGR
14h Reserved
Reset Value 0 0 0 0 0 0 0 0
TIM1_CCMR1
OC2CE

OC1CE
OC2PE

OC1PE
OC2FE

OC1FE
OC2M CC2S OC1M CC1S
Output Compare
Reserved [2:0] [1:0] [2:0] [1:0]
mode
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18h
TIM1_CCMR1 IC2 IC1
CC2S CC1S
Input Capture IC2F[3:0] PSC IC1F[3:0] PSC
Reserved [1:0] [1:0]
mode [1:0] [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIM1_CCMR2 OC3CE
OC4PE

OC3PE
OC4FE

OC3FE
O24CE

OC4M CC4S OC3M CC3S

Output Compare
Reserved [2:0] [1:0] [2:0] [1:0]
mode
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1Ch
TIM1_CCMR2 IC4 IC3
CC4S CC3S
Input Capture IC4F[3:0] PSC IC3F[3:0] PSC
Reserved [1:0] [1:0]
mode [1:0] [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CC3NP
CC3NE

CC2NP
CC2NE

CC1NP
CC1NE
CC4P
CC4E

CC3P
CC3E

CC2P
CC2E

CC1P
CC1E
TIM1_CCER
20h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CNT CNT[15:0]
24h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_PSC PSC[15:0]
28h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_ARR ARR[15:0]
2Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_RCR REP[7:0]
30h Reserved
Reset Value 0 0 0 0 0 0 0 0

TIM1_CCR1 CCR1[15:0]
34h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 38. TIM1 - Register Map and Reset Values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
TIM1_CCR2 CCR2[15:0]
38h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CCR3 CCR3[15:0]
3Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_CCR4 CCR4[15:0]
40h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OSSR
OSSI
MOE
LOCK

AOE
BKP
BKE
TIM1_BDTR DT[7:0]
44h Reserved [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIM1_DCR DBL[4:0] DBA[4:0]

48h Reserved Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0

TIM1_DMAR DMAB[15:0]
4Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 General purpose timer (TIMx)

13 General purpose timer (TIMx)

13.1 Introduction
The General purpose timers consist of a 16-bit auto-reload counter driven by a
programmable prescaler.
They may be used for a variety of purposes, including measuring the pulse lengths of input
signals (input capture) or generating output waveforms (output compare and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the RCC clock controller prescalers.
The timers are completely independent, and do not share any resources. They can be
synchronized together as described in Section 13.4.15.

13.2 Main features

General purpose TIMx timer features include:
● 16-bit up, down, up/down auto-reload counter.
● 16-bit programmable prescaler allowing dividing (also “on the fly”) the counter clock
frequency either by any factor between 1 and 65535.
● Up to 4 independent channels for:
– Input Capture
– Output Compare
– PWM generation (Edge and Center-aligned Mode)
– One Pulse Mode output
● Synchronization circuit to control the timer with external signals and to interconnect
several timers between them.
● Interrupt/DMA generation on the following events:
– Update: counter overflow/underflow, counter initialization (by software or
internal/external trigger)
– Trigger event (counter start, stop, initialization or count by internal/external trigger
– Input capture
– Output compare

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13.3 Block diagram

Figure 72. General purpose timer block diagram

Internal Clock (CK_INT)

TIMXCLK from RCC
ETRF
ETRP
ETR Polarity Selection & Edge
TIMx_ETR Input Filter
Detector & Prescaler
TRGO
TIM1 (ITR0)
Trigger
TIM2 (ITR1) ITR
TGI Controller to other timers
TIM3 (ITR2) TRC TRGI
TIM4 (ITR3) Slave
Reset, Enable, Up/Down, Count,
Mode
TI1F_ED Controller

TI1FP1 Encoder
TI2FP2 Interface

U AutoReload Register UI

Stop, Clear or Up/Down

U
CK_PSC PSC CK_CNT +/- CNT
Prescaler COUNTER
CC1I CC1I
TI1 TI1FP1
XOR
Input Filter &
IC1 IC1PS U OC1REF output OC1
TI1FP2 Prescaler Capture/Compare 1 Register TIMx_CH1
EdgeDetector control
TIMx_CH1 TRC
CC2I
CC2I
TI2FP1 IC2 IC2PS U
TI2 Input Filter & OC2REF output OC2
TIMx_CH2
TIMx_CH2 TI2FP2 Prescaler Capture/Compare 2 Register
EdgeDetector control
TRC
CC3I
CC3I
TI3FP3 IC3 U OC3
TI3 Input Filter & IC3PS OC3REF output
TIMx_CH3 TI3FP4 Prescaler Capture/Compare 3 Register TIMx_CH3
EdgeDetector control
TRC
CC4I
CC4I
TI4FP3 IC4 U OC4
TI4 IC4PS OC4REF output
TIMx_CH4 Input Filter & Prescaler Capture/Compare 4 Register TIMx_CH4
EdgeDetector TI4FP4 control
TRC
ETRF

Notes:
Reg Preload registers transferred
to active registers on U event
according to control bit

event

interrupt & DMA output

13.4 Functional description

13.4.1 Time base unit

The main block of the Programmable Timer is a 16-bit counter with its related auto-reload
register. The counter can count up, down or both up and down. The counter clock can be
divided by a prescaler.
The counter, the auto-reload register and the prescaler register can be written or read by
software. This is true even when the counter is running.

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UM0306 General purpose timer (TIMx)

The Time Base Unit includes:

● Counter Register (TIMx_CNT)
● Prescaler Register (TIMx_PSC):
● Auto-Reload Register (TIMx_ARR)
The auto-reload register is preloaded. Writing or reading the auto-reload register access the
preload register. The content of the preload register is transferred in the shadow register
permanently or at each update event UEV, depending on the auto-reload preload enable bit
(ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the
overflow (or underflow when down-counting) and if the UDIS bit equals 0 in the TIMx_CR1
register. It can also be generated by software. The generation of the update event is
described in detail for each configuration.
The counter is clocked by the prescaler output CK_CNT, which is enabled only when the
counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller
description to get more details on counter enabling).
Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN.

Prescaler description
The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It
is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register).
It can be changed on the fly as this control register is buffered. The new prescaler ratio is
taken in account at the next update event.
Figure 73 and Figure 74 give some examples of the counter behavior when the prescaler
ratio is changed on the fly:

Figure 73. Counter timing diagram with prescaler division change from 1 to 2

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F7 F8 F9 FA FB FC 00 01 02 03

UPDATE EVENT (UEV)

PRESCALER CONTROL REGISTER 0 1

Write a new value in TIMx_PSC

PRESCALER BUFFER 0 1

PRESCALER COUNTER 0 0 1 0 1 0 1 0 1

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Figure 74. Counter timing diagram with prescaler division change from 1 to 4

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F7 F8 F9 FA FB FC 00 01

UPDATE EVENT (UEV)

PRESCALER CONTROL REGISTER 0 3

Write a new value in TIMx_PSC

PRESCALER BUFFER 0 3

PRESCALER COUNTER 0 0 1 2 3 0 1 2 3

13.4.2 Counter modes

Up-counting mode
In up-counting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
An Update event can be generate at each counter overflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller).
The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register.
This is to avoid updating the shadow registers while writing new values in the preload
registers. Then no update event occurs until the UDIS bit has been written to 0. However,
the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate
doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register
is set, setting the UG bit generates an update event UEV but without setting the UIF flag
(thus no interrupt or DMA request is sent). This is to avoid generating both update and
capture interrupts when clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The auto-reload shadow register is updated with the preload value (TIMx_ARR),
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

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UM0306 General purpose timer (TIMx)

Figure 75. Counter timing diagram, internal clock divided by 1

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 76. Counter timing diagram, internal clock divided by 2

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0034 0035 0036 0000 0001 0002 0003

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 77. Counter timing diagram, internal clock divided by 4

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0035 0036 0000 0001

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

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General purpose timer (TIMx) UM0306

Figure 78. Counter timing diagram, internal clock divided by N

CK_INT

TIMER CLOCK = CK_CNT

COUNTER REGISTER 1F 20 00

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 79. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD REGISTER FF 36

Write a new value in TIMx_ARR

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UM0306 General purpose timer (TIMx)

Figure 80. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
preloaded)

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F0 F1 F2 F3 F4 F5 00 01 02 03 04 05 06 07

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD PRELOAD REGISTER F5 36

AUTO-RELOAD SHADOW REGISTER F5 36

Write a new value in TIMx_ARR

Down-counting mode
In down-counting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until UDIS bit has been written to 0.
However, the counter restarts from the current auto-reload value, whereas the counter of the
prescaler restarts from 0 (but the prescale rate doesn’t change).
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupts when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The auto-reload active register is updated with the preload value (content of the TIMx_ARR
register). Note that the auto-reload is updated before the counter is reloaded, so that the
next period is the expected one.
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.

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General purpose timer (TIMx) UM0306

Figure 81. Counter timing diagram, internal clock divided by 1

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

COUNTER UNDERFLOW (cnt_udf)

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 82. Counter timing diagram, internal clock divided by 2

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0002 0001 0000 0036 0035 0034 0033

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 83. Counter timing diagram, internal clock divided by 4

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0001 0000 0036 0035

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

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UM0306 General purpose timer (TIMx)

Figure 84. Counter timing diagram, internal clock divided by N

CK_INT

TIMER CLOCK = CK_CNT

COUNTER REGISTER 20 1F 00 36

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 85. Counter timing diagram, Update event when repetition counter is not
used

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 05 04 03 02 01 00 36 35 34 33 32 31 30 2F

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD REGISTER FF 36

Write a new value in TIMx_ARR

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), generates an counter overflow event, then counts down to 0 and
generates a counter underflow event. Then it restarts counting from 0.
In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated
by hardware and gives the current direction of the counter.
The update event can be generated at each counter overflow and at each counter underflow
or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller) also generates an update event. In this case, the counter restarts counting from
0, as well as the counter of the prescaler.
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter continues counting up and down, based on the current auto-reload
value.

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General purpose timer (TIMx) UM0306

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
The auto-reload active register is updated with the preload value (content of the TIMx_ARR
register). Note that if the update source is a counter overflow, the auto-reload is updated
before the counter is reloaded, so that the next period is the expected one (the counter is
loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.

Figure 86. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 04 03 02 01 00 01 02 03 04 05 06 05 04 03

COUNTER UNDERFLOW

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Note: Here, center-aligned mode 1 is used

Figure 87. Counter timing diagram, internal clock divided by 2

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0003 0002 0001 0000 0001 0002 0003

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

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UM0306 General purpose timer (TIMx)

Figure 88. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 0034 0035 0036 0035

COUNTER OVERFLOW (cnt_ovf)

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Note: Here, center-aligned mode 2 or 3 is used with an UIF on overflow

Figure 89. Counter timing diagram, internal clock divided by N

CK_INT

TIMER CLOCK = CK_CNT

COUNTER REGISTER 20 1F 01 00

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

Figure 90. Counter timing diagram, Update event with ARPE=1 (counter underflow)

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER 06 05 04 03 02 01 00 01 02 03 04 05 06 07

COUNTER UNDERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD PRELOAD REGISTER FD 36

Write a new value in TIMx_ARR

AUTO-RELOAD ACTIVE REGISTER FD 36

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Figure 91. Counter timing diagram, Update event with ARPE=1 (counter overflow)

CK_INT

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER F7 F8 F9 FA FB FC 36 35 34 33 32 31 30 2F

COUNTER OVERFLOW

UPDATE EVENT (UEV)

UPDATE INTERRUPT FLAG (UIF)

AUTO-RELOAD PRELOAD REGISTER FD 36

Write a new value in TIMx_ARR

AUTO-RELOAD ACTIVE REGISTER FD 36

13.4.3 Clock selection

The counter clock can be provided by the following clock sources:
● Internal clock (CK_INT)
● External clock mode1: external input pin (TIx)
● External clock mode2: external trigger input (ETR)
● Internal trigger inputs (ITRx): using one timer as prescaler for another timer, for
example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to : Using
one timer as prescaler for the another on page 252 for more details.

Internal clock source (CK_INT)

If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the
CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual
control bits and can be changed only by software (except UG which remains cleared
automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal
clock CK_INT.
Figure 92 shows the behavior of the control circuit and the up-counter in normal mode,
without prescaler.

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Figure 92. Control circuit in normal mode, internal clock divided by 1

CK_INT

CEN=CNT_EN

UG

CNT_INIT

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 31 32 33 34 35 36 00 01 02 03 04 05 06 07

External clock source mode 1

This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count
at each rising or falling edge on a selected input.

Figure 93. TI2 external clock connection example

TIMx_SMCR
TS[2:0]

ti2f or
or
ti1f or encoder
ITR1 001 mode
ti1f_ed 100
ti1fp1 trgi external clock
ti2f_rising 0 101 mode 1 CK_PSC
TI2 Filter Edge ti2fp2 110
Detector ti2f_falling etrf external clock
1 etrf 111 mode 2
ICF[3:0] CC2P CK_INT internal clock
TIMx_CCMR1 TIMx_CCER mode
(internal clock)

ECE SMS[2:0]
TIMx_SMCR

For example, to configure the up-counter to count in response to a rising edge on the TI2
input, use the following procedure:
For example, to configure the up-counter to count in response to a rising edge on the TI2
input, use the following procedure:
1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01’ in the
TIMx_CCMR1 register.
2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1
register (if no filter is needed, keep IC2F=0000).
Note: The capture prescaler is not used for triggering, so you don’t need to configure it.
3. Select rising edge polarity by writing CC2P=0 in the TIMx_CCER register.
4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR
register.
5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register.
6. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
When a rising edge occurs on TI2, the counter counts once and the TIF flag is set.

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The delay between the rising edge on TI2 and the actual clock of the counter is due to the
resynchronization circuit on TI2 input.

Figure 94. Control circuit in external clock mode 1

TI2

CNT_EN

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 34 35 36

TIF

Write TIF=0

External clock source mode 2

This mode is selected by writing ECE=1 in the TIMx_SMCR register.
The counter can count at each rising or falling edge on the external trigger input ETR.
The Figure 95 gives an overview of the external trigger input block.

Figure 95. External trigger input block

ti2f or
or
ti1f or encoder
mode

trgi external clock

mode 1 ck_psc
ETR
ETR pin 0 ETRP
divider filter etrf external clock
down-counter mode 2
/1, /2, /4, /8
1 CK_INT
CK_INT internal clock
mode
(internal clock)
ETP ETPS[1:0] ETF[3:0]
TIMx_SMCR TIMx_SMCR TIMx_SMCR ECE SMS[2:0]
TIMx_SMCR

For example, to configure the up-counter to count each 2 rising edges on ETR, use the
following procedure:
1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register.
2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register
3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR
register
4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register.
5. Enable the counter by writing CEN=1 in the TIMx_CR1 register.
The counter counts once each 2 ETR rising edges.
The delay between the rising edge on ETR and the actual clock of the counter is due to the
resynchronization circuit on the ETRP signal.

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Figure 96. Control circuit in external clock mode 2

fMASTER

CNT_EN

ETR

ETRP

ETRF

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 34 35 36

13.4.4 Capture/compare channels

Each Capture/Compare channel is built around a capture/compare register (including a
shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and
an output stage (with comparator and output control).
The following figure gives an overview of one Capture/Compare channel.
The input stage samples the corresponding TIx input to generate a filtered signal TIxF.
Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be
used as trigger input by the slave mode controller or as the capture command. It is
prescaled before the capture register (ICxPS).

Figure 97. Capture/compare channel (example: channel 1 input stage)

TI1F_ED
to the slave mode controller

TI1F_rising 0
TI1 TI1F
filter Edge TI1FP1
01
fDTS down-counter Detector TI1F_falling
1
TI2FP1 IC1 divider IC1PS
10
/1, /2, /4, /8
ICF[3:0] CC1P TRC
11
TIMx_CCMR1 TIMx_CCER (from slave mode
controller)
TI2F_rising 0
(from channel 2)
CC1S[1:0] ICPS[1:0] CC1E
TI2F_falling
1
(from channel 2) TIMx_CCMR1 TIMx_CCER

The output stage generates an intermediate waveform which is then used for reference:
OCxRef (active high). The polarity acts at the end of the chain.

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Figure 98. Capture/compare channel 1 main circuit

APB Bus

MCU-PERIPHERAL INTERFACE

(if 16-bit)
8 8

high

low
S write CCR1H
read CCR1H S write_in_progress
read_in_progress
Capture/Compare Preload Register write CCR1L
read CCR1L R
R CC1S[1]
output
capture_transfer compare_transfer mode
CC1S[0]
CC1S[1] input
mode OC1PE
Capture/Compare Shadow Register OC1PE
CC1S[0] UEV
TIMx_CCMR1
comparator (from time
ic1ps capture base unit)
CC1E CNT>CCR1
Counter
CNT=CCR1
CC1G
TIMx_EGR

Figure 99. Output stage of capture/compare channel (channel 1)

ETRF To the master mode 0

controller Output OC1
Enable
1 Circuit

CC1P
CNT > CCR1
Output Mode oc1ref TIMx_CCER
CNT = CCR1 Controller

CC1E TIMx_CCER

OC1M[2:0]
TIMx_CCMR1

The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.

13.4.5 Input capture mode

In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding ICx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be

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cleared by software by writing it to ‘0’ or by reading the captured data stored in the
TIMx_CCRx register (when you read the low byte in case of 16-bit register). CCxOF is
cleared when you write it to ‘0’.
The following example shows how to capture the counter value in TIMx_CCR1 when TI1
input rises. To do this, use the following procedure:
● Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S
bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00,
the channel is configured in input and the TIMx_CCR1 register becomes read-only.
● Program the input filter duration you need with respect to the signal you connect to the
timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s
imagine that, when toggling, the input signal is not stable during at must 5 internal clock
cycles. We must program a filter duration longer than these 5 clock cycles. We can
validate a transition on TI1 when 8 consecutive samples with the new level have been
detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the
TIMx_CCMR1 register.
● Select the edge of the active transition on the TI1 channel by writing CC1P bit to 0 in
the TIMx_CCER register (rising edge in this case).
● Program the input prescaler. In our example, we wish the capture to be performed at
each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the
TIMx_CCMR1 register).
● Enable capture from the counter into the capture register by setting the CC1E bit in the
TIMx_CCER register.
● If needed, enable the related interrupt request by setting the CC1IE bit in the
TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the
TIMx_DIER register.
When an input capture occurs:
● The TIMx_CCR1 register gets the value of the counter on the active transition.
● CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures
occurred whereas the flag was not cleared.
● An interrupt is generated depending on the CC1IE bit.
● A DMA request is generated depending on the CC1DE bit.
In order to handle the overcapture, it is recommended to read the data before the
overcapture flag. This is to avoid missing an overcapture which could happen after reading
the flag and before reading the data.
Note: IC interrupt and/or DMA requests can be generated by software by setting the
corresponding CCxG bit in the TIMx_EGR register.

13.4.6 PWM input mode

This mode is a particular case of input capture mode. The procedure is the same except:
● Two ICx signals are mapped on the same TIx input.
● These 2 ICx signals are active on edges with opposite polarity.
● One of the two TIxFP signals is selected as trigger input and the slave mode controller
is configured in reset mode.

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For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in
TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending
on CK_INT frequency and prescaler value):
● Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1
register (TI1 selected).
● Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter
clear): write the CC1P bit to ‘0’ (active on rising edge).
● Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1
register (TI1 selected).
● Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P
bit to ‘1’ (active on falling edge).
● Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register
(TI1FP1 selected).
● Configure the slave mode controller in reset mode: write the SMS bits to 100 in the
TIMx_SMCR register.
● Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register.

Figure 100. PWM input mode timing.

TI1

TIMx_CNT 0004 0000 0001 0002 0003 0004 0000

TIMx_CCR1 0004

TIMx_CCR2 0002

IC1 Capture IC2 Capture

period measurement pulse width measurement
reset counter

13.4.7 Forced output mode

In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal
(OCxREF and then OCx) can be forced to active or inactive level directly by software,
independently of any comparison between the output compare register and the counter.
To force an output compare signal (ocxref/OCx) to its active level, you just need to write 101
in the OCxM bits in the corresponding TIMx_CCMRx register. Thus ocxref is forced high
(OCxREF is always active high) and OCx get opposite value to CCxP polarity bit.
e.g.: CCxP=0 (OCx active high) => OCx is forced to high level.
ocxref signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx
register.
Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still
performed and allows the flag to be set. Interrupt and DMA requests can be sent
accordingly. This is described in the Output Compare Mode section.

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13.4.8 Output compare mode

This function is used to control an output waveform or indicating when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
● Assigns the corresponding output pin to a programmable value defined by the output
compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP
bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set
active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match.
● Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register).
● Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the
TIMx_DIER register).
● Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the
TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request
selection).
The TIMx_CCRx registers can be programmed with or without preload registers using the
OCxPE bit in the TIMx_CCMRx register.
In output compare mode, the update event UEV has no effect on ocxref and OCx output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in One Pulse Mode).
Procedure:
1. Select the counter clock (internal, external, prescaler).
2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers.
3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be
generated.
4. Select the output mode. For example, you must write OCxM=’011’, OCxPE=’0’,
CCxP=’0’ and CCxE=’1’ to toggle OCx output pin when CNT matches CCRx, CCRx
preload is not used, OCx is enabled and active high.
5. Enable the counter by setting the CEN bit in the TIMx_CR1 register.
The TIMx_CCRx register can be updated at any time by software to control the output
waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx
shadow register is updated only at the next update event UEV). An example is given in
Figure 101.

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Figure 101. Output compare mode, toggle on OC1.

Write B201h in the OC1R register

TIMx_CNT 0039 003A 003B B200 B201

TIMx_CCR1 003A B201

oc1ref=OC1

Match detected on OCR1

Interrupt generated if enabled

13.4.9 PWM mode

Pulse Width Modulation mode allows you to generate a signal with a frequency determined
by the value of the TIMx_ARR register and a duty cycle determined by the value of the
TIMx_CCRx register.
The PWM mode can be selected independently on each channel (one PWM per OCx
output) by writing ‘110’ (PWM mode 1) or ‘111’ (PWM mode 2) in the OCxM bits in the
TIMx_CCMRx register. You must enable the corresponding preload register by setting the
OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in
up-counting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register.
As the preload registers are transferred to the shadow registers only when an update event
occurs, before starting the counter, you have to initialize all the registers by setting the UG
bit in the TIMx_EGR register.
OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It
can be programmed as active high or active low. OCx output is enabled by the CCxE bit in
the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details.
In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine
whether TIMx_CCRx≤TIMx_CNT or TIMx_CNT≤TIMx_CCRx (depending on the direction of
the counter). However, to comply with the OCREF_CLR functionality (OCREF can be
cleared by an external event through the ETR signal until the next PWM period), the OCREF
signal is asserted only:
● When the result of the comparison changes, or
● When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from
the “frozen” configuration (no comparison, OCxM=‘000’) to one of the PWM modes
(OCxM=‘110’ or ‘111’).
This allows to force the PWM by software while running.
The timer is able to generate PWM in edge-aligned mode or center-aligned mode
depending on the CMS bits in the TIMx_CR1 register.

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PWM edge-aligned mode

Up-counting configuration
Up-counting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the
Section : Up-counting mode on page 224.
In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is
high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in
TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at
‘1’. If the compare value is 0 then OCxREF is held at ‘0’. Figure 102 shows some edge-
aligned PWM waveforms in an example where TIMx_ARR=8.

Figure 102. Edge-aligned PWM waveforms (ARR=8)

COUNTER REGISTER 0 1 2 3 4 5 6 7 8 0 1

ocxref
CCRx=4
CCxIF

ocxref
CCRx=8
CCxIF

ocxref ‘1’
CCRx>8
CCxIF

ocxref ‘0’
CCRx=0
CCxIF

Down-counting configuration
Down-counting is active when DIR bit in TIMx_CR1 register is high. Refer to Down-counting
mode on page 227
In PWM mode 1, the reference signal ocxref is low as long as TIMx_CNT>TIMx_CCRx else
it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in
TIMx_ARR, then ocxref is held at ‘1’. 0% PWM is not possible in this mode.

PWM center-aligned mode

Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from
‘00’ (all the remaining configurations having the same effect on the ocxref/OCx signals). The
compare flag is set when the counter counts up, when it counts down or both when it counts
up and down depending on the CMS bits configuration. The direction bit (DIR) in the
TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to
the Center-aligned mode (up/down counting) on page 229.
Figure 103 shows some center-aligned PWM waveforms in an example where:
● TIMx_ARR=8,
● PWM mode is the PWM mode 1,
● The flag is set when the counter counts down corresponding to the center-aligned
mode 1 selected for CMS=01 in TIMx_CR1 register.

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Figure 103. Center-aligned PWM waveforms (ARR=8)

COUNTER REGISTER 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1

ocxref
CCRx=4
CCxIF

ocxref
CCRx=7
CCxIF

ocxref ‘1’
CCRx>=8
CCxIF

ocxref ‘0’
CCRx=0
CCxIF

Hints on using center-aligned mode:

● When starting in center-aligned mode, the current up-down configuration is used. It
means that the counter counts up or down depending on the value written in the DIR bit
in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the
same time by the software.
● Writing to the counter while running in center-aligned mode is not recommended as it
can lead to unexpected results. In particular:
– The direction is not updated if you write a value in the counter that is greater than
the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was
counting up, it continues to count up.
– The direction is updated if you write 0 or write the TIMx_ARR value in the counter
but no Update Event UEV is generated.
● The safest way to use center-aligned mode is to generate an update by software
(setting the UG bit in the TIMx_EGR register) just before starting the counter and not to
write the counter while it is running.

13.4.10 One pulse mode

One Pulse Mode (OPM) is a particular case of the previous modes. It allows the counter to
be started in response to a stimulus and to generate a pulse with a programmable length
after a programmable delay.
Starting the counter can be controlled through the slave mode controller. Generating the
waveform can be done in output compare mode or PWM mode. You select One Pulse Mode
by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically
at the next update event UEV.
A pulse can be correctly generated only if the compare value is different from the counter
initial value. Before starting (when the timer is waiting for the trigger), the configuration must
be:
In up-counting: CNT<CCRx≤ARR (in particular, 0<CCRx),
In down-counting: CNT>CCRx.

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Figure 104. Example of one pulse mode.

TI2

OC1Ref

OC1

TIM1_ARR
COUNTER

TIM1_CCR1

0
tDELAY
tPULSE t

For example you may want to generate a positive pulse on OC1 with a length of tPULSE and
after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin.
Let’s use TI2FP2 as trigger 1:
● Map TI2FP2 on TI2 by writing IC2S=’01’ in the TIMx_CCMR1 register.
● TI2FP2 must detect a rising edge, write CC2P=’0’ in the TIMx_CCER register.
● Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in
the TIMx_SMCR register.
● TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register
(trigger mode).
The OPM waveform is defined by writing the compare registers (taking into account the
clock frequency and the counter prescaler).
● The tDELAY is defined by the value written in the TIMx_CCR1 register.
● The tPULSE is defined by the difference between the auto-reload value and the compare
value (TIMx_ARR - TIMx_CCR1).
● Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare
match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload
value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1
register. You can optionally enable the preload registers by writing OC1PE=’1’ in the
TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to
write the compare value in the TIMx_CCR1 register, the auto-reload value in the
TIMx_ARR register, generate an update by setting the UG bit and wait for external
trigger event on TI2. CC1P is written to ‘0’ in this example.
In our example, the DIR and CMS bits in the TIMx_CR1 register should be low.
You only want 1 pulse, so you write ‘1’ in the OPM bit in the TIMx_CR1 register to stop the
counter at the next update event (when the counter rolls over from the auto-reload value
back to 0).
Particular case: OCx fast enable:
In One Pulse Mode, the edge detection on TIx input set the CEN bit which enables the
counter. Then the comparison between the counter and the compare value makes the

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output toggle. But several clock cycles are needed for these operations and it limits the
minimum delay tDELAY min we can get.
If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the
TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus,
without taking in account the comparison. Its new level is the same as if a compare match
had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode.

13.4.11 Clearing the OCxREF signal on an external event

The OCxREF signal for a given channel can be reset by applying a High level on the ETRF
input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The
OCxREF remains low until the next update event, UEV, occurs.

This function can be only used in output compare mode and PWM mode. It does not work in
forced mode.
For example, the OCxREF signal can be connected to the output of a comparator to be used
for current handling. In this case, the ETR must be configured as follow:
1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIM1_SMCR
register set to ‘00’.
2. The external clock mode 2 must be disabled: bit ECE of the TIM1_SMCR register set to
‘0’.
3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be
configured according to the user needs.
Figure 105 shows the behavior of the OCxREF signal when the ETRF Input becomes High,
for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in
PWM mode.

Figure 105. Clearing TIMx OCxREF

(CCRx)
counter (CNT)

ETRF

OCxREF
(OCxCE=’0’)

OCxREF
(OCxCE=’1’)

OCREF_CLR OCREF_CLR
becomes high still high

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13.4.12 Encoder interface mode

To select Encoder Interface mode write SMS=‘001’ in the TIMx_SMCR register if the
counter is counting on TI2 edges only, SMS=’010’ if it is counting on TI1 edges only and
SMS=’011’ if it is counting on both TI1 and TI2 edges.
Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER
register. When needed, you can program the input filter as well.
The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to
Table 39. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2
after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted,
TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in
TIMx_CR1 register written to ‘1’). The sequence of transitions of the two inputs is evaluated
and generates count pulses as well as the direction signal. Depending on the sequence the
counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware
accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever
the counter is counting on TI1 only, TI2 only or both TI1 and TI2.
Encoder interface mode acts simply as an external clock with direction selection. This
means that the counter just counts continuously between 0 and the auto-reload value in the
TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must
configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler,
trigger output features continue to work as normal.
In this mode, the counter is modified automatically following the speed and the direction of
the incremental encoder and its content, therefore, always represents the encoder’s
position. The count direction correspond to the rotation direction of the connected sensor.
The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the
same time.

Table 39. Counting direction versus encoder signals

Level on TI1FP1 signal TI2FP2 signal
opposite
signal (TI1FP1
Active Edge
for TI2,
Rising Falling Rising Falling
TI2FP2 for
TI1)

Counting on High Down Up No Count No Count

TI1 only Low Up Down No Count No Count

Counting on High No Count No Count Up Down

TI2 only Low No Count No Count Down Up

Counting on High Down Up Up Down

TI1 and TI2 Low Up Down Down Up

An external incremental encoder can be connected directly to the MCU without external
interface logic. However, comparators are normally be used to convert the encoder’s
differential outputs to digital signals. This greatly increases noise immunity. The third
encoder output which indicate the mechanical zero position, may be connected to an
external interrupt input and trigger a counter reset.
The Figure 106 gives an example of counter operation, showing count signal generation and
direction control. It also shows how input jitter is compensated where both edges are

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selected. This might occur if the sensor is positioned near to one of the switching points. For
this example we assume that the configuration is the following:
● CC1S=’01’ (TIMx_CCMR1 register, IC1FP1 mapped on TI1).
● CC2S=’01’ (TIMx_CCMR2 register, IC2FP2 mapped on TI2).
● CC1P=’0’ (TIMx_CCER register, IC1FP1 non-inverted, IC1FP1=TI1).
● CC2P=’0’ (TIMx_CCER register, IC2FP2 non-inverted, IC2FP2=TI2).
● SMS=’011’ (TIMx_SMCR register, both inputs are active on both rising and falling
edges).
● CEN=’1’ (TIMx_CR1 register, Counter is enabled).

Figure 106. Example of counter operation in encoder interface mode.

forward jitter backward jitter forward

TI1

TI2

COUNTER

up down up

Figure 107 gives an example of counter behavior when IC1FP1 polarity is inverted (same
configuration as above except CC1P=’1’).

Figure 107. Example of encoder interface mode with IC1FP1 polarity inverted.
forward jitter backward jitter forward

TI1

TI2

COUNTER

down up down

The timer, when configured in Encoder Interface mode provides information on the sensor’s
current position. You can obtain dynamic information (speed, acceleration, deceleration) by
measuring the period between two encoder events using a second timer configured in
capture mode. The output of the encoder which indicates the mechanical zero can be used
for this purpose. Depending on the time between two events, the counter can also be read

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at regular times. You can do this by latching the counter value into a third input capture
register if available (then the capture signal must be periodic and can be generated by
another timer). when available, it is also possible to read its value through a DMA request
generated by a Real-Time clock.

13.4.13 Timer input XOR function

The TI1S bit in the TIM1_CR2 register, allows the input filter of channel 1 to be connected to
the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3.
The XOR output can be used with all the timer input functions such as trigger or input
capture.
An example of this feature used to interface Hall sensors is given in Section 12.4.18 on page
185.

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13.4.14 Timers and external trigger synchronization

The TIMx Timers can be synchronized with an external trigger in several modes: Reset
mode, Gated mode and Trigger mode.

Slave mode: Reset mode

The counter and its prescaler can be reinitialized in response to an event on a trigger input.
Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is
generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated.
In the following example, the up-counter is cleared in response to a rising edge on TI1 input:
● Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write
CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edges only).
● Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
● Start the counter by writing CEN=1 in the TIMx_CR1 register.
The counter starts counting on the internal clock, then behaves normally until TI1 rising
edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the
trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA
request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register).
The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36.
The delay between the rising edge on TI1 and the actual reset of the counter is due to the
resynchronization circuit on TI1 input.

Figure 108. Control circuit in reset mode

TI1

UG

COUNTER CLOCK = ck_cnt = ck_psc

COUNTER REGISTER 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03

TIF

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Slave mode: Gated mode

The counter can be enabled depending on the level of a selected input.
In the following example, the up-counter counts only when TI1 input is low:
● Configure the channel 1 to detect low levels on TI1. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC1F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits
select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write
CC1P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
● Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
● Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the
counter doesn’t start if CEN=0, whatever is the trigger input level).
The counter starts counting on the internal clock as long as TI1 is low and stops as soon as
TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts
or stops.
The delay between the rising edge on TI1 and the actual stop of the counter is due to the
resynchronization circuit on TI1 input.

Figure 109. Control circuit in gated mode

TI1

cnt_en

COUNTER CLOCK = ck_cnt = ck_psc

COUNTER REGISTER 30 31 32 33 34 35 36 37 38

TIF

Write TIF=0

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Slave mode: Trigger mode

The counter can start in response to an event on a selected input.
In the following example, the up-counter starts in response to a rising edge on TI2 input:
● Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration
(in this example, we don’t need any filter, so we keep IC2F=0000). The capture
prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are
selecting the input capture source only, CC2s=01 in TIMx_CCMR1 register. Write
CC2P=1 in TIMx_CCER register to validate the polarity (and detect low level only).
● Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI2 as the input source by writing TS=110 in TIMx_SMCR register.
When a rising edge occurs on TI2, the counter starts counting on the internal clock and the
TIF flag is set.
The delay between the rising edge on TI2 and the actual start of the counter is due to the
resynchronization circuit on TI2 input.

Figure 110. Control circuit in trigger mode

TI2

cnt_en

COUNTER CLOCK = ck_cnt = ck_psc

COUNTER REGISTER 34 35 36 37 38

TIF

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Slave mode: External Clock mode 2 + trigger mode

The external clock mode 2 can be used in addition to another slave mode (except external
clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock
input, and another input can be selected as trigger input when operating in reset mode,
gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS
bits of TIMx_SMCR register.
In the following example, the up-counter is incremented at each rising edge of the ETR
signal as soon as a rising edge of TI1 occurs:
1. Configure the external trigger input circuit by programming the TIMx_SMCR register as
follows:
– ETF = 0000: no filter
– ETPS=00: prescaler disabled
– ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock
mode 2.
2. Configure the channel 1 as follows, to detect rising edges on TI:
– IC1F=0000: no filter.
– The capture prescaler is not used for triggering and does not need to be
configured.
– CC1S=01in TIMx_CCMR1 register to select only the input capture source
– CC1P=0 in TIMx_CCER register to validate the polarity (and detect rising edge
only).
3. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select
TI1 as the input source by writing TS=101 in TIMx_SMCR register.
A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on
ETR rising edges.
The delay between the rising edge of the ETR signal and the actual reset of the counter is
due to the resynchronization circuit on ETRP input.

Figure 111. Control circuit in external clock mode 2 + trigger mode

TI1

CEN/CNT_EN

ETR

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER 34 35 36

TIF

13.4.15 Timer synchronization

The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
The following figure presents an overview of the trigger selection and the master mode

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selection blocks.

Using one timer as prescaler for the another

Figure 112. Master/Slave timer example

TIMER 1 TIMER 2

Clock MMS TS SMS

UEV MASTER SLAVE CK_PSC

TRGO1 ITR1
MODE MODE
PRESCALER COUNTER CONTROL CONTROL PRESCALER COUNTER

INPUT
TRIGGER
SELECTION

For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Figure 112. To do this:
● Configure Timer 1 in master mode so that it outputs a periodic trigger signal on each
update event UEV. If you write MMS=010 in the TIM1_CR2 register, a rising edge is
output on TRGO1 each time an update event is generated.
● To connect the TRGO1 output of Timer 1 to Timer 2, Timer 2 must be configured in
slave mode using ITR1 as internal trigger. You select this through the TS bits in the
TIM2_SMCR register (writing TS=001).
● Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the
TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the
periodic Timer 1 trigger signal (which correspond to the timer 1 counter overflow).
● Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1
register).
Note: If OCx is selected on Timer 1 as trigger output (MMS=1xx), its rising edge is used to clock
the counter of timer 2.

Using one timer to enable another timer

In this example, we control the enable of Timer 2 with the output compare 1 of Timer 1.
Refer to Figure 112 for connections. Timer 2 counts on the divided internal clock only when
OC1REF of Timer 1 is high. Both counter clock frequencies are divided by 3 by the
prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
● Configure Timer 2 to get the input trigger from Timer 1 (TS=001 in the TIM2_SMCR
register).
● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
● Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register).
● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).
Note: The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer 2
counter enable signal.

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Figure 113. Gating Timer 2 with OC1REF of Timer 1

CK_INT

TIMER1-OC1REF

TIMER1-CNT FC FD FE FF 00 01

TIMER2-CNT 3045 3046 3047 3048

TIMER 2-TIF

Write TIF=0

In the example in Figure 113, the Timer 2 counter and prescaler are not initialized before
being started. So they start counting from their current value. It is possible to start from a
given value by resetting both timers before starting Timer 1. You can then write any value
you want in the timer counters. The timers can easily be reset by software using the UG bit
in the TIMx_EGR registers.
In the next example, we synchronize Timer 1 and Timer 2. Timer 1 is the master and starts
from 0. Timer 2 is the slave and starts from 0xE7. The prescaler ratio is the same for both
timers. Timer 2 stops when Timer 1 is disabled by writing ‘0’ to the CEN bit in the TIM1_CR1
register:
● Configure Timer 1 master mode to send its Output Compare 1 Reference (OC1REF)
signal as trigger output (MMS=100 in the TIM1_CR2 register).
● Configure the Timer 1 OC1REF waveform (TIM1_CCMR1 register).
● Configure Timer 2 to get the input trigger from Timer 1 (TS=001 in the TIM2_SMCR
register).
● Configure Timer 2 in gated mode (SMS=101 in TIM2_SMCR register).
● Reset Timer 1 by writing ‘1’ in UG bit (TIM1_EGR register).
● Reset Timer 2 by writing ‘1’ in UG bit (TIM2_EGR register).
● Initialize Timer 2 to 0xE7 by writing ‘0xE7’ in the timer 2 counter (TIM2_CNTL).
● Enable Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register).
● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).
● Stop Timer 1 by writing ‘0’ in the CEN bit (TIM1_CR1 register).

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Figure 114. Gating Timer 2 with ENABLE of Timer 1

CK_INT

TIMER1-CEN=cnt_en

TIMER1-cnt_init

TIMER1-CNT 75 00 01 02

TIMER2-CNT AB 00 E7 E8 E9

TIMER2-cnt_init

TIMER2
write CNT

TIMER 2-TIF

Write TIF=0

Using one timer to start another timer

In this example, we set the enable of Timer 2 with the update event of Timer 1. Refer to
Figure 112 for connections. Timer 2 starts counting from its current value (which can be
non-zero) on the divided internal clock as soon as the update event is generated by Timer 1.
When Timer 2 receives the trigger signal its CEN bit is automatically set and the counter
counts until we write ‘0’ to the CEN bit in the TIM2_CR1 register. Both counter clock
frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3).
● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register).
● Configure the Timer 1 period (TIM1_ARR registers).
● Configure Timer 2 to get the input trigger from Timer 1 (TS=001 in the TIM2_SMCR
register).
● Configure Timer 2 in trigger mode (SMS=110 in TIM2_SMCR register).
● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).

Figure 115. Triggering Timer 2 with UPDATE of Timer 1

CK_INT

TIMER1-UEV

TIMER1-CNT FD FE FF 00 01 02

TIMER2-CNT 45 46 47 48

TIMER2-CEN=cnt_en

TIMER 2-TIF

Write TIF=0

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As in the previous example, you can initialize both counters before starting counting.
Figure 116 shows the behavior with the same configuration as in Figure 115 but in trigger
mode instead of gated mode (SMS=110 in the TIM2_SMCR register).

Figure 116. Triggering Timer 2 with ENABLE of Timer 1

CK_INT

TIMER1-CEN=cnt_en

TIMER1-cnt_init

TIMER1-CNT 75 00 01 02

TIMER2-CNT CD 00 E7 E8 E9 EA

TIMER2-cnt_init

TIMER2
write CNT

TIMER 2-TIF

Write TIF=0

Using one timer as prescaler for another timer

For example, you can configure Timer 1 to act as a prescaler for Timer 2. Refer to
Figure 112 for connections. To do this:
● Configure Timer 1 master mode to send its Update Event (UEV) as trigger output
(MMS=010 in the TIM1_CR2 register). then it outputs a periodic signal on each counter
overflow.
● Configure the Timer 1 period (TIM1_ARR registers).
● Configure Timer 2 to get the input trigger from Timer 1 (TS=001 in the TIM2_SMCR
register).
● Configure Timer 2 in external clock mode 1 (SMS=111 in TIM2_SMCR register).
● Start Timer 2 by writing ‘1’ in the CEN bit (TIM2_CR1 register).
● Start Timer 1 by writing ‘1’ in the CEN bit (TIM1_CR1 register).

Starting 2 timers synchronously in response to an external trigger

In this example, we set the enable of timer 1 when its TI1 input rises, and the enable of
Timer 2 with the enable of Timer 1. Refer to Figure 112 for connections. To ensure the

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counters are aligned, Timer 1 must be configured in Master/Slave mode (slave with respect
to TI1, master with respect to Timer 2):
● Configure Timer 1 master mode to send its Enable as trigger output (MMS=001 in the
TIM1_CR2 register).
● Configure Timer 1 slave mode to get the input trigger from TI1 (TS=100 in the
TIM1_SMCR register).
● Configure Timer 1 in trigger mode (SMS=110 in the TIM1_SMCR register).
● Configure the Timer 1 in Master/Slave mode by writing MSM=’1’ (TIM1_SMCR
register).
● Configure Timer 2 to get the input trigger from Timer 1 (TS=001 in the TIM2_SMCR
register).
● Configure Timer 2 in trigger mode (SMS=110 in the TIM2_SMCR register).
When a rising edge occurs on TI1 (Timer 1), both counters starts counting synchronously on
the internal clock and both TIF flags are set.
Note: In this example both timers are initialized before starting (by setting their respective UG
bits). Both counters starts from 0, but you can easily insert an offset between them by
writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode
insert a delay between CNT_EN and CK_PSC on timer 1.

Figure 117. Triggering Timer 1 and 2 with Timer 1 TI1 input.

CK_INT

TIMER 1-TI1

TIMER1-CEN=cnt_en

TIMER 1-ck_psc

TIMER1-CNT 00 01 02 03 04 05 06 07 08 09

TIMER1-TIF

TIMER2-CEN=cnt_en

TIMER 2-ck_psc

TIMER2-CNT 00 01 02 03 04 05 06 07 08 09

TIMER2-TIF

13.4.16 Debug mode

When the microcontroller enters debug mode (Cortex-M3 core - halted), the TIMx counter
either continues to work normally or stops, depending on DBG_TIMx_STOP configuration
bit in DBG module. For more details, refer to Section 20.15.2: Debug support for timers and
watchdog and bxCAN.

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13.5 TIMx register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

13.5.1 Control register 1 (TIMx_CR1)

Address offset: 00h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved CKD[1:0] ARPE CMS DIR OPM URS UDIS CEN

rw rw rw rw rw rw rw rw rw rw

Bits 15:10 Reserved, always read as 0

CKD: Clock Division.
This bit-field indicates the division ratio between the timer clock (CK_INT) frequency
and sampling clock used by the digital filters (ETR, TIx),
Bits 9:8 00: TDTS=Tck_tim
01: TDTS=2*Tck_tim
10: TDTS=4*Tck_tim
11: Reserved
ARPE: Auto-Reload Preload enable.
Bit 7 0: TIMx_ARR register is not buffered.
1: TIMx_ARR register is buffered.
CMS: Center-aligned Mode Selection.
00: Edge-aligned mode. The counter counts up or down depending on the direction
bit (DIR).
01: Center-aligned mode 1. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx
register) are set only when the counter is counting down.
10: Center-aligned mode 2. The counter counts up and down alternatively. Output
Bits 6:5
compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx
register) are set only when the counter is counting up.
11: Center-aligned mode 3. The counter counts up and down alternatively. Output
compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx
register) are set both when the counter is counting up or down.
Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as
long as the counter is enabled (CEN=1)
DIR: Direction.
0: Counter used as up-counter.
Bit 4 1: Counter used as down-counter.
Note: This bit is read only when the timer is configured in Center-aligned mode or
Encoder mode.
OPM: One Pulse Mode.
Bit 3 0: Counter is not stopped at update event
1: Counter stops counting at the next update event (clearing the bit CEN).

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URS: Update Request Source.

This bit is set and cleared by software to select the UEV event sources.
0: Any of the following events generate an update interrupt or DMA request if
enabled. These events can be:
Bit 2 – Counter overflow/underflow
– Setting the UG bit
– Update generation through the slave mode controller
1: Only counter overflow/underflow generates an update interrupt or DMA request if
enabled.
UDIS: Update DIsable.
This bit is set and cleared by software to enable/disable UEV event generation.
0: UEV enabled. The Update (UEV) event is generated by one of the following
events:
– Counter overflow/underflow
Bit 1 – Setting the UG bit
– Update generation through the slave mode controller
Buffered registers are then loaded with their preload values.
1: UEV disabled. The Update event is not generated, shadow registers keep their
value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if
the UG bit is set or if a hardware reset is received from the slave mode controller.
CEN: Counter enable.
0: Counter disabled
1: Counter enabled
Bit 0 Note: External clock, gated mode and encoder mode can work only if the CEN bit has
been previously set by software. However trigger mode can set the CEN bit
automatically by hardware.
CEN is cleared automatically in one pulse mode, when an update event occurs.

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13.5.2 Control register 2 (TIMx_CR2)

Address offset: 04h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TI1S MMS[2:0] CCDS Reserved

rw rw rw rw rw

Bits 15:8 Reserved, always read as 0.

TI1S: TI1 Selection.
0: The TIMx_CH1 pin is connected to TI1 input.
Bit 7 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR
combination)
See also Section 12.4.18: Interfacing with Hall sensors on page 185
MMS: Master Mode Selection.
These bits allow to select the information to be sent in master mode to slave timers
for synchronization (TRGO). The combination is as follows:
000: Reset - the UG bit from the TIMx_EGR register is used as trigger output
(TRGO). If the reset is generated by the trigger input (slave mode controller
configured in reset mode) then the signal on TRGO is delayed compared to the
actual reset.
001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO).
It is useful to start several timers at the same time or to control a window in which a
slave timer is enabled. The Counter Enable signal is generated by a logic OR
between CEN control bit and the trigger input when configured in gated mode.
Bits 6:4 When the Counter Enable signal is controlled by the trigger input, there is a delay on
TRGO, except if the master/slave mode is selected (see the MSM bit description in
TIMx_SMCR register).
010: Update - The update event is selected as trigger output (TRGO). For instance a
master timer can then be used as a prescaler for a slave timer.
011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag
is to be set (even if it was already high), as soon as a capture or a compare match
occurred. (TRGO).
100: Compare - OC1REF signal is used as trigger output (TRGO).
101: Compare - OC2REF signal is used as trigger output (TRGO).
110: Compare - OC3REF signal is used as trigger output (TRGO).
111: Compare - OC4REF signal is used as trigger output (TRGO).
CCDS: Capture/Compare DMA Selection.
Bit 3 0: CCx DMA request sent when CCx event occurs
1: CCx DMA requests sent when update event occurs
Bits 2:0 Reserved, always read as 0

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13.5.3 Slave mode control register (TIMx_SMCR)

Address offset: 08h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ETP ECE ETPS[1:0] ETF[3:0] MSM TS[2:0] Res. SMS[2:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ETP: External Trigger Polarity.

Bit 15 This bit selects whether ETR or ETR is used for trigger operations
0: ETR is non-inverted, active at high level or rising edge.
1: ETR is inverted, active at low level or falling edge.
ECE: External Clock enable.
This bit enables External clock mode 2.
0: External clock mode 2 disabled.
1: External clock mode 2 enabled. The counter is clocked by any active edge on the
ETRF signal.
Bit 14 Note 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with
TRGI connected to ETRF (SMS=111 and TS=111).
Note 2: It is possible to simultaneously use external clock mode 2 with the following
slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not
be connected to ETRF in this case (TS bits must not be 111).
Note 3: If external clock mode 1 and external clock mode 2 are enabled at the same
time, the external clock input is ETRF.
ETPS: External Trigger Prescaler.
External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A
prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast
external clocks.
Bits 13:12
00: Prescaler OFF.
01: ETRP frequency divided by 2.
10: ETRP frequency divided by 4.
11: ETRP frequency divided by 8.

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ETF[3:0]: External Trigger Filter.

This bit-field then defines the frequency used to sample ETRP signal and the length
of the digital filter applied to ETRP. The digital filter is made of an event counter in
which N events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS.
0001: fSAMPLING=fCK_INT, N=2.
0010: fSAMPLING=fCK_INT, N=4.
0011: fSAMPLING=fCK_INT, N=8.
0100: fSAMPLING=fDTS/2, N=6.
0101: fSAMPLING=fDTS/2, N=8.
Bits 11:8
0110: fSAMPLING=fDTS/4, N=6.
0111: fSAMPLING=fDTS/4, N=8.
1000: fSAMPLING=fDTS/8, N=6.
1001: fSAMPLING=fDTS/8, N=8.
1010: fSAMPLING=fDTS/16, N=5.
1011: fSAMPLING=fDTS/16, N=6.
1100: fSAMPLING=fDTS/16, N=8.
1101: fSAMPLING=fDTS/32, N=5.
1110: fSAMPLING=fDTS/32, N=6.
1111: fSAMPLING=fDTS/32, N=8.

MSM: Master/Slave mode.

0: No action
Bit 7 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect
synchronization between the current timer and its slaves (through TRGO). It is useful
if we want to synchronize several timers on a single external event.
TS: Trigger Selection.
This bit-field selects the trigger input to be used to synchronize the counter. Refer to
the product specification to see the connection of the internal inputs.
000: Internal Trigger 0 (ITR0). TIM1
001: Internal Trigger 1 (ITR1). TIM2
010: Internal Trigger 2 (ITR2). TIM3
Bits 6:4 011: Internal Trigger 3 (ITR3). TIM4
100: TI1 Edge Detector (TI1F_ED).
101: Filtered Timer Input 1 (TI1FP1).
110: Filtered Timer Input 2 (TI2FP2).
111: External Trigger input (ETRF).
Note: These bits must be changed only when they are not used (e.g. when SMS=000)
to avoid wrong edge detections at the transition.

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General purpose timer (TIMx) UM0306

Bit 3 Reserved, always read as 0.

SMS: Slave Mode Selection.
When external signals are selected the active edge of the trigger signal (TRGI) is
linked to the polarity selected on the external input (see Input Control register and
Control Register description.
000: Slave mode disabled - if CEN = ‘1’ then the prescaler is clocked directly by the
internal clock.
001: Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on
TI1FP1 level.
010: Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on
TI2FP2 level.
011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges
depending on the level of the other input.
Bits 2:0
100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the
counter and generates an update of the registers.
101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is
high. The counter stops (but is not reset) as soon as the trigger becomes low. Both
start and stop of the counter are controlled.
110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is
not reset). Only the start of the counter is controlled.
111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the
counter.
Note: The gated mode must not be used if TI1F_ED is selected as the trigger input
(TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the
gated mode checks the level of the trigger signal.

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UM0306 General purpose timer (TIMx)

13.5.4 DMA/Interrupt enable register (TIMx_DIER)

Address offset: 0Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4 CC3 CC2 CC1
Res. TDE Res. UDE Res. TIE Res. CC4IE CC3IE CC2IE CC1IE UIE
DE DE DE DE
rw rw rw rw rw rw rw rw rw rw rw rw

Bit 15 Reserved, always read as 0.

TDE: Trigger DMA request enable.
Bit 14 0: Trigger DMA request disabled.
1: Trigger DMA request enabled.
Bit 13 Reserved, always read as 0.
CC4DE: Capture/Compare 4 DMA request enable.
Bit 12 0: CC4 DMA request disabled.
1: CC4 DMA request enabled.
CC3DE: Capture/Compare 3 DMA request enable.
Bit 11 0: CC3 DMA request disabled.
1: CC3 DMA request enabled.
CC2DE: Capture/Compare 2 DMA request enable.
Bit 10 0: CC2 DMA request disabled.
1: CC2 DMA request enabled.
CC1DE: Capture/Compare 1 DMA request enable.
Bit 9 0: CC1 DMA request disabled.
1: CC1 DMA request enabled.
UDE: Update DMA request enable.
Bit 8 0: Update DMA request disabled.
1: Update DMA request enabled.
Bit 7 Reserved, always read as 0.
TIE: Trigger interrupt enable.
Bit 6 0: Trigger interrupt disabled.
1: Trigger interrupt enabled.
Bit 5 Reserved, always read as 0.
CC4IE: Capture/Compare 4 interrupt enable.
Bit 4 0: CC4 interrupt disabled.
1: CC4 interrupt enabled.
CC3IE: Capture/Compare 3 interrupt enable.
Bit 3 0: CC3 interrupt disabled.
1: CC3 interrupt enabled.
CC2IE: Capture/Compare 2 interrupt enable.
Bit 2 0: CC2 interrupt disabled.
1: CC2 interrupt enabled.

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General purpose timer (TIMx) UM0306

CC1IE: Capture/Compare 1 interrupt enable.

Bit 1 0: CC1 interrupt disabled.
1: CC1 interrupt enabled.
UIE: Update interrupt enable.
Bit 0 0: Update interrupt disabled.
1: Update interrupt enabled.

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UM0306 General purpose timer (TIMx)

13.5.5 Status register (TIMx_SR)

Address offset: 10h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CC4 CC3 CC2 CC1
Reserved Reserved TIF Res. CC4IF CC3IF CC2IF CC1IF UIF
OF OF OF OF
rc rc rc rc rc rc rc rc rc rc

Bit 15:13 Reserved, always read as 0.

CC4OF: Capture/Compare 4 Overcapture Flag.
Bit 12
refer to CC1OF description
CC3OF: Capture/Compare 3 Overcapture Flag.
Bit 11
refer to CC1OF description
CC2OF: Capture/Compare 2 Overcapture Flag.
Bit 10
refer to CC1OF description
CC1OF: Capture/Compare 1 Overcapture Flag.
This flag is set by hardware only when the corresponding channel is configured in
Bit 9 input capture mode. It is cleared by software by writing it to ‘0’.
0: No overcapture has been detected.
1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was
already set
Bits 8:7 Reserved, always read as 0.
TIF: Trigger interrupt Flag.
This flag is set by hardware on trigger event (active edge detected on TRGI input
when the slave mode controller is enabled in all modes but gated mode, both edges
Bit 6
in case gated mode is selected). It is cleared by software.
0: No trigger event occurred.
1: Trigger interrupt pending.

Bit 5 Reserved, always read as 0.

CC4IF: Capture/Compare 4 interrupt Flag.
Bit 4
refer to CC1IF description
CC3IF: Capture/Compare 3 interrupt Flag.
Bit 3
refer to CC1IF description
CC2IF: Capture/Compare 2 interrupt Flag.
Bit 2
refer to CC1IF description

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CC1IF: Capture/compare 1 interrupt Flag.

If channel CC1 is configured as output:
This flag is set by hardware when the counter matches the compare value, with some
exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register
description). It is cleared by software.
0: No match.
1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1
Bit 1
register.
If channel CC1 is configured as input:
This bit is set by hardware on a capture. It is cleared by software or by reading the
TIMx_CCR1 register.
0: No input capture occurred.
1: The counter value has been captured in TIMx_CCR1 register (An edge has been
detected on IC1 which matches the selected polarity).
UIF: Update interrupt flag.
This bit is set by hardware on an update event. It is cleared by software.
0: No update occurred.
1: Update interrupt pending. This bit is set by hardware when the registers are
updated:
Bit 0 – At overflow or underflow regarding the repetition down-counter value (update if
REP_CNT=0) and if the UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if
URS=0 and UDIS=0 in the TIMx_CR1 register.
– When CNT is reinitialized by a trigger event (refer to the synchro control register
description), if URS=0 and UDIS=0 in the TIMx_CR1 register.

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UM0306 General purpose timer (TIMx)

13.5.6 Event generation register (TIMx_EGR)

Address offset: 14h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TG Res. CC4G CC3G CC2G CC1G UG

w w w w w w

Bits 15:7 Reserved, always read as 0.

TG: Trigger generation.
This bit is set by software in order to generate an event, it is automatically cleared by
Bit 6 hardware.
0: No action.
1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can
occur if enabled.
Bit 5 Reserved, always read as 0.
CC4G: Capture/compare 4 generation.
Bit 4
refer to CC1G description
CC3G: Capture/compare 3 generation.
Bit 3
refer to CC1G description
CC2G: Capture/compare 2 generation.
Bit 2
refer to CC1G description
CC1G: Capture/compare 1 generation.
This bit is set by software in order to generate an event, it is automatically cleared by
hardware.
0: No action.
1: A capture/compare event is generated on channel 1:
Bit 1 If channel CC1 is configured as output:
CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled.
If channel CC1 is configured as input:
The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag
is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag
is set if the CC1IF flag was already high.
UG: Update generation.
This bit can be set by software, it is automatically cleared by hardware.
0: No action.
Bit 0 1: Re-initialize the counter and generates an update of the registers. Note that the
prescaler counter is cleared too (anyway the prescaler ratio is not affected). The
counter is cleared if the center-aligned mode is selected or if DIR=0 (up-counting),
else it takes the auto-reload value (TIMx_ARR) if DIR=1 (down-counting).

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General purpose timer (TIMx) UM0306

13.5.7 Capture/compare mode register 1 (TIMx_CCMR1)

Address offset: 18h
Reset value: 0000h
The channels can be used in input (capture mode) or in output (compare mode). The
direction of a channel is defined by configuring the corresponding CCxS bits. All the other
bits of this register have a different function in input and in output mode. For a given bit,
OCxx describes its function when the channel is configured in output, ICxx describes its
function when the channel is configured in input. So you must take care that the same bit
can have a different meaning for the input stage and for the output stage.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC2 OC2 OC2 OC1 OC1 OC1
OC2M[2:0] OC1M[2:0]
CE PE FE CC2S[1:0] CE PE FE CC1S[1:0]
IC2F[3:0] IC2PSC[1:0] IC1F[3:0] IC1PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output compare mode:

Bit 15 OC2CE: Output Compare 2 Clear Enable
Bits 14:12 OC2M[2:0]: Output Compare 2 Mode.
Bit 11 OC2PE: Output Compare 2 Preload enable.
Bit 10 OC2FE: Output Compare 2 Fast enable.
CC2S[1:0]: Capture/Compare 2 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
Bits 9:8 10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in
TIMx_CCER).
OC1CE: Output Compare 1Clear Enable
OC1CE: Output Compare 1 Clear Enable
Bit 7
0: OC1Ref is not affected by the ETRF input
1: OC1Ref is cleared as soon as a High level is detected on ETRF input

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UM0306 General purpose timer (TIMx)

OC1M: Output Compare 1 Mode.

These bits define the behavior of the output reference signal OC1REF from which
OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active
level depends on CC1P and CC1NP bits.
000: Frozen - The comparison between the output compare register TIMx_CCR1 and
the counter TIMx_CNT has no effect on the outputs.
001: Set channel 1 to active level on match. OC1REF signal is forced high when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the
counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1).
011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.
100: Force inactive level - OC1REF is forced low.
Bits 6:4 101: Force active level - OC1REF is forced high.
110: PWM mode 1 - In up-counting, channel 1 is active as long as
TIMx_CNT<TIMx_CCR1 else inactive. In down-counting, channel 1 is inactive
(OC1REF=‘0’) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=’1’).
111: PWM mode 2 - In up-counting, channel 1 is inactive as long as
TIMx_CNT<TIMx_CCR1 else active. In down-counting, channel 1 is active as long as
TIMx_CNT>TIMx_CCR1 else inactive.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
Note 2: In PWM mode 1 or 2, the OCREF level changes only when the result of the
comparison changes or when the output compare mode switches from “frozen” mode
to “PWM” mode.
OC1PE: Output Compare 1 Preload enable.
0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime,
the new value is taken in account immediately.
1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the
preload register. TIMx_CCR1 preload value is loaded in the active register at each
Bit 3 update event.
Note 1: These bits can not be modified as long as LOCK level 3 has been programmed
(LOCK bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in
output).
Note 2: The PWM mode can be used without validating the preload register only in one
pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed.

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General purpose timer (TIMx) UM0306

OC1FE: Output Compare 1 Fast enable.

This bit is used to accelerate the effect of an event on the trigger in input on the CC
output.
0: CC1 behaves normally depending on counter and CCR1 values even when the
trigger is ON. The minimum delay to activate CC1 output when an edge occurs on
Bit 2 the trigger input is 5 clock cycles.
1: An active edge on the trigger input acts like a compare match on CC1 output.
Then, OC is set to the compare level independently from the result of the
comparison. Delay to sample the trigger input and to activate CC1 output is reduced
to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2
mode.
CC1S: Capture/Compare 1 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
Bits 1:0 10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in
TIMx_CCER).

Input capture mode

Bits 15:12 IC2F: Input Capture 2 Filter.
Bits 11:10 IC2PSC[1:0]: Input Capture 2 Prescaler.
CC2S: Capture/Compare 2 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC2 channel is configured as output.
01: CC2 channel is configured as input, IC2 is mapped on TI2.
Bits 9:8 10: CC2 channel is configured as input, IC2 is mapped on TI1.
11: CC2 channel is configured as input, IC2 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC2S bits are writable only when the channel is OFF (CC2E = ’0’ in
TIMx_CCER).

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UM0306 General purpose timer (TIMx)

IC1F: Input Capture 1 Filter.

This bit-field defines the frequency used to sample TI1 input and the length of the
digital filter applied to TI1. The digital filter is made of an event counter in which N
events are needed to validate a transition on the output:
0000: No filter, sampling is done at fDTS.
0001: fSAMPLING=fCK_INT, N=2.
0010: fSAMPLING=fCK_INT, N=4.
0011: fSAMPLING=fCK_INT, N=8.
0100: fSAMPLING=fDTS/2, N=6.
0101: fSAMPLING=fDTS/2, N=8.
0110: fSAMPLING=fDTS/4, N=6.
Bits 7:4
0111: fSAMPLING=fDTS/4, N=8.
1000: fSAMPLING=fDTS/8, N=6.
1001: fSAMPLING=fDTS/8, N=8.
1010: fSAMPLING=fDTS/16, N=5.
1011: fSAMPLING=fDTS/16, N=6.
1100: fSAMPLING=fDTS/16, N=8.
1101: fSAMPLING=fDTS/32, N=5.
1110: fSAMPLING=fDTS/32, N=6.
1111: fSAMPLING=fDTS/32, N=8.
Note: In current silicon revision, fDTS is replaced in the formula by CK_INT when
ICxF[3:0]= 1, 2 or 3.
IC1PSC: Input Capture 1 Prescaler.
This bit-field defines the ratio of the prescaler acting on CC1 input (IC1).
The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register).
Bits 3:2 00: no prescaler, capture is done each time an edge is detected on the capture input.
01: capture is done once every 2 events.
10: capture is done once every 4 events.
11: capture is done once every 8 events.
CC1S: Capture/Compare 1 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC1 channel is configured as output.
01: CC1 channel is configured as input, IC1 is mapped on TI1.
Bits 1:0 10: CC1 channel is configured as input, IC1 is mapped on TI2.
11: CC1 channel is configured as input, IC1 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC1S bits are writable only when the channel is OFF (CC1E = ’0’ in
TIMx_CCER).

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General purpose timer (TIMx) UM0306

13.5.8 Capture/compare mode register 2 (TIMx_CCMR2)

Address offset: 1Ch
Reset value: 0000h
Refer to the above CCMR1 register description.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OC4 OC4 OC4 OC3 OC3 OC3
OC4M[2:0] OC3M[2:0]
CE PE FE CC4S[1:0] CE. PE FE CC3S[1:0]
IC4F[3:0] IC4PSC[1:0] IC3F[3:0] IC3PSC[1:0]
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Output Compare mode

Bit 15 OC4CE: Output Compare 4 Clear Enable
Bits 14:12 OC4M: Output Compare 4 Mode.
Bit 11 OC4PE: Output Compare 4 Preload enable.
Bit 10 OC4FE: Output Compare 4 Fast enable.
CC4S: Capture/Compare 4 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
Bits 9:8 10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in
TIMx_CCER).
Bit 7 OC3CE: Output Compare 3 Clear Enable
Bits 6:4 OC3M: Output Compare 3 Mode.
Bit 3 OC3PE: Output Compare 3 Preload enable.
Bit 2 OC3FE: Output Compare 3 Fast enable.
CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
Bits 1:0 10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in
TIMx_CCER).

Input capture mode

Bits 15:12 IC4F: Input Capture 4 Filter.
Bits 11:10 IC4PSC: Input Capture 4 Prescaler.

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CC4S: Capture/Compare 4 Selection.

This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC4 channel is configured as output.
01: CC4 channel is configured as input, IC4 is mapped on TI4.
Bits 9:8 10: CC4 channel is configured as input, IC4 is mapped on TI3.
11: CC4 channel is configured as input, IC4 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC4S bits are writable only when the channel is OFF (CC4E = ’0’ in
TIMx_CCER).
Bits 7:4 IC3F: Input Capture 3 Filter.
Bits 3:2 IC3PSC: Input Capture 3 Prescaler.
CC3S: Capture/Compare 3 Selection.
This bit-field defines the direction of the channel (input/output) as well as the used
input.
00: CC3 channel is configured as output.
01: CC3 channel is configured as input, IC3 is mapped on TI3.
Bits 1:0 10: CC3 channel is configured as input, IC3 is mapped on TI4.
11: CC3 channel is configured as input, IC3 is mapped on TRGI. This mode is
working only if an internal trigger input is selected through TS bit (TIMx_SMCR
register)
Note: CC3S bits are writable only when the channel is OFF (CC3E = ’0’ in
TIMx_CCER).

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General purpose timer (TIMx) UM0306

13.5.9 Capture/compare enable register (TIMx_CCER)

Address offset: 20h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved CC4P CC4E Reserved CC3P CC3E Reserved CC2P CC2E Reserved CC1P CC1E

rw rw rw rw rw rw rw rw

Bits 15:14 Reserved, always read as 0.

CC4P: Capture/Compare 4 output Polarity.
Bit 13
refer to CC1P description
CC4E: Capture/Compare 4 output enable.
Bit 12
refer to CC1E description
Bits 11:10 Reserved, always read as 0.
CC3P: Capture/Compare 3 output Polarity.
Bit 9
refer to CC1P description
CC3E: Capture/Compare 3 output enable.
Bit 8
refer to CC1E description
Bits 7:6 Reserved, always read as 0.
CC2P: Capture/Compare 2 output Polarity.
Bit 5
refer to CC1P description
CC2E: Capture/Compare 2 output enable.
Bit 4
refer to CC1E description
Bits 3:2 Reserved, always read as 0.
CC1P: Capture/Compare 1 output Polarity.
CC1 channel configured as output:
0: OC1 active high.
1: OC1 active low.
Bit 1 CC1 channel configured as input:
This bit selects whether IC1 or IC1 is used for trigger or capture operations.
0: non-inverted: capture is done on a rising edge of IC1. When used as external
trigger, IC1 is non-inverted.
1: inverted: capture is done on a falling edge of IC1. When used as external trigger,
IC1 is inverted.
CC1E: Capture/Compare 1 output enable.
CC1 channel configured as output:
0: Off - OC1 is not active.
1: On - OC1 signal is output on the corresponding output pin.
Bit 0 CC1 channel configured as input:
This bit determines if a capture of the counter value can actually be done into the
input capture/compare register 1 (TIMx_CCR1) or not.
0: Capture disabled.
1: Capture enabled.

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UM0306 General purpose timer (TIMx)

Table 40. Output control bit for standard OCx channels

CCxE bit OCx output state
0 Output Disabled (OCx=0, OCx_EN=0)
1 OCx=OCxREF + Polarity, OCx_EN=1

Note: The state of the external I/O pins connected to the standard OCx channels depends on the
OCx channel state and the GPIO and AFIO registers.

13.5.10 Counter (TIMx_CNT)

Address offset: 24h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CNT[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 15:0 CNT[15:0]: Counter Value.

13.5.11 Prescaler (TIMx_PSC)

Address offset: 28h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PSC[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

PSC[15:0]: Prescaler Value.

The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
Bits 15:0
PSC contains the value to be loaded in the active prescaler register at each update
event.

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13.5.12 Auto-reload register (TIMx_ARR)

Address offset: 2Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ARR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

ARR[15:0]: Prescaler Value.

ARR is the value to be loaded in the actual auto-reload register.
Bits 15:0 Refer to the Section 13.4.1: Time base unit on page 222 for more details about ARR
update and behavior.
The counter is blocked while the auto-reload value is null.

13.5.13 Capture/compare register 1 (TIMx_CCR1)

Address offset: 34h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR1[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR1[15:0]: Capture/Compare 1 Value).

If channel CC1 is configured as output:
CCR1 is the value to be loaded in the actual capture/compare 1 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1
Bits 15:0 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC1 output.

If channel CC1is configured as input:

CCR1 is the counter value transferred by the last input capture 1 event (IC1).

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13.5.14 Capture/compare register 2 (TIMx_CCR2)

Address offset: 38h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR2[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR2[15:0]: Capture/Compare 2 Value.

If channel CC2 is configured as output:
CCR2 is the value to be loaded in the actual capture/compare 2 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2
Bits 15:0 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC2 output.

If channel CC2 is configured as input:

CCR2 is the counter value transferred by the last input capture 2 event (IC2).

13.5.15 Capture/compare register 3 (TIMx_CCR3)

Address offset: 3Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR3[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR3[15:0]: Capture/Compare Value.

If channel CC3 is configured as output:
CCR3 is the value to be loaded in the actual capture/compare 3 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3
Bits 15:0 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC3 output.

If channel CC3is configured as input:

CCR3 is the counter value transferred by the last input capture 3 event (IC3).

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13.5.16 Capture/compare register 4 (TIMx_CCR4)

Address offset: 40h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CCR4[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CCR4[15:0]: Capture/Compare Value.

1/ if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload
value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4
Bits 15:0 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4
register when an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.

2/ if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):

CCR4 is the counter value transferred by the last input capture 4 event (IC4).

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13.5.17 DMA control register (TIMx_DCR)

Address offset: 48h
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved DBL[4:0] Reserved DBA[4:0]

rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, always read as 0

DBL[4:0]: DMA Burst Length.
This 5-bits vector defines the length of DMA transfers in burst mode (the timer
recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR
address), i.e. the number of bytes to be transferred.
Bits 12:8 00000: 1 byte,
00001: 2 bytes,
00010: 3 bytes,
...
10001: 18 bytes.
Bits 7:5 Reserved, always read as 0
DBA[4:0]: DMA Base Address.
This 5-bit vector defines the base-address for DMA transfers in burst mode (when
read/write access are done through the TIMx_DMAR address). DBA is defined as an
offset starting from the address of the TIMx_CR1 register.
Bits 4:0 Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...

13.5.18 DMA address for burst mode (TIMx_DMAR)

Address offset: 4Ch
Reset value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMAB[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

DMAB[15:0]: DMA register for burst accesses.

A read or write access to the DMAR register accesses the register located at the
address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
Bits 15:0
TIMx_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in the TIMx_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on
the length of the transfer DBL in the TIMx_DCR register.

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13.6 TIMx register map

TIMx registers are mapped as 16-bit addressable registers as described in the table below:

Table 41. TIMx - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
ARPE

UDIS
OPM
CKD CMS

CEN
URS
DIR
TIMx_CR1
00h Reserved [1:0] [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0

CCDS
TI1S
TIMx_CR2 MMS[2:0]
04h Reserved Reserved
Reset Value 0 0 0 0 0

CC3IE Reserved
MSM
ETPS

ECE
ETP
TIMx_SMCR ETF[3:0] TS[2:0] SMS[2:0]
08h Reserved [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CC4DE
CC3DE
CC2DE
CC1DE
Reserved

Reserved

Reserved Reserved Reserved

CC4IE

CC2IE
CC1IE
UDE
TDE

UIE
TIE
TIMx_DIER
0Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

CC4OF
CC3OF
CC2OF
CC1OF

Reserved

CC4IF
CC3IF
CC2IF
CC1IF
UIF
TIF
TIMx_SR
10h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0

CC4G
CC3G
CC2G
CC1G
UG
TG
TIMx_EGR
14h Reserved
Reset Value 0 0 0 0 0 0
TIMx_CCMR1
OC2CE

OC1CE
OC2PE

OC1PE
OC2FE

OC1FE
OC2M CC2S OC1M CC1S
Output Compare
Reserved [2:0] [1:0] [2:0] [1:0]
mode
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
18h
TIMx_CCMR1 IC2 IC1
CC2S CC1S
Input Capture IC2F[3:0] PSC IC1F[3:0] PSC
Reserved [1:0] [1:0]
mode [1:0] [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TIMx_CCMR2
OC3CE
OC4PE

OC3PE
OC4FE

OC3FE
O24CE

OC4M CC4S OC3M CC3S

Output Compare
Reserved [2:0] [1:0] [2:0] [1:0]
mode
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1Ch
TIMx_CCMR2 IC4 IC3
CC4S CC3S
Input Capture IC4F[3:0] PSC IC3F[3:0] PSC
Reserved [1:0] [1:0]
mode [1:0] [1:0]
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved

Reserved

Reserved
CC4P
CC4E

CC3P
CC3E

CC2P
CC2E

CC1P
CC1E
TIMx_CCER
20h Reserved
Reset Value 0 0 0 0 0 0 0 0

TIMx_CNT CNT[15:0]
24h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_PSC PSC[15:0]
28h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_ARR ARR[15:0]
2Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

30h Reserved

TIMx_CCR1 CCR1[15:0]
34h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 41. TIMx - register map and reset values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
TIMx_CCR2 CCR2[15:0]
38h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCR3 CCR3[15:0]
3Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMx_CCR4 CCR4[15:0]
40h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

44h Reserved

TIMx_DCR DBL[4:0] DBA[4:0]

48h Reserved Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0

TIMx_DMAR DMAB[15:0]
4Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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Controller area network (bxCAN) UM0306

14 Controller area network (bxCAN)

14.1 Introduction
The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It
supports the CAN protocols version 2.0A and B. It has been designed to manage a high
number of incoming messages efficiently with a minimum CPU load. It also meets the
priority requirements for transmit messages.
For safety-critical applications, the CAN controller provides all hardware functions for
supporting the CAN Time Triggered Communication option.

14.2 Main features

● Supports CAN protocol version 2.0 A, B Active
● Bit rates up to 1 Mbit/s
● Supports the Time Triggered Communication option
Transmission
● Three transmit mailboxes
● Configurable transmit priority
● Time Stamp on SOF transmission
Reception
● Two receive FIFOs with three stages
● 14 scalable filter banks/CAN cell - shared between CAN cells
● Identifier list feature
● Configurable FIFO overrun
● Time Stamp on SOF reception
Time Triggered Communication Option
● Disable automatic retransmission mode
● 16-bit free running timer
● Configurable timer resolution
● Time Stamp sent in last two data bytes
Management
● Maskable interrupts
● Software-efficient mailbox mapping at a unique address space

14.3 General description

In today’s CAN applications, the number of nodes in a network is increasing and often
several networks are linked together via gateways. Typically the number of messages in the
system (and thus to be handled by each node) has significantly increased. In addition to the

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application messages, Network Management and Diagnostic messages have been

introduced.
● An enhanced filtering mechanism is required to handle each type of message.
Furthermore, application tasks require more CPU time, therefore real-time constraints
caused by message reception have to be reduced.
● A receive FIFO scheme allows the CPU to be dedicated to application tasks for a long
time period without losing messages.
The standard HLP (Higher Layer Protocol) based on standard CAN drivers requires an
efficient interface to the CAN controller.

Figure 118. CAN network topology

CAN node 1

CAN node 2

CAN node n
MCU
Application

CAN
Controller

CAN CAN
Rx Tx

CAN
Transceiver

CAN CAN
High Low

CAN Bus

14.3.1 CAN 2.0B active core

The bxCAN module handles the transmission and the reception of CAN messages fully
autonomously. Standard identifiers (11-bit) and extended identifiers (29-bit) are fully
supported by hardware.

14.3.2 Control, status and configuration registers

The application uses these registers to:
● Configure CAN parameters, e.g. baud rate
● Request transmissions
● Handle receptions
● Manage interrupts
● Get diagnostic information

14.3.3 Tx mailboxes
Three transmit mailboxes are provided to the software for setting up messages. The
transmission Scheduler decides which mailbox has to be transmitted first.

14.3.4 Acceptance filters

The bxCAN provides 14 scalable/configurable identifier filter banks for selecting the
incoming messages the software needs and discarding the others.

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14.3.5 Receive FIFO

Two receive FIFOs are used by hardware to store the incoming messages. Three complete
messages can be stored in each FIFO. The FIFOs are managed completely by hardware.

Figure 119. CAN block diagram

Tx Mailboxes Receive FIFO 0 Receive FIFO 1

Master Control Mailbox 2 2 2
Master Status 1 1
Mailbox 0 Mailbox 0
Transmit Control
Mailbox 1
Transmit Status
Transmit Priority
Control/Status/Configuration

Receive FIFO Mailbox 0

Interrupt Enable
Error Status
Acceptance Filters
Error Int. Enable
13
.. .. 12
Tx Error Counter 3
2
Transmission 1
Rx Error Counter Filter 0
Scheduler
Diagnostic
Bit Timing
Filter Mode CAN 2.0B Active Core

Filter Config.

Figure 120. bxCAN operating modes

RESET

SLEEP
SLAK= 1
INAK = 0
N RQ SL
.I EE
C P
YN .I
NR
.S SL Q
P K EE
EE . AC P
.A
CK
SL .I
E EP NR
SL Q
.A
CK
NORMAL INRQ . ACK INITIALIZATION
SLAK= 0 SLAK= 0
INAK = 0 INAK = 1
INRQ . SYNC . SLEEP

Note: 1 ACK = The wait state during which hardware confirms a request by setting the INAK or
SLAK bits in the CAN_MSR register
2 SYNC = The state during which bxCAN waits until the CAN bus is idle, meaning 11
consecutive recessive bits have been monitored on CANRX

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14.4 Operating modes

bxCAN has three main operating modes: initialization, normal and SLEEP. After a
hardware reset, bxCAN is in SLEEP mode to reduce power consumption and an internal
pull-up is active on CANTX. The software requests bxCAN to enter initialization or SLEEP
mode by setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has
been entered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register
and the internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in
normal mode. Before entering normal mode bxCAN always has to synchronize on the
CAN bus. To synchronize, bxCAN waits until the CAN bus is idle, this means 11 consecutive
recessive bits have been monitored on CANRX.

14.4.1 Initialization mode

The software initialization can be done while the hardware is in Initialization mode. To enter
this mode the software sets the INRQ bit in the CAN_MCR register and waits until the
hardware has confirmed the request by setting the INAK bit in the CAN_MSR register.
To leave Initialization mode, the software clears the INQR bit. bxCAN has left Initialization
mode once the INAK bit has been cleared by hardware.
While in Initialization Mode, all message transfers to and from the CAN bus are stopped and
the status of the CAN bus output CANTX is recessive (high).
Entering Initialization Mode does not change any of the configuration registers.
To initialize the CAN Controller, software has to set up the Bit Timing (CAN_BTR) and CAN
options (CAN_MCR) registers.
To initialize the registers associated with the CAN filter banks (mode, scale, FIFO
assignment, activation and filter values), software has to set the FINIT bit (CAN_FMR). Filter
initialization also can be done outside the initialization mode.
Note: When FINIT=1, CAN reception is deactivated.
The filter values also can be modified by deactivating the associated filter activation bits (in
the CAN_FA0R register).
If a filter bank is not used, it is recommended to leave it non active (leave the corresponding
FACT bit cleared).

14.4.2 Normal mode

Once the initialization has been done, the software must request the hardware to enter
Normal mode, to synchronize on the CAN bus and start reception and transmission.
Entering Normal mode is done by clearing the INRQ bit in the CAN_MCR register and
waiting until the hardware has confirmed the request by clearing the INAK bit in the
CAN_MSR register. Afterwards, the bxCAN synchronizes with the data transfer on the CAN
bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (≡ Bus Idle)
before it can take part in bus activities and start message transfer.
The initialization of the filter values is independent from Initialization Mode but must be done
while the filter is not active (corresponding FACTx bit cleared). The filter scale and mode
configuration must be configured before entering Normal Mode.

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14.4.3 SLEEP mode (low power)

To reduce power consumption, bxCAN has a low-power mode called SLEEP mode. This
mode is entered on software request by setting the SLEEP bit in the CAN_MCR register. In
this mode, the bxCAN clock is stopped, however software can still access the bxCAN
mailboxes.
If software requests entry to initialization mode by setting the INRQ bit while bxCAN is in
SLEEP mode, it must also clear the SLEEP bit.
bxCAN can be woken up (exit SLEEP mode) either by software clearing the SLEEP bit or on
detection of CAN bus activity.
On CAN bus activity detection, hardware automatically performs the wake-up sequence by
clearing the SLEEP bit if the AWUM bit in the CAN_MCR register is set. If the AWUM bit is
cleared, software has to clear the SLEEP bit when a wake-up interrupt occurs, in order to
exit from SLEEP mode.
Note: If the wake-up interrupt is enabled (WKUIE bit set in CAN_IER register) a wake-up interrupt
will be generated on detection of CAN bus activity, even if the bxCAN automatically performs
the wake-up sequence.
After the SLEEP bit has been cleared, SLEEP mode is exited once bxCAN has
synchronized with the CAN bus, refer to Figure 120: bxCAN operating modes. The SLEEP
mode is exited once the SLAK bit has been cleared by hardware.

14.4.4 Test mode

Test mode can be selected by the SILM and LBKM bits in the CAN_BTR register. These bits
must be configured while bxCAN is in Initialization mode. Once test mode has been
selected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode.

14.4.5 Silent mode

The bxCAN can be put in Silent mode by setting the SILM bit in the CAN_BTR register.
In Silent mode, the bxCAN is able to receive valid data frames and valid remote frames, but
it sends only recessive bits on the CAN bus and it cannot start a transmission. If the bxCAN
has to send a dominant bit (ACK bit, overload flag, active error flag), the bit is rerouted
internally so that the CAN Core monitors this dominant bit, although the CAN bus may
remain in recessive state. Silent mode can be used to analyze the traffic on a CAN bus
without affecting it by the transmission of dominant bits (Acknowledge Bits, Error Frames).

Figure 121. bxCAN in silent mode

bxCAN
Tx Rx

=1

CANTX CANRX

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14.4.6 Loop back mode

The bxCAN can be set in Loop Back Mode by setting the LBKM bit in the CAN_BTR
register. In Loop Back Mode, the bxCAN treats its own transmitted messages as received
messages and stores them (if they pass acceptance filtering) in a Receive mailbox.

Figure 122. bxCAN in loop back mode

bxCAN
Tx Rx

CANTX CANRX

This mode is provided for self-test functions. To be independent of external events, the CAN
Core ignores acknowledge errors (no dominant bit sampled in the acknowledge slot of a
data / remote frame) in Loop Back Mode. In this mode, the bxCAN performs an internal
feedback from its Tx output to its Rx input. The actual value of the CANRX input pin is
disregarded by the bxCAN. The transmitted messages can be monitored on the CANTX pin.

14.4.7 Loop back combined with silent mode

It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and
SILM bits in the CAN_BTR register. This mode can be used for a “Hot Selftest”, meaning the
bxCAN can be tested like in Loop Back mode but without affecting a running CAN system
connected to the CANTX and CANRX pins. In this mode, the CANRX pin is disconnected
from the bxCAN and the CANTX pin is held recessive.

Figure 123. bxCAN in combined mode

bxCAN
Tx Rx

=1

CANTX CANRX

14.5 Functional description

14.5.1 Transmission handling

In order to transmit a message, the application must select one empty transmit mailbox, set
up the identifier, the data length code (DLC) and the data before requesting the transmission
by setting the corresponding TXRQ bit in the CAN_TIxR register. Once the mailbox has left

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empty state, the software no longer has write access to the mailbox registers. Immediately
after the TXRQ bit has been set, the mailbox enters pending state and waits to become the
highest priority mailbox, see Transmit Priority. As soon as the mailbox has the highest
priority it will be scheduled for transmission. The transmission of the message of the
scheduled mailbox will start (enter transmit state) when the CAN bus becomes idle. Once
the mailbox has been successfully transmitted, it will become empty again. The hardware
indicates a successful transmission by setting the RQCP and TXOK bits in the CAN_TSR
register.
If the transmission fails, the cause is indicated by the ALST bit in the CAN_TSR register in
case of an Arbitration Lost, and/or the TERR bit, in case of transmission error detection.

Transmit priority
By identifier:
When more than one transmit mailbox is pending, the transmission order is given by the
identifier of the message stored in the mailbox. The message with the lowest identifier value
has the highest priority according to the arbitration of the CAN protocol. If the identifier
values are equal, the lower mailbox number will be scheduled first.
By transmit request order:
The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the
CAN_MCR register. In this mode the priority order is given by the transmit request order.
This mode is very useful for segmented transmission.

Abort
A transmission request can be aborted by the user setting the ABRQ bit in the CAN_TSR
register. In pending or scheduled state, the mailbox is aborted immediately. An abort
request while the mailbox is in transmit state can have two results. If the mailbox is
transmitted successfully the mailbox becomes empty with the TXOK bit set in the
CAN_TSR register. If the transmission fails, the mailbox becomes scheduled, the
transmission is aborted and becomes empty with TXOK cleared. In all cases the mailbox
will become empty again at least at the end of the current transmission.

Non-automatic retransmission mode

This mode has been implemented in order to fulfil the requirement of the Time Triggered
Communication option of the CAN standard. To configure the hardware in this mode the
NART bit in the CAN_MCR register must be set.
In this mode, each transmission is started only once. If the first attempt fails, due to an
arbitration loss or an error, the hardware will not automatically restart the message
transmission.
At the end of the first transmission attempt, the hardware considers the request as
completed and sets the RQCP bit in the CAN_TSR register. The result of the transmission is
indicated in the CAN_TSR register by the TXOK, ALST and TERR bits.

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Figure 124. Transmit mailbox states

EMPTY
RQCP=X
TXOK=X
TXRQ=1
TME = 1

PENDING
RQCP=0 Mailbox has
TXOK=0 highest priority
ABRQ=1
TME = 0

Mailbox does not

have highest priority
EMPTY SCHEDULED
RQCP=1 ABRQ=1 RQCP=0
TXOK=0 TXOK=0
TME = 1 TME = 0
CAN Bus = IDLE

Transmit failed * NART TRANSMIT Transmit failed * NART

RQCP=0
TXOK=0
TME = 0

EMPTY
Transmit succeeded
RQCP=1
TXOK=1
TME = 1

14.5.2 Time triggered communication mode

In this mode, the internal counter of the CAN hardware is activated and used to generate the
Time Stamp value stored in the CAN_RDTxR/CAN_TDTxR registers, respectively (for Rx
and Tx mailboxes). The internal counter is captured on the sample point of the Start Of
Frame bit in both reception and transmission.

14.5.3 Reception handling

For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In
order to save CPU load, simplify the software and guarantee data consistency, the FIFO is
managed completely by hardware. The application accesses the messages stored in the
FIFO through the FIFO output mailbox.

Valid message
A received message is considered as valid when it has been received correctly according to
the CAN protocol (no error until the last but one bit of the EOF field) and It passed through
the identifier filtering successfully, see Section 14.5.4: Identifier filtering.

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Figure 125. Receive FIFO states

EMPTY
FMP=0x00 Valid Message
FOVR=0 Received

PENDING_1
Release FMP=0x01
Mailbox FOVR=0

Release Valid Message

Mailbox Received
RFOM=1

PENDING_2
FMP=0x10
FOVR=0

Release Valid Message

Mailbox Received
RFOM=1

PENDING_3
FMP=0x11 Valid Message
FOVR=0 Received

OVERRUN
Release FMP=0x11
Mailbox FOVR=1
RFOM=1

Valid Message
Received

FIFO management
Starting from the empty state, the first valid message received is stored in the FIFO which
becomes pending_1. The hardware signals the event setting the FMP[1:0] bits in the CRFR
register to the value 01b. The message is available in the FIFO output mailbox. The software
reads out the mailbox content and releases it by setting the RFOM bit in the CRFR register.
The FIFO becomes empty again. If a new valid message has been received in the
meantime, the FIFO stays in pending_1 state and the new message is available in the
output mailbox.
If the application does not release the mailbox, the next valid message will be stored in the
FIFO which enters pending_2 state (FMP[1:0] = 10b). The storage process is repeated for
the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 11b). At this
point, the software must release the output mailbox by setting the RFOM bit, so that a
mailbox is free to store the next valid message. Otherwise the next valid message received
will cause a loss of message.
Refer also to Section 14.5.5: Message storage

Overrun
Once the FIFO is in pending_3 state (i.e. the three mailboxes are full) the next valid
message reception will lead to an overrun and a message will be lost. The hardware

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signals the overrun condition by setting the FOVR bit in the CRFR register. Which message
is lost depends on the configuration of the FIFO:
● If the FIFO lock function is disabled (RFLM bit in the CAN_MCR register cleared) the
last message stored in the FIFO will be overwritten by the new incoming message. In
this case the latest messages will be always available to the application.
● If the FIFO lock function is enabled (RFLM bit in the CAN_MCR register set) the most
recent message will be discarded and the software will have the three oldest messages
in the FIFO available.

Reception related interrupts

Once a message has been stored in the FIFO, the FMP[1:0] bits are updated and an
interrupt request is generated if the FMPIE bit in the CAN_IER register is set.
When the FIFO becomes full (i.e. a third message is stored) the FULL bit in the CRFR
register is set and an interrupt is generated if the FFIE bit in the CAN_IER register is set.
On overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in
the CAN_IER register is set.

14.5.4 Identifier filtering

In the CAN protocol the identifier of a message is not associated with the address of a node
but related to the content of the message. Consequently a transmitter broadcasts its
message to all receivers. On message reception a receiver node decides - depending on
the identifier value - whether the software needs the message or not. If the message is
needed, it is copied into the SRAM. If not, the message must be discarded without
intervention by the software.
To fulfil this requirement, the bxCAN Controller provides 14 configurable and scalable
filterbanks (13-0) to the application, in order to receive only the messages the software
needs. This hardware filtering saves CPU resources which would be otherwise needed to
perform filtering by software. Each filter bank x consists of two 32-bit registers, CAN_FxR0
and CAN_FxR1.

Scalable width
To optimize and adapt the filters to the application needs, each filter bank can be scaled
independently. Depending on the filter scale a filter bank provides:
● One 32-bit filter for the STDID[10:0], EXTID[17:0], IDE and RTR bits.
● Two 16-bit filters for the STDID[10:0], RTR, IDE and EXTID[17:15] bits.
Refer to Figure 126.
Furthermore, the filters can be configured in mask mode or in identifier list mode.

Mask mode
In mask mode the identifier registers are associated with mask registers specifying which
bits of the identifier are handled as “must match” or as “don’t care”.

Identifier list mode

In identifier list mode, the mask registers are used as identifier registers. Thus instead of
defining an identifier and a mask, two identifiers are specified, doubling the number of single

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identifiers. All bits of the incoming identifier must match the bits specified in the filter
registers.

Filter bank scale and mode configuration

The filter banks are configured by means of the corresponding CFMR register. To configure
a filter bank it must be deactivated by clearing the FACT bit in the CAN_FAR register. The
filter scale is configured by means of the corresponding FSCx bit in the CFSCR register,
refer to Figure 126. The identifier list or identifier mask mode for the corresponding
Mask/Identifier registers is configured by means of the FBMx bits in the CFMR register.
To filter a group of identifiers, configure the Mask/Identifier registers in mask mode.
To select single identifiers, configure the Mask/Identifier registers in identifier list mode.
Filters not used by the application should be left deactivated.
Each filter within a filter bank is numbered (called the Filter Number) from 0 to a maximum
dependent on the mode and the scale of each of the 14 filter banks.
Concerning the filter configuration, refer to Figure 126.

Figure 126. Filter bank scale configuration - register organization

Filter
One 32-Bit Filter - Identifier Mask Num.
FBMx = 0

ID CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR0[15:8] CAN_FxR0[7:0]

n
Mask CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0]
FSCx = 1

Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] IDE RTR 0

Two 32-Bit Filters - Identifier List

FBMx = 1

ID CAN_FxR0[31:24] CAN_FxR0[23:16] CAN_FxR0[15:8] CAN_FxR0[7:0] n

ID CAN_FxR1[31:24] CAN_FxR1[23:16] CAN_FxR1[15:8] CAN_FxR1[7:0] n+1
Mapping STID[10:3] STID[2:0] EXID[17:13] EXID[12:5] EXID[4:0] IDE RTR 0

Two 16-Bit Filters - Identifier Mask

ID CAN_FxR0[15:8] CAN_FxR0[7:0]
FBMx = 0

n
Mask CAN_FxR0[31:24] CAN_FxR0[23:16]

ID CAN_FxR1[15:8] CAN_FxR1[7:0]
n+1
Mask CAN_FxR1[31:24] CAN_FxR1[23:16]
FSCx = 0

Mapping STID[10:3] STID[2:0] RTR IDE EXID[17:15]

Four 16-Bit Filters - Identifier List

ID CAN_FxR0[15:8] CAN_FxR0[7:0] n
FBMx = 1

ID CAN_FxR0[31:24] CAN_FxR0[23:16] n+1

ID CAN_FxR1[15:8] CAN_FxR1[7:0] n+2
ID CAN_FxR1[31:24] CAN_FxR1[23:16] n+3
Mapping STID[10:3] STID[2:0] RTR IDE EXID[17:15]
Filter Bank Mode2
Filter Bank Scale
Config. Bits1

x = filter bank number

ID=Identifier
1
These bits are located in the CAN_FS0R register
2 These bits are located in the CAN_FM0R register

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Filter match index

Once a message has been received in the FIFO it is available to the application. Typically,
application data is copied into SRAM locations. To copy the data to the right location the
application has to identify the data by means of the identifier. To avoid this, and to ease the
access to the SRAM locations, the CAN controller provides a Filter Match Index.
This index is stored in the mailbox together with the message according to the filter priority
rules. Thus each received message has its associated filter match index.
The Filter Match index can be used in two ways:
● Compare the Filter Match index with a list of expected values.
● Use the Filter Match Index as an index on an array to access the data destination
location.
For non-masked filters, the software no longer has to compare the identifier.
If the filter is masked the software reduces the comparison to the masked bits only.
The index value of the filter number does not take into account the activation state of the
filter banks. In addition, two independent numbering schemes are used, one for each FIFO.
Refer to Figure 127 for an example.

Figure 127. Example of filter numbering

Filter FIFO0 Filter Filter FIFO1 Filter
Bank Num. Bank Num.
0 0
0 ID List (32-bit) 2 ID Mask (16-bit)
1 1

2
1 ID Mask (32-bit) 2 4 ID List (32-bit) 3

3
4 Deactivated 4
3 ID List (16-bit) 7
5 ID Mask (16-bit) 5
6

Deactivated 7 6
5 8 ID Mask (16-bit)
ID List (32-bit) 8 7

8
9 Deactivated 9
6 ID Mask (16-bit) 10 10
10 ID List (16-bit)
11

11 12
9 ID List (32-bit) 11 ID List (32-bit)
12 13

13 ID Mask (32-bit) 13 12 ID Mask (32-bit) 14

ID=Identifier

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Filter priority rules

Depending on the filter combination it may occur that an identifier passes successfully
through several filters. In this case the filter match value stored in the receive mailbox is
chosen according to the following priority rules:
● A 32-bit filter takes priority over a 16-bit filter.
● For filters of equal scale, priority is given to the Identifier List mode over the Identifier
Mask mode
● For filters of equal scale and mode, priority is given by the filter number (the lower the
number, the higher the priority).

Figure 128. Filtering mechanism - example

Example of 3 filter banks in 32-bit Unidentified List mode and
the remaining in 32-bit Identifier Mask mode
Message Received
Identifier Ctrl Data

Filter bank
Num Receive FIFO
Identifier 0
0
Identifier 1 Message
Identifier List

Identifier 4 Identifier #4 Match Stored

2

Identifier 5
Identifier & Mask

1
Identifier
Mask 2 Filter number stored in the
FMI
Filter Match Index field
within the CAN_RDTxR
Identifier register
4 3
Mask
No Match
Found

Message Discarded

The example above shows the filtering principle of the bxCAN. On reception of a message,
the identifier is compared first with the filters configured in identifier list mode. If there is a
match, the message is stored in the associated FIFO and the index of the matching filter is
stored in the Filter Match Index. As shown in the example, the identifier matches with
Identifier #2 thus the message content and FMI 2 is stored in the FIFO.
If there is no match, the incoming identifier is then compared with the filters configured in
mask mode.
If the identifier does not match any of the identifiers configured in the filters, the message is
discarded by hardware without disturbing the software.

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14.5.5 Message storage

The interface between the software and the hardware for the CAN messages is
implemented by means of mailboxes. A mailbox contains all information related to a
message; identifier, data, control, status and time stamp information.

Transmit mailbox
The software sets up the message to be transmitted in an empty transmit mailbox. The
status of the transmission is indicated by hardware in the CAN_TSR register.

Table 42. Transmit mailbox mapping

Offset to Transmit Mailbox base
Register Name
address

0 CAN_TIxR
4 CAN_TDTxR
8 CAN_TDLxR
12 CAN_TDHxR

Receive mailbox
When a message has been received, it is available to the software in the FIFO output
mailbox. Once the software has handled the message (e.g. read it) the software must
release the FIFO output mailbox by means of the RFOM bit in the CRFR register to make
the next incoming message available. The filter match index is stored in the MFMI field of
the CAN_RDTxR register. The 16-bit time stamp value is stored in the TIME[15:0] field of
CAN_RDTxR.

Table 43. Receive mailbox mapping

Offset to Receive Mailbox base
Register Name
address (bytes)

0 CAN_RIxR
4 CAN_RDTxR
8 CAN_RDLxR
12 CAN_RDHxR

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Figure 129. CAN error state diagram

When TEC or REC > 127

ERROR ACTIVE
ERROR PASSIVE

When TEC and REC < 128,

When 128 * 11 recessive bits occur: When TEC > 255

BUS OFF

14.5.6 Error management

The error management as described in the CAN protocol is handled entirely by hardware
using a Transmit Error Counter (TEC value, in CAN_ESR register) and a Receive Error
Counter (REC value, in the CAN_ESR register), which get incremented or decremented
according to the error condition. For detailed information about TEC and REC management,
please refer to the CAN standard.
Both of them may be read by software to determine the stability of the network.
Furthermore, the CAN hardware provides detailed information on the current error status in
CAN_ESR register. By means of the CAN_IER register (ERRIE bit, etc.), the software can
configure the interrupt generation on error detection in a very flexible way.

Bus-Off recovery
The Bus-Off state is reached when TEC is greater than 255, this state is indicated by BOFF
bit in CAN_ESR register. In Bus-Off state, the bxCAN is no longer able to transmit and
receive messages.
Depending on the ABOM bit in the CAN_MCR register bxCAN will recover from Bus-Off
(become error active again) either automatically or on software request. But in both cases
the bxCAN has to wait at least for the recovery sequence specified in the CAN standard
(128 occurrences of 11 consecutive recessive bits monitored on CANRX).
If ABOM is set, the bxCAN will start the recovering sequence automatically after it has
entered Bus-Off state.
If ABOM is cleared, the software must initiate the recovering sequence by requesting
bxCAN to enter and to leave initialization mode.
Note: In initialization mode, bxCAN does not monitor the CANRX signal, therefore it cannot
complete the recovery sequence. To recover, bxCAN must be in normal mode.

14.5.7 Bit timing

The bit timing logic monitors the serial bus-line and performs sampling and adjustment of
the sample point by synchronizing on the start-bit edge and resynchronizing on the following
edges.

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Its operation may be explained simply by splitting nominal bit time into three segments as
follows:
● Synchronization segment (SYNC_SEG): a bit change is expected to occur within this
time segment. It has a fixed length of one time quantum (1 x tCAN).
● Bit segment 1 (BS1): defines the location of the sample point. It includes the
PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable
between 1 and 16 time quanta but may be automatically lengthened to compensate for
positive phase drifts due to differences in the frequency of the various nodes of the
network.
● Bit segment 2 (BS2): defines the location of the transmit point. It represents the
PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8
time quanta but may also be automatically shortened to compensate for negative
phase drifts.
The resynchronization Jump Width (SJW) defines an upper bound to the amount of
lengthening or shortening of the bit segments. It is programmable between 1 and 4 time
quanta.
A valid edge is defined as the first transition in a bit time from dominant to recessive bus
level provided the controller itself does not send a recessive bit.
If a valid edge is detected in BS1 instead of SYNC_SEG, BS1 is extended by up to SJW so
that the sample point is delayed.
Conversely, if a valid edge is detected in BS2 instead of SYNC_SEG, BS2 is shortened by
up to SJW so that the transmit point is moved earlier.
As a safeguard against programming errors, the configuration of the Bit Timing Register
(CAN_BTR) is only possible while the device is in STANDBY mode.
Note: For a detailed description of the CAN bit timing and resynchronization mechanism, please
refer to the ISO 11898 standard.

Figure 130. Bit timing

NOMINAL BIT TIME

SYNC_SEG BIT SEGMENT 1 (BS1) BIT SEGMENT 2 (BS2)

1 x tq tBS1 tBS2

SAMPLE POINT TRANSMIT POINT

1
BaudRate = ----------------------------------------------
NominalBitTime
NominalBitTime = 1 × t q + t BS1 + t BS2
with:
tBS1 = tq x (TS1[3:0] + 1) ,
tBS2 = tq x (TS2[2:0] + 1),
tq = ( BRP[9:0] + 1 ) x tPCLK
where tq refers to the Time quantum
tPCLK = time period of the APB clock,
BRP[9:0], TS1[3:0] and TS2[2:0] are defined in the CAN_BTR Register.

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Figure 131. CAN frames

Inter-Frame Space
Inter-Frame Space Data Frame (Standard identifier) or Overload Frame
44 + 8 * N
Arbitration Field Ctrl Field Data Field CRC Field Ack Field
2
12 6 8*N 16 7

ID DLC CRC EOF

IDE
r0
RTR
SOF

ACK
Inter-Frame Space
Inter-Frame Space Data Frame (Extended Identifier) or Overload Frame
64 + 8 * N

Std Arbitr. Field Ext Arbitr. Field Ctrl Field Data Field CRC Field Ack Field
2
12 20 6 8*N 16 7

ID DLC CRC EOF

r1
RTR
IDE

r0
SRR
SOF

ACK
Inter-Frame Space
Inter-Frame Space Remote Frame or Overload Frame
44
Arbitration Field Ctrl Field CRC Field Ack Field
2
12 6 16 7

ID DLC CRC EOF

IDE
r0
RTR
SOF

ACK
Data Frame or Inter-Frame Space
Remote Frame Error Frame or Overload Frame Notes:
Error Flag Echo Error Delimiter • 0 <= N <= 8
Flag
6 ≤6 8 • SOF = Start Of Frame
• ID = Identifier
• RTR = Remote Transmission Request
Data Frame or • IDE = Identifier Extension Bit
Any Frame Inter-Frame Space Remote Frame • r0 = Reserved Bit
Suspend • DLC = Data Length Code
Intermission Transmission Bus Idle
3 • CRC = Cyclic Redundancy Code
8
• Error flag: 6 dominant bits if node is error

End Of Frame or active else 6 recessive bits.

Error Delimiter or Inter-Frame Space • Suspend transmission: applies to error
Overload Delimiter Overload Frame or Error Frame passive nodes only.
Overload Overload Overload • EOF = End of Frame
Flag Echo Delimiter
6 ≤6 8 • ACK = Acknowledge bit
• Ctrl = Control

14.6 Interrupts
Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently
enabled or disabled by means of the CAN Interrupt Enable Register (CAN_IER).

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Figure 132. Event flags and interrupt generation

CAN_IER
TRANSMIT
INTERRUPT
RQCP0 TMEIE
CAN_TSR RQCP1 + &
RQCP2

FMPIE0
FMP0
& FIFO 0
INTERRUPT
FFIE0
CAN_RF0R FULL0
& +
FOVIE0
FOVR0
&

FMPIE1
FMP1
& FIFO 1
INTERRUPT
FFIE1
CAN_RF1R FULL1
& +
FOVIE1
FOVR1
&

ERRIE

EWGIE
EWGF &
EPVIE
CAN_ESR EPVF & &
BOFIE
+
ERRI
BOFF & CAN_MSR STATUS CHANGE
ERROR
LECIE
1≤LEC≤6 & INTERRUPT

WKUIE
WKUI
&
CAN_MSR
SLKIE
SLAKI
&

● The transmit interrupt can be generated by the following events:

– Transmit mailbox 0 becomes empty, RQCP0 bit in the CAN_TSR register set.
– Transmit mailbox 1 becomes empty, RQCP1 bit in the CAN_TSR register set.
– Transmit mailbox 2 becomes empty, RQCP2 bit in the CAN_TSR register set.
● The FIFO 0 interrupt can be generated by the following events:
– Reception of a new message, FMP0 bits in the CAN_RF0R register are not ‘00’.
– FIFO0 full condition, FULL0 bit in the CAN_RF0R register set.
– FIFO0 overrun condition, FOVR0 bit in the CAN_RF0R register set.
● The FIFO 1 interrupt can be generated by the following events:
– Reception of a new message, FMP1 bits in the CAN_RF1R register are not ‘00’.
– FIFO1 full condition, FULL1 bit in the CAN_RF1R register set.
– FIFO1 overrun condition, FOVR1 bit in the CAN_RF1R register set.

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● The error and status change interrupt can be generated by the following events:
– Error condition, for more details on error conditions please refer to the CAN Error
Status register (CAN_ESR).
– Wake-up condition, SOF monitored on the CAN Rx signal.
– Entry into SLEEP mode.

14.7 Register access protection

Erroneous access to certain configuration registers can cause the hardware to temporarily
disturb the whole CAN network. Therefore the CAN_BTR register can be modified by
software only while the CAN hardware is in initialization mode.
Although the transmission of incorrect data will not cause problems at the CAN network
level, it can severely disturb the application. A transmit mailbox can be only modified by
software while it is in empty state, refer to Figure 124: Transmit mailbox states.
The filters values can be modified either deactivating the associated filter banks or by setting
the FINIT bit. Moreover, the modification of the filter configuration (scale, mode and FIFO
assignment) in CAN_FMxR, CAN_FSxR and CAN_FFAR registers can only be done when
the filter initialization mode is set (FINIT=1) in the CAN_FMR register.

14.8 CAN register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

14.8.1 Control and status registers

CAN master control register (CAN_MCR)
Address Offset: 00h
Reset value: 00010002h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ

rw rw rw rw rw rw rw rw

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved DBF

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RE
Reserved TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ
SET

rs rw rw rw rw rw rw rw rw

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Bits 31:16 Reserved, forced by hardware to 0.

DBF: (non user) - Debug Freeze (ENFCT)
0: CAN working during debug break activated
Bit 16
1: CAN reception/transmission frozen during debug. Reception FIFOs can still be
accessed/controlled normally.
RESET: bxCAN software master reset
0: Normal operation.
Bit 15 1: Force a master reset of the bxCAN -> SLEEP mode activated after reset (FMP
bits and CAN_MCR register are initialized to the reset values). This bit is
automatically reset to 0.
Bits 14:8 Reserved, forced by hardware to 0.
Bits 31:8 Reserved, forced by hardware to 0.
TTCM: Time Triggered Communication Mode
0: Time Triggered Communication mode disabled.
Bit 7 1: Time Triggered Communication mode enabled
Note: For more information on Time Triggered Communication mode, please refer to
Section 14.5.2: Time triggered communication mode.
ABOM: Automatic Bus-Off Management
This bit controls the behavior of the CAN hardware on leaving the Bus-Off state.
0: The Bus-Off state is left on software request, once 128 occurrences of 11
recessive bits have been monitored and the software has first set and cleared the
Bit 6 INRQ bit of the CAN_MCR register.
1: The Bus-Off state is left automatically by hardware once 128 occurrences of 11
recessive bits have been monitored.
For detailed information on the Bus-Off state please refer to Section 14.5.6: Error
management.
AWUM: Automatic Wake-Up Mode
This bit controls the behavior of the CAN hardware on message reception during
SLEEP mode.
0: The SLEEP mode is left on software request by clearing the SLEEP bit of the
Bit 5
CAN_MCR register.
1: The SLEEP mode is left automatically by hardware on CAN message detection.
The SLEEP bit of the CAN_MCR register and the SLAK bit of the CAN_MSR
register are cleared by hardware.
NART: No Automatic Retransmission
0: The CAN hardware will automatically retransmit the message until it has been
Bit 4 successfully transmitted according to the CAN standard.
1: A message will be transmitted only once, independently of the transmission
result (successful, error or arbitration lost).
RFLM: Receive FIFO Locked Mode
0: Receive FIFO not locked on overrun. Once a receive FIFO is full the next
Bit 3 incoming message will overwrite the previous one.
1: Receive FIFO locked against overrun. Once a receive FIFO is full the next
incoming message will be discarded.
TXFP: Transmit FIFO Priority
This bit controls the transmission order when several mailboxes are pending at the
Bit 2 same time.
0: Priority driven by the identifier of the message
1: Priority driven by the request order (chronologically)

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SLEEP: SLEEP Mode Request

This bit is set by software to request the CAN hardware to enter the SLEEP mode.
SLEEP mode will be entered as soon as the current CAN activity (transmission or
reception of a CAN frame) has been completed.
Bit 1
This bit is cleared by software to exit SLEEP mode.
This bit is cleared by hardware when the AWUM bit is set and a SOF bit is
detected on the CAN Rx signal.
This bit is set after reset - CAN starts in SLEEP mode.
INRQ: Initialization Request
The software clears this bit to switch the hardware into normal mode. Once 11
consecutive recessive bits have been monitored on the Rx signal the CAN
hardware is synchronized and ready for transmission and reception. Hardware
Bit 0 signals this event by clearing the INAK bit in the CAN_MSR register.
Software sets this bit to request the CAN hardware to enter initialization mode.
Once software has set the INRQ bit, the CAN hardware waits until the current
CAN activity (transmission or reception) is completed before entering the
initialization mode. Hardware signals this event by setting the INAK bit in the
CAN_MSR register.

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CAN master status register (CAN_MSR)

Address Offset: 04h
Reset value: 00000C02h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RX SAMP RXM TXM Reserved SLAKI WKUI ERRI SLAK INAK

r r r r rc_w1 rc_w1 rc_w1 r r

Bits 31:12 Reserved, forced by hardware to 0.

RX: CAN Rx Signal
Bit 11
Monitors the actual value of the CAN_RX Pin.
SAMP: Last Sample Point
Bit 10
The value of RX on the last sample point (current received bit value).
RXM: Receive Mode
Bit 9
The CAN hardware is currently receiver.
TXM: Transmit Mode
Bit 8
The CAN hardware is currently transmitter.
Bits 7:5 Reserved, forced by hardware to 0.
SLAKI: SLEEP Acknowledge Interrupt
When SLKIE=1, this bit is set by hardware to signal that the bxCAN has entered
SLEEP Mode. When set, this bit generates a status change interrupt if the SLKIE
Bit 4 bit in the CAN_IER register is set.
This bit is cleared by software or by hardware, when SLAK is cleared.
Note: When SLKIE=0, no polling on SLAKI is possible. In this case the SLAK bit can
be polled.
WKUI: Wake-Up Interrupt
This bit is set by hardware to signal that a SOF bit has been detected while the
Bit 3 CAN hardware was in SLEEP mode. Setting this bit generates a status change
interrupt if the WKUIE bit in the CAN_IER register is set.
This bit is cleared by software.
ERRI: Error Interrupt
This bit is set by hardware when a bit of the CAN_ESR has been set on error
detection and the corresponding interrupt in the CAN_IER is enabled. Setting this
Bit 2
bit generates a status change interrupt if the ERRIE bit in the CAN_IER register is
set.
This bit is cleared by software.

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SLAK: SLEEP Acknowledge

This bit is set by hardware and indicates to the software that the CAN hardware is
now in SLEEP mode. This bit acknowledges the SLEEP mode request from the
software (set SLEEP bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left SLEEP mode (to
Bit 1
be synchronized on the CAN bus). To be synchronized the hardware has to
monitor a sequence of 11 consecutive recessive bits on the CAN RX signal.
Note: The process of leaving SLEEP mode is triggered when the SLEEP bit in the
CAN_MCR register is cleared. Please refer to the AWUM bit of the CAN_MCR
register description for detailed information for clearing SLEEP bit
INAK: Initialization Acknowledge
This bit is set by hardware and indicates to the software that the CAN hardware is
now in initialization mode. This bit acknowledges the initialization request from the
Bit 0 software (set INRQ bit in CAN_MCR register).
This bit is cleared by hardware when the CAN hardware has left the initialization
mode (to be synchronized on the CAN bus). To be synchronized the hardware has
to monitor a sequence of 11 consecutive recessive bits on the CAN RX signal.

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CAN transmit status register (CAN_TSR)

Address Offset: 08h
Reset value: 1C000000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ABRQ TERR TXOK RQCP

LOW2 LOW1 LOW0 TME2 TME1 TME0 CODE[1:0] Reserved ALST2
2 2 2 2

r r r r r r r r rs rc_w1 rc_w1 rc_w1 rc_w1

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ABRQ TERR TXOK RQCP ABRQ TERR TXOK RQCP

Reserved ALST1 Reserved ALST0
1 1 1 1 0 0 0 0

rs rc_w1 rc_w1 rc_w1 rc_w1 rs rc_w1 rc_w1 rc_w1 rc_w1

LOW2: Lowest Priority Flag for Mailbox 2

Bit 31 This bit is set by hardware when more than one mailbox are pending for
transmission and mailbox 2 has the lowest priority.
LOW1: Lowest Priority Flag for Mailbox 1
Bit 30 This bit is set by hardware when more than one mailbox are pending for
transmission and mailbox 1 has the lowest priority.
LOW0: Lowest Priority Flag for Mailbox 0
This bit is set by hardware when more than one mailbox are pending for
Bit 29
transmission and mailbox 0 has the lowest priority.
Note: The LOW[2:0] bits are set to zero when only one mailbox is pending.
TME2: Transmit Mailbox 2 Empty
Bit 28
This bit is set by hardware when no transmit request is pending for mailbox 2.
TME1: Transmit Mailbox 1 Empty
Bit 27
This bit is set by hardware when no transmit request is pending for mailbox 1.
TME0: Transmit Mailbox 0 Empty
Bit 26
This bit is set by hardware when no transmit request is pending for mailbox 0.
CODE[1:0]: Mailbox Code
In case at least one transmit mailbox is free, the code value is equal to the number
Bits 25:24 of the next transmit mailbox free.
In case all transmit mailboxes are pending, the code value is equal to the number
of the transmit mailbox with the lowest priority.
ABRQ2: Abort Request for Mailbox 2
Set by software to abort the transmission request for the corresponding mailbox.
Bit 23
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 22:20 Reserved, forced by hardware to 0.
TERR2: Transmission Error of Mailbox 2
Bit 19
This bit is set when the previous TX failed due to an error.
ALST2: Arbitration Lost for Mailbox 2
Bit 18
This bit is set when the previous TX failed due to an arbitration lost.

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TXOK2: Transmission OK of Mailbox 2

The hardware updates this bit after each transmission attempt.
Bit 17 0: The previous transmission failed
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 2 has been
completed successfully. Please refer to Figure 124.
RQCP2: Request Completed Mailbox2
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ2
Bit 16
set in CAN_TMID2R register).
Clearing this bit clears all the status bits (TXOK2, ALST2 and TERR2) for Mailbox
2.
ABRQ1: Abort Request for Mailbox 1
Set by software to abort the transmission request for the corresponding mailbox.
Bit 15
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 14:12 Reserved, forced by hardware to 0.
TERR1: Transmission Error of Mailbox1
Bit 11
This bit is set when the previous TX failed due to an error.
ALST1: Arbitration Lost for Mailbox1
Bit 10
This bit is set when the previous TX failed due to an arbitration lost.
TXOK1: Transmission OK of Mailbox1
The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
Bit 9
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been
completed successfully. Please refer to Figure 124
RQCP1: Request Completed Mailbox1
Set by hardware when the last request (transmit or abort) has been performed.
Bit 8 Cleared by software writing a “1” or by hardware on transmission request (TXRQ1
set in CAN_TI1R register).
Clearing this bit clears all the status bits (TXOK1, ALST1 and TERR1) for Mailbox
1.
ABRQ0: Abort Request for Mailbox0
Set by software to abort the transmission request for the corresponding mailbox.
Bit 7
Cleared by hardware when the mailbox becomes empty.
Setting this bit has no effect when the mailbox is not pending for transmission.
Bits 6:4 Reserved, forced by hardware to 0.
TERR0: Transmission Error of Mailbox0
Bit 3
This bit is set when the previous TX failed due to an error.
ALST0: Arbitration Lost for Mailbox0
Bit 2
This bit is set when the previous TX failed due to an arbitration lost.

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TXOK0: Transmission OK of Mailbox0

The hardware updates this bit after each transmission attempt.
0: The previous transmission failed
Bit 1
1: The previous transmission was successful
This bit is set by hardware when the transmission request on mailbox 1 has been
completed successfully. Please refer to Figure 124
RQCP0: Request Completed Mailbox0
Set by hardware when the last request (transmit or abort) has been performed.
Cleared by software writing a “1” or by hardware on transmission request (TXRQ0
Bit 0
set in CAN_TI0R register).
Clearing this bit clears all the status bits (TXOK0, ALST0 and TERR0) for Mailbox
0.

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Controller area network (bxCAN) UM0306

CAN receive FIFO 0 register (CAN_RF0R)

Address Offset: 0Ch
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RFOM0 FOVR0 FULL0 Res. FMP0[1:0]

rs rc_w1 rc_w1 r r

Bit 31:6 Reserved, forced by hardware to 0.

RFOM0: Release FIFO 0 Output Mailbox
Set by software to release the output mailbox of the FIFO. The output mailbox can
only be released when at least one message is pending in the FIFO. Setting this
Bit 5 bit when the FIFO is empty has no effect. If at least two messages are pending in
the FIFO, the software has to release the output mailbox to access the next
message.
Cleared by hardware when the output mailbox has been released.
FOVR0: FIFO 0 Overrun
This bit is set by hardware when a new message has been received and passed
Bit 4
the filter while the FIFO was full.
This bit is cleared by software.
FULL0: FIFO 0 Full
Bit 3 Set by hardware when three messages are stored in the FIFO.
This bit is cleared by software.
Bit 2 Reserved, forced by hardware to 0.
FMP0[1:0]: FIFO 0 Message Pending
These bits indicate how many messages are pending in the receive FIFO.
Bits 1:0 FMP is increased each time the hardware stores a new message in to the FIFO.
FMP is decreased each time the software releases the output mailbox by setting
the RFOM0 bit.

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CAN receive FIFO 1 register (CAN_RF1R)

Address Offset: 10h
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved RFOM1 FOVR1 FULL1 Res. FMP1[1:0]

rs rc_w1 rc_w1 r r

Bits 31:6 Reserved, forced by hardware to 0.

RFOM1: Release FIFO 1 Output Mailbox
Set by software to release the output mailbox of the FIFO. The output mailbox can
only be released when at least one message is pending in the FIFO. Setting this
Bit 5 bit when the FIFO is empty has no effect. If at least two messages are pending in
the FIFO, the software has to release the output mailbox to access the next
message.
Cleared by hardware when the output mailbox has been released.
FOVR1: FIFO 1 Overrun
This bit is set by hardware when a new message has been received and passed
Bit 4
the filter while the FIFO was full.
This bit is cleared by software.
FULL1: FIFO 1 Full
Bit 3 Set by hardware when three messages are stored in the FIFO.
This bit is cleared by software.
Bit 2 Reserved, forced by hardware to 0.
FMP1[1:0]: FIFO 1 Message Pending
These bits indicate how many messages are pending in the receive FIFO1.
Bits 1:0 FMP1 is increased each time the hardware stores a new message in to the FIFO1.
FMP is decreased each time the software releases the output mailbox by setting
the RFOM1 bit.

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Controller area network (bxCAN) UM0306

CAN interrupt enable register (CAN_IER)

Address Offset: 14h
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SLKIE WKUIE

rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LEC BOF EPV EWG FOV FF FMP FOV FF FMP TME

ERRIE Reserved Res.
IE IE IE IE IE1 IE1 IE1 IE0 IE0 IE0 IE

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:18 Reserved, forced by hardware to 0.

SLKIE: SLEEP Interrupt Enable
Bit 17 0: No interrupt when SLAKI bit is set.
1: Interrupt generated when SLAKI bit is set.
WKUIE: Wake-Up Interrupt Enable
Bit 16 0: No interrupt when WKUI is set.
1: Interrupt generated when WKUI bit is set.
ERRIE: Error Interrupt Enable
0: No interrupt will be generated when an error condition is pending in the
Bit 15 CAN_ESR.
1: An interrupt will be generation when an error condition is pending in the
CAN_ESR.
Bits 14:12 Reserved, forced by hardware to 0.
LECIE: Last Error Code Interrupt Enable
0: ERRI bit will not be set when the error code in LEC[2:0] is set by hardware on
Bit 11 error detection.
1: ERRI bit will be set when the error code in LEC[2:0] is set by hardware on error
detection.
BOFIE: Bus-Off Interrupt Enable
Bit 10 0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
EPVIE: Error Passive Interrupt Enable
Bit 9 0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
EWGIE: Error Warning Interrupt Enable
Bit 8 0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
Bit 7 Reserved, forced by hardware to 0.
FOVIE1: FIFO Overrun Interrupt Enable
Bit 6 0: No interrupt when FOVR is set.
1: Interrupt generation when FOVR is set.

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FFIE1: FIFO Full Interrupt Enable

Bit 5 0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
FMPIE1: FIFO Message Pending Interrupt Enable
Bit 4 0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
FOVIE0: FIFO Overrun Interrupt Enable
Bit 3 0: No interrupt when FOVR bit is set.
1: Interrupt generated when FOVR bit is set.
FFIE0: FIFO Full Interrupt Enable
Bit 2 0: No interrupt when FULL bit is set.
1: Interrupt generated when FULL bit is set.
FMPIE0: FIFO Message Pending Interrupt Enable
Bit 1 0: No interrupt generated when state of FMP[1:0] bits are not 00b.
1: Interrupt generated when state of FMP[1:0] bits are not 00b.
TMEIE: Transmit Mailbox Empty Interrupt Enable
0: No interrupt when RQCPx bit is set.
Bit 0
1: Interrupt generated when RQCPx bit is set.
Note: refer to Section 14.6: Interrupts.

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Controller area network (bxCAN) UM0306

CAN error status register (CAN_ESR)

Address Offset: 18h
Reset value: 00h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

REC[7:0] TEC[7:0]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved LEC[2:0] Res. BOFF EPVF EWGF

rw rw rw r r r

REC[7:0]: Receive Error Counter

The implementing part of the fault confinement mechanism of the CAN protocol. In
case of an error during reception, this counter is incremented by 1 or by 8
Bits 31:24 depending on the error condition as defined by the CAN standard. After every
successful reception the counter is decremented by 1 or reset to 120 if its value
was higher than 128. When the counter value exceeds 127, the CAN controller
enters the error passive state.
TEC[7:0]: least significant byte of the 9-bit Transmit Error Counter
Bits 23:16
The implementing part of the fault confinement mechanism of the CAN protocol.
Bits 15:7 Reserved, forced by hardware to 0.
LEC[2:0]: Last Error Code
This field is set by hardware and holds a code which indicates the error condition
of the last error detected on the CAN bus. If a message has been transferred
(reception or transmission) without error, this field will be cleared to ‘0’.
Code 7 is unused and may be written by the hardware to check for an update
000: No Error
Bits 6:4 001: Stuff Error
010: Form Error
011: Acknowledgment Error
100: Bit recessive Error
101: Bit dominant Error
110: CRC Error
111: Set by software
Bit 3 Reserved, forced by hardware to 0.
BOFF: Bus-Off Flag
Bit 2 This bit is set by hardware when it enters the bus-off state. The bus-off state is
entered on TEC overflow, greater than 255, refer to Section 14.5.6 on page 296.
EPVF: Error Passive Flag
Bit 1 This bit is set by hardware when the Error Passive limit has been reached
(Receive Error Counter or Transmit Error Counter>127).
EWGF: Error Warning Flag
Bit 0 This bit is set by hardware when the warning limit has been reached
(Receive Error Counter or Transmit Error Counter≥96).

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UM0306 Controller area network (bxCAN)

CAN bit timing register (CAN_BTR)

Address Offset: 1Ch
Reset value: 01230000h
Note: This register can only be accessed by the software when the CAN hardware is in
initialization mode.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

SILM LBKM Reserved SJW[1:0] Res. TS2[2:0] TS1[3:0]

rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved Reserved BRP[9:0]

rw rw rw rw rw rw rw rw rw rw rw

SILM: Silent Mode (Debug)

Bit 31 0: Normal operation
1: Silent Mode
LBKM: Loop Back Mode (Debug)
Bit 30 0: Loop Back Mode disabled
1: Loop Back Mode enabled
Bits 29:26 Reserved, forced by hardware to 0.
SJW[1:0]: reSynchronization Jump Width
Bits 25:24 These bits define the maximum number of time quanta the CAN hardware is
allowed to lengthen or shorten a bit to perform the resynchronization.
Bit 23 Reserved, forced by hardware to 0.
TS2[2:0]: Time Segment 2
Bits 22:20 These bits define the number of time quanta in Time Segment 2.
tBS2 = tCAN x (TS2[2:0] + 1)

TS1[3:0]: Time Segment 1

These bits define the number of time quanta in Time Segment 1
Bits 19:16 tBS1 = tCAN x (TS1[3:0] + 1)
For more information on bit timing, please refer to Section 14.5.7: Bit timing on
page 296.
CLK8: CLK8 8MHz Clock Input
Bit 15 0: APB clock selected (fsys = PCLK1)
1: 8MHz XTAL clock selected (fsys = fXTAL)

Bits 14:10 Reserved, forced by hardware to 0.

BRP[9:0]: Baud Rate Prescaler
Bits 9:0 These bits define the length of a time quanta.
tq = (BRP[9:0]+1) x tPCLK

14.8.2 Mailbox registers

This chapter describes the registers of the transmit and receive mailboxes. Refer to
Section 14.5.5: Message storage on page 295 for detailed register mapping.

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Controller area network (bxCAN) UM0306

Transmit and receive mailboxes have the same registers except:

● The FMI field in the CAN_RDTxR register.
● A receive mailbox is always write protected.
● A transmit mailbox is write-enabled only while empty, corresponding TME bit in the
CAN_TSR register set.
There are 3 TX Mailboxes and 2 RX Mailboxes. Each RX Mailbox allows access to a 3 level
depth FIFO, the access being offered only to the oldest received message in the FIFO.
Each mailbox consist of 4 registers.

CAN_RI0R CAN_RI1R CAN_TI0R CAN_TI1R CAN_TI2R

CAN_RDT0R CAN_RDT1R CAN_TDT0R CAN_TDT1R CAN_TDT2R
CAN_RL0R CAN_RL1R CAN_TDL0R CAN_TDL1R CAN_TDL2R
CAN_RH0R CAN_RH1R CAN_TDH0R CAN_TDH1R CAN_TDH2R

FIFO0 FIFO1 Three Tx Mailboxes

TX mailbox identifier register (CAN_TIxR) (x=0..2)

Address Offsets: 180h, 190h, 1A0h
Reset Value: xXh (except bit 0, TXRQ = 0)
Note: 1 All TX registers are write protected when the mailbox is pending transmission (TMEx reset).
2 This register also implements the TX request control (bit 0) - reset value 0.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STID[10:0] EXID[17:13]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXID[12:0] IDE RTR TXRQ

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

STID[10:0]: Standard Identifier

Bits 31:21
The standard part of the identifier.
EXID[17:0:] Extended Identifier
Bit 20:3
The extended part of the identifier.
IDE: Extended Identifier
This bit defines the identifier type of message in the mailbox.
Bit 2
0: Standard identifier.
1: Extended identifier.

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UM0306 Controller area network (bxCAN)

RTR: Remote Transmission Request

Bit 1 0: Data frame
1: Remote frame
TXRQ: Transmit Mailbox Request
Bit 0 Set by software to request the transmission for the corresponding mailbox.
Cleared by hardware when the mailbox becomes empty.

Mailbox data length control and time stamp register (CAN_TDTxR) (x=0..2)
All bits of this register are write protected when the mailbox is not in empty state.
Address Offsets: 184h, 194h, 1A4h
Reset Value: xxh
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TIME[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TGT Reserved DLC[3:0]

rw rw rw rw rw

TIME[15:0]: Message Time Stamp

Bits 31:16
This field contains the 16-bit timer value captured at the SOF transmission.
Bits 15:9 Reserved
TGT: Transmit Global Time
This bit is active only when the hardware is in the Time Trigger Communication
mode, TTCM bit of the CAN_MCR register is set.
0: Time stamp TIME[15:0] is not sent.
Bit 8
1: Time stamp TIME[15:0] value is sent in the last two data bytes of the 8-byte
message: TIME[7:0] in data byte 6 and TIME[15:8] in data byte 7, replacing the
data written in CAN_TDHxR[31:16] register (DATA6[7:0] and DATA7[7:0]). DLC
must be programmed as 8 in order these two bytes to be sent over the CAN bus.
Bits 7:4 Reserved
DLC[3:0]: Data Length Code
This field defines the number of data bytes a data frame contains or a remote
Bits 3:0 frame request.
A message can contain from 0 to 8 data bytes, depending on the value in the DLC
field.

Mailbox data low register (CAN_TDLxR) (x=0..2)

All bits of this register are write protected when the mailbox is not in empty state.

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Controller area network (bxCAN) UM0306

Address Offsets: 188h, 198h, 1A8h

Reset Value: xxh
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA3[7:0] DATA2[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA1[7:0] DATA0[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

DATA3[7:0]: Data Byte 3

Bits 31:24
Data byte 3 of the message.
DATA2[7:0]: Data Byte 2
Bits 23:16
Data byte 2 of the message.
DATA1[7:0]: Data Byte 1
Bits 15:8
Data byte 1 of the message.
DATA0[7:0]: Data Byte 0
Bits 7:0 Data byte 0 of the message.
A message can contain from 0 to 8 data bytes and starts with byte 0.

Mailbox data high register (CAN_TDHxR) (x=0..2)

All bits of this register are write protected when the mailbox is not in empty state.
Address Offsets: 18Ch, 19Ch, 1ACh
Reset Value: xxh

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA7[7:0] DATA6[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA5[7:0] DATA4[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

DATA7[7:0]: Data Byte 7

Data byte 7 of the message.
Bits 31:24
Note: if TGT of this message and TTCM are active, DATA7 and DATA6 will be
replaced by the TIME stamp value.
DATA6[7:0]: Data Byte 6
Bits 23:16
Data byte 6 of the message.

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DATA5[7:0]: Data Byte 5

Bits 15:8
Data byte 5 of the message.
DATA4[7:0]: Data Byte 4
Bits 7:0
Data byte 4 of the message.

Rx FIFO mailbox identifier register (CAN_RIxR) (x=0..1)

Address Offsets: 1B0h, 1C0h
Reset Value: xxh
Note: All RX registers are write protected.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

STID[10:0] EXID[17:13]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXID[12:0] IDE RTR Res.

r r r r r r r r r r r r r r r

STID[10:0]: Standard Identifier

Bits 31:21
The standard part of the identifier.
EXID[17:0]: Extended Identifier
Bits 20:3
The extended part of the identifier.
IDE: Extended Identifier
This bit defines the identifier type of message in the mailbox.
Bit 2
0: Standard identifier.
1: Extended identifier.
RTR: Remote Transmission Request
Bit 1 0: Data frame
1: Remote frame
Bit 0 Reserved

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Receive FIFO mailbox data length control and time stamp register
(CAN_RDTxR) (x=0..1)
Address Offsets: 1B4h, 1C4h
Reset Value: xxh
Note: All RX registers are write protected.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TIME[15:0]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FMI[7:0] Reserved DLC[3:0]

r r r r r r r r r r r r

TIME[15:0]: Message Time Stamp

Bits 31:16
This field contains the 16-bit timer value captured at the SOF detection.
FMI[7:0]: Filter Match Index
This register contains the index of the filter the message stored in the mailbox
Bits 15:8
passed through. For more details on identifier filtering please refer to
Section 14.5.4: Identifier filtering on page 291 - Filter Match Index paragraph.
Bits 7:4 Reserved, forced by hardware to 0.
DLC[3:0]: Data Length Code
Bits 3:0 This field defines the number of data bytes a data frame contains (0 to 8). It is 0 in
the case of a remote frame request.

Receive FIFO mailbox data low register (CAN_RDLxR) (x=0..1)

All bits of this register are write protected when the mailbox is not in empty state.
Address Offsets: 1B8h, 1C8h
Reset Value: xxh
Note: All RX registers are write protected.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA3[7:0] DATA2[7:0]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA1[7:0] DATA0[7:0]

r r r r r r r r r r r r r r r r

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DATA3[7:0]: Data Byte 3

Bits 31:24
Data byte 3 of the message.
DATA2[7:0]: Data Byte 2
Bits 23:16
Data byte 2 of the message.
DATA1[7:0]: Data Byte 1
Bits 15:8
Data byte 1 of the message.
DATA0[7:0]: Data Byte 0
Bits 7:0 Data byte 0 of the message.
A message can contain from 0 to 8 data bytes and starts with byte 0.

Receive FIFO mailbox data high register (CAN_RDHxR) (x=0..1)

Address Offsets: 1BCh, 1CCh
Reset Value: xxh
Note: All RX registers are write protected.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

DATA7[7:0] DATA6[7:0]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA5[7:0] DATA4[7:0]

r r r r r r r r r r r r r r r r

DATA7[7:0]: Data Byte 7

Bits 31:24
Data byte 3 of the message.
DATA6[7:0]: Data Byte 6
Bits 23:16
Data byte 2 of the message.
DATA5[7:0]: Data Byte 5
Bits 15:8
Data byte 1 of the message.
DATA4[7:0]: Data Byte 4
Bits 7:0
Data byte 0 of the message.

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Controller area network (bxCAN) UM0306

14.8.3 CAN filter registers

(these registers are implemented only in the master CAN - CAN0)

CAN filter master register (CAN_FMR)

Address Offset: 200h
Reset Value: 2A1C0E01h
Note: All bits of this register are set and cleared by software.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved FINIT

rw

Bits 31:1 Reserved, forced to reset value

FINIT: Filter Init Mode
Initialization mode for filter banks
Bit 0
0: Active filters mode.
1: Initialization mode for the filters.

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CAN filter mode register (CAN_FM0R)

Address Offset: 204h
Reset Value: 00h
Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the
CAN_FMR register.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved FBM13 FBM12 FBM11 FBM10 FBM9 FBM8 FBM7 FBM6 FBM5 FBM4 FBM3 FBM2 FBM1 FBM0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: Please refer to Figure 126: Filter bank scale configuration - register organization on
page 292

Bits 31:14 Reserved. Forced to 0 by hardware.

FBMx: Filter Mode
Mode of the registers of Filter x.
Bits 13:0
0: Two 32-bit registers of filter bank x are in Identifier Mask mode.
1: Two 32-bit registers of filter bank x are in Identifier List mode.

CAN filter scale register (CAN_FS0R)

Address Offset: 20Ch
Reset Value: 00h
Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the
CAN_FMR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved FSC13 FSC12 FSC11 FSC10 FSC9 FSC8 FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Note: Please refer to Figure 126: Filter bank scale configuration - register organization on
page 292

Bits 31:14 Reserved, forced by hardware to 0.

FSCx: Filter Scale Configuration
These bits define the scale configuration of Filters 13-0.
Bits 13:0
0: Dual 16-bit scale configuration
1: Single 32-bit scale configuration

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CAN filter FIFO assignment register (CAN_FFA0R)

Address Offset: 214h
Reset Value: 00h
Note: This register can be written only when the filter initialization mode is set (FINIT=1) in the
CAN_FMR register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved FFA13 FFA12 FFA11 FFA10 FFA9 FFA8 FFA7 FFA6 FFA5 FFA4 FFA3 FFA2 FFA1 FFA0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, forced by hardware to 0.

FFAx: Filter FIFO Assignment for Filter x
The message passing through this filter will be stored in the specified FIFO.
Bits 13:0
0: Filter assigned to FIFO 0
1: Filter assigned to FIFO 1

CAN filter activation register (CAN_FA0R)

Address Offset: 21Ch
Reset Value: 00h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FACT FACT FACT FACT

Reserved FACT9 FACT8 FACT7 FACT6 FACT5 FACT4 FACT3 FACT2 FACT1 FACT0
13 12 11 10

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, forced by hardware to 0.

FACTx: Filter Active
The software sets this bit to activate Filter x. To modify the Filter x registers
(CAN_FxR[0:7]), the FACTx bit must be cleared or the FINIT bit of the CAN_FMR
Bits 13:0
register must be set.
0: Filter x is not active
1: Filter x is active

Filter bank x registers (CAN_FxR[1:0]) (x=0..13)

Address Offsets: 240h..2ACh
Reset Value: xxh

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Note: There are 14 filter banks, x=0..13. Each filter bank x is composed of two 32-bit registers,
CAN_FxR[1:0].
This register can only be modified when the FACTx bit of the CAN_FAxR register is cleared
or when the FINIT bit of the CAN_FMR register is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

FB31 FB30 FB29 FB28 FB27 FB26 FB25 FB24 FB23 FB22 FB21 FB20 FB19 FB18 FB17 FB16

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FB15 FB14 FB13 FB12 FB11 FB10 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 FB0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

In all configurations:
FB[31:0] Filter Bits
Identifier
Each bit of the register specifies the level of the corresponding bit of the expected
identifier.
0: Dominant bit is expected
1: Recessive bit is expected
Bits 31:0
Mask
Each bit of the register specifies whether the bit of the associated identifier
register must match with the corresponding bit of the expected identifier or not.
0: Don’t care, the bit is not used for the comparison
1: Must match, the bit of the incoming identifier must have the same level has
specified in the corresponding identifier register of the filter.

Note: Depending on the scale and mode configuration of the filter the function of each register can
differ. For the filter mapping, functions description and mask registers association, refer to
Section 14.5.4: Identifier filtering on page 291.
A Mask/Identifier register in mask mode has the same bit mapping as in identifier list
mode.
For the register mapping/addresses of the filter banks please refer to the Table 44 on
page 324.

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Controller area network (bxCAN) UM0306

14.9 bxCAN register map

Refer to Table 1 on page 27 for the register boundary addresses.

Table 44. bxCAN - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
SLEEP
AWUM
ABOM
TTCM

RFLM
NART

TXFP

INRQ
CAN_MCR
000h Reserved

Reset Value 0 0 0 0 0 0 1 0

SLAKI
SAMP

WKUI

SLAK
ERRI

INAK
RXM
TXM
RX
CAN_MSR
004h Reserved Reserved

Reset Value CODE[1:0] 1 1 0 0 0 0 0 1 0

RQCP2

RQCP1

RQCP0
ABRQ2

ABRQ1

ABRQ0
TERR2

TXOK2

TERR1

TXOK1

TERR0

TXOK0
ALST2

ALST1

ALST0
CAN_TSR LOW[2:0] TME[2:0]
008h Reserved Reserved Reserved

Reset Value 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

FMP0[1:0]
RFOM0
FOVR0
FULL0
Reserved
CAN_RF0R
00Ch Reserved

Reset Value 0 0 0 0 0

FMP1[1:0]
RFOM1
FOVR1
FULL1
Reserved
CAN_RF1R
010h Reserved

Reset Value 0 0 0 0 0

FMPIE1

FMPIE0
FOVIE1

FOVIE0
EWGIE
WKUIE
ERRIE

TMEIE
BOFIE

Reserved
EPVIE
LECIE
SLKIE

FFIE1

FFIE0
CAN_IER
014h Reserved Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

LEC[2:0]

EWGF
Reserved
BOFF
EPVF
CAN_ESR REC[7:0] TEC[7:0]
018h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SJW[1:0]

Reserved
LBKM

CLK8
SILM

CAN_BTR TS2[2:0] TS1[3:0] BRP[9:0]

01Ch Reserved Reserved

Reset Value 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

020h-17Fh Reserved

TXRQ
RTR
IDE

CAN_TI0R STID[10:0] EXID[17:0]

180h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0
TGT

CAN_TDT0R TIME[15:0] DLC[3:0]

184h Reserved Reserved

Reset Value x x x x x x x x x x x x x x x x x x x x x

CAN_TDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]

188h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_TDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0]

18Ch

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
TXRQ
RTR
IDE

CAN_TI1R STID[10:0] EXID[17:0]

190h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0

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Table 44. bxCAN - register map and reset values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
TGT
CAN_TDT1R TIME[15:0] DLC[3:0]
194h Reserved Reserved

Reset Value x x x x x x x x x x x x x x x x x x x x x

CAN_TDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]

198h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_TDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0]

19Ch

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

TXRQ
RTR
IDE
CAN_TI2R STID[10:0] EXID[17:0]
1A0h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 0

TGT
CAN_TDT2R TIME[15:0] DLC[3:0]
1A4h Reserved Reserved

Reset Value x x x x x x x x x x x x x x x x x x x x x

CAN_TDL2R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]

1A8h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_TDH2R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0]

1ACh

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

Reserved
RTR
IDE
CAN_RI0R STID[10:0] EXID[17:0]
1B0h
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_RDT0R TIME[15:0] FMI[7:0] DLC[3:0]

1B4h Reserved

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_RDL0R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]

1B8h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_RDH0R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0]

1BCh

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Reserved
RTR
IDE

CAN_RI1R STID[10:0] EXID[17:0]

1C0h
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_RDT1R TIME[15:0] FMI[7:0] DLC[3:0]

1C4h Reserved

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_RDL1R DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0]

1C8h

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_RDH1R DATA7[7:0] DATA6[7:0] DATA5[7:0] DATA4[7:0]

1CCh

Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

1D0h-1FFh Reserved

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Table 44. bxCAN - register map and reset values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0 FINIT
CAN_FMR
200h Reserved
Reset Value 1

CAN_FM0R FBM[13:0]
204h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

208h Reserved

CAN_FS0R FSC[13:0]
20Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

210h Reserved

CAN_FFA0R FFA[13:0]
214h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

218h Reserved

CAN_FA0R FACT[13:0]
21Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

220h Reserved

224-23Fh Reserved

CAN_F0R0 FB[31:0]
240h
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_F0R1 FB[31:0]
244h
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_F1R0 FB[31:0]
248h
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_F1R1 FB[31:0]
24Ch
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
. . .
. . .
. . .
. . .

CAN_F13R0 FB[31:0]
2A8h
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

CAN_F13R1 FB[31:0]
2ACh
Reset Value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x

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UM0306 Inter-integrated circuit (I2C) interface

15 Inter-integrated circuit (I2C) interface

15.1 Introduction
I2C (Inter-Integrated Circuit) Bus Interface serves as an interface between the
microcontroller and the serial I2C bus. It provides multi-master capability, and controls all I2C
bus-specific sequencing, protocol, arbitration and timing. It supports standard and fast
speed modes. It is also SMBus 2.0 compatible.
It may be used for a variety of purposes, including CRC generation and verification, SMBus
(System Management Bus) and PMBus (Power Management Bus).
Depending on specific device implementation DMA capability can be available for reduced
CPU overload.

15.2 Main features

● Parallel-bus/I2C protocol converter
● Multi-master capability: the same interface can act as Master or Slave
● I2C Master features:
– Clock generation
– Start and Stop generation
● I2C Slave features:
– Programmable I2C Address detection
– Dual Addressing Capability to acknowledge 2 slave addresses
– Stop bit detection
● Generation and detection of 7-bit/10-bit addressing and General Call
● Supports different communication speeds:
– Standard Speed (up to 100 kHz),
– Fast Speed (up to 400 kHz)
● Status flags:
– Transmitter/Receiver mode flag
– End-of-Byte transmission flag
– I2C busy flag
● Error flags:
– Arbitration lost condition for master mode
– Acknowledgement failure after address/ data transmission
– Detection of misplaced start or stop condition
– Overrun/Underrun if clock stretching is disabled
● 2 Interrupt vectors:
– 1 Interrupt for successful address/ data communication
– 1 Interrupt for error condition
● Optional Clock Stretching
● 1-byte buffer with DMA capability

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● Configurable PEC (Packet Error Checking) Generation or Verification:

– PEC value can be transmitted as last byte in Tx mode
– PEC error checking for last received byte
● SMBus 2.0 Compatibility:
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low extend time
– Hardware PEC generation/verification with ACK control
– Address Resolution Protocol (ARP) supported
● PMBus Compatibility
Note: Some of the above features may not be available in certain products. The user should refer
to the product data sheet, to identify the specific features supported by the I2C interface
implementation.

15.3 General description

In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa. The interrupts are enabled or disabled by software. The interface is
connected to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected
with a standard (up to 100 kHz) or fast (up to 400 kHz) I2C bus.

Mode selection
The interface can operate in one of the four following modes:
● Slave transmitter
● Slave receiver
● Master transmitter
● Master receiver
By default, it operates in slave mode. The interface automatically switches from slave to
master, after it generates a START condition and from master to slave, if an arbitration loss
or a STOP generation occurs, allowing Multi-Master capability.
Communication flow
In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a start condition and ends with a stop condition. Both
start and stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and
the General Call address. The General Call address detection may be enabled or disabled
by software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to the following figure.

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Figure 133. I2C bus protocol

SDA
MSB ACK

SCL
1 2 8 9

START STOP
CONDITION CONDITION

Acknowledge may be enabled or disabled by software. The I2C interface addresses (dual
addressing 7-bit/ 10-bit and/or general call address) can be selected by software.
The Block Diagram of the I2C interface is shown in Figure 134.

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Figure 134. I2C block diagram

DATA REGISTER

DATA
SDA CONTROL DATA SHIFT REGISTER

COMPARATOR PEC CALCULATION

OWN ADDRESS REGISTER

DUAL ADDRESS REGISTER

CLOCK
SCL CONTROL PEC REGISTER

CLOCK CONTROL
REGISTER (CCR)

CONTROL REGISTERS
(CR1&CR2)
CONTROL
STATUS REGISTERS LOGIC
(SR1&SR2)
SMBALERT

INTERRUPTS DMA REQUESTS & ACK

Note: SMBALERT is an optional signal in SMBus mode. This signal is not applicable if
SMBus is disabled.

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15.4 Functional description

By default the I2C interface operates in Slave mode. To switch from default Slave mode to
Master mode a Start condition generation is needed.

15.4.1 I2C slave mode

The peripheral input clock must be programmed in the I2C_CR2 register in order to
generate correct timings. The peripheral input clock frequency must be at least:
● 2 MHz in Standard mode
● 4 MHz in Fast mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the address of the interface (OAR1) and with
OAR2 (if ENDUAL=1) or the General Call address (if ENGC = 1).
Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0),
where xx denotes the two most significant bits of the address.
Header or address not matched: the interface ignores it and waits for another Start
condition.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set and waits for the 8-bit slave address.
Address matched: the interface generates in sequence:
● An acknowledge pulse if the ACK bit is set
● The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit is
set.
● If ENDUAL=1, the software has to read the DUALF bit to check which slave address
has been acknowledged.
In 10-bit mode, after receiving the address sequence the slave is always in Receiver mode.
It will enter Transmitter mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
The TRA bit indicates whether the slave is in Receiver or Transmitter mode.

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Slave transmitter
Following the address reception and after clearing ADDR, the slave sends bytes from the
DR register to the SDA line via the internal shift register.
The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent
(see Figure 135 Transfer sequencing EV1 EV3).
When the acknowledge pulse is received:
● The TxE bit is set by hardware with an interrupt if the ITEVFEN and the ITBUFEN bits
are set.
If TxE is set and a data was not written in the DR register before the end of the last data
transmission, the BTF bit is set and the interface waits for a write in the DR register,
stretching SCL low.

Figure 135. Transfer sequence diagram for slave transmitter

7-bit slave transmitter:
S Address A Data1 A Data2 A DataN NA P
.....
EV1 EV3-1 EV3 EV3 EV3 EV3-2

10-bit slave transmitter

S Header A Address A
EV1

Sr Header A Data1 A .... DataN NA P

EV1 EV3_1 EV3 EV3 . EV3-2

Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVFEN=1)

EV1: ADDR=1, cleared by reading SR1 followed by reading SR2

EV3-1: TxE=1, shift register empty.
EV3: TxE=1, cleared by writing DR; shift register not empty
EV3-2: AF=1; AF is cleared by writing ‘0’ in AF bit of SR1 register.

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Slave receiver
Following the address reception and after clearing ADDR, the slave receives bytes from the
SDA line into the DR register via the internal shift register. After each byte the interface
generates in sequence:
● An acknowledge pulse if the ACK bit is set
● The RxNE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bit is set.
If RxNE is set and the data in the DR register is not read before the end of the last data
reception, the BTF bit is set and the interface waits for a read to the DR register, stretching
SCL low (see Figure 136 Transfer sequencing).

Figure 136. Transfer sequence diagram for slave receiver

7-bit Slave receiver:
S Address A Data1 A Data2 A DataN A P
.....
EV1 EV2 EV2 EV2 EV4

10-bit Slave receiver:

S Header A Address A Data1 A DataN A P
.....
EV1 EV2 EV2 EV4

Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVFEN=1)

EV1: ADDR=1, cleared by reading SR1 followed by reading SR2

EV2: RxNE=1 cleared by reading DR register.
EV4: STOPF=1, cleared by reading SR1 register followed by writing to the CR1 register

Closing slave communication

After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets,
● The STOPF bit and generates an interrupt if the ITEVFEN bit is set.
Then the interface waits for a read of the SR1 register followed by a write to the CR1 register
(see Figure 136 Transfer sequencing EV4).

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15.4.2 I2C master mode

In Master mode, the I2C interface initiates a data transfer and generates the clock signal. A
serial data transfer always begins with a Start condition and ends with a Stop condition.
Master mode is selected as soon as the Start condition is generated on the bus with a
START bit.
The following is the required sequence in master mode.
● Program the peripheral input clock in I2C_CR2 Register in order to generate correct
timings
● Configure the clock control registers
● Configure the rise time register
● Program the I2C_CR1 register to enable the peripheral
● Set the START bit in the I2C_CR2 register to generate a Start condition
The peripheral input clock frequency must be at least:
● 2 MHz in Standard mode
● 4 MHz in Fast mode

Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to generate a Start
condition and switch to Master mode (M/SL bit set).
Once the Start condition is sent:
● The SB bit is set by hardware and an interrupt is generated if the ITEVFEN bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address (see Figure 137 & Figure 138 Transfer sequencing EV5).

Slave address transmission

Then the slave address is sent to the SDA line via the internal shift register.
● In 10-bit addressing mode, sending the header sequence causes the following event:
– The ADD10 bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Then the master waits for a read of the SR1 register followed by a write in the DR
register with the second address byte (see Figure 137 & Figure 138 Transfer
sequencing).
– The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see Figure 137 & Figure 138 Transfer sequencing).
● In 7-bit addressing mode, one address byte is sent.
As soon as the address byte is sent,
– The ADDR bit is set by hardware and an interrupt is generated if the ITEVFEN bit
is set.
Then the master waits for a read of the SR1 register followed by a read of the SR2
register (see Figure 137 & Figure 138 Transfer sequencing).

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The master can decide to enter Transmitter or Receiver mode depending on the LSB of the
slave address sent.
● In 7-bit addressing mode,
– To enter Transmitter mode, a master sends the slave address with LSB reset.
– To enter Receiver mode, a master sends the slave address with LSB set.
● In 10-bit addressing mode,
– To enter Transmitter mode, a master sends the header (11110xx0) and then the
slave address with LSB reset, (where xx denotes the two most significant bits of
the address).
– To enter Receiver mode, a master sends the header (11110xx0) and then the
slave address with LSB reset. Then it should send a repeated Start condition
followed by the header (11110xx1), (where xx denotes the two most significant bits
of the address).
The TRA bit indicates whether the master is in Receiver or Transmitter mode.

Master transmitter
Following the address transmission and after clearing ADDR, the master sends bytes from
the DR register to the SDA line via the internal shift register.
The master waits until TxE is cleared, (see Figure 137 Transfer sequencing EV8).
When the acknowledge pulse is received:
● The TxE bit is set by hardware and an interrupt is generated if the ITEVFEN and
ITBUFEN bits are set.
If TxE is set and a data byte was not written in the DR register before the end of the last data
transmission, BTF is set and the interface waits until BTF is cleared.

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Closing the communication

After writing the last byte to the DR register, the STOP bit is set by software to generate a
Stop condition (see Figure 137 Transfer sequencing EV8_2). The interface goes
automatically back to slave mode (M/SL bit cleared).
Note: Stop condition should be programmed during EV8_2 event, when either TxE or BTF is set.

Figure 137. Transfer Sequence Diagram for Master Transmitter

7-bit Master Transmitter:
S Address A Data1 A Data2 A DataN A P
.....
EV5 EV6 EV8_1 EV8 EV8 EV8 EV8_2

10-bit Master Transmitter

S Header A Address A Data1 A DataN A P
.....
EV5 EV9 EV6 EV8_1 EV8 EV8 EV8_2

Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVFEN=1)

EV5: SB=1, cleared by reading SR1 register followed by writing DR register with Address.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2.
EV8_1: TxE=1 shift register empty
EV8: TxE=1 cleared by writing DR register.
EV8_2: TxE=1, BTF = 1 cleared by HW by stop condition
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.

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Master receiver
Following the address transmission and after clearing ADDR, the I2C interface enters
Master Receiver mode. In this mode the interface receives bytes from the SDA line into the
DR register via the internal shift register. After each byte the interface generates in
sequence:
● An acknowledge pulse if the ACK bit is set
● The RxNE bit is set and an interrupt is generated if the ITEVFEN and ITBUFEN bits are
set (see Figure 138 Transfer sequencing EV7).
If the RxNE bit is set and the data in the DR register is not read before the end of the last
data reception, the BTF bit is set by hardware and the interface waits for a read in the DR
register.

Closing the communication

The master sends a NACK for the last byte received from the slave. After receiving this
NACK, the slave releases the control of the SCL and SDA lines. Then the master can send
a Stop/Re-Start condition.
● In order to generate the non-acknowledge pulse after the last received data byte, the
ACK bit must be cleared just after reading the second last data byte (after second last
RxNE event).
● In order to generate the Stop/Re-Start condition, software must set the STOP/START
bit just after reading the second last data byte (after the second last RxNE event).
After the Stop condition generation, the interface goes automatically back to slave mode
(M/SL bit cleared).

Figure 138. Transfer sequence diagram for master receiver

7-bit Master Receiver:
S Address A Data1 A Data2 A DataN NA P
.....
EV5 EV6 EV7 EV7 EV7_1 EV7

10-bit Master Receiver

S Header A Address A
EV5 EV9 EV6

Sr Header A Data1 A DataN NA P

.....
EV5 EV6 EV7 EV7_1 EV7

Legend: S= Start, Sr = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge,

EVx= Event (with interrupt if ITEVFEN=1)
EV5: SB=1, cleared by reading SR1 register followed by writing DR register.
EV6: ADDR=1, cleared by reading SR1 register followed by reading SR2. In 10-bit master receiver mode, this se-
quence should be followed by writing CR2 with START = 1.
EV7: RxNE=1 cleared by reading DR register.
EV7_1: RxNE=1 cleared by reading DR register, program ACK=0 and STOP request
EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.

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15.4.3 Error conditions

The following are the error conditions which may cause communication to fail.

Bus error (BERR)

This error occurs when the I2C interface detects a Stop or a Start condition during a byte
transfer. In this case,
● The BERR bit is set and an interrupt is generated if the ITERREN bit is set
● In case of Slave: data is discarded and the lines are released by hardware:
– in case of misplaced start, the slave considers it is a restart and waits for address,
or stop condition.
– in case of misplaced stop, the slave reacts like for a stop condition and the lines
are released by hardware.

Acknowledge failure (AF)

This error occurs when the interface detects a non-acknowledge bit. In this case,
● The AF bit is set and an interrupt is generated if the ITERREN bit is set
● A transmitter which receives a NACK must reset the communication:
– If Slave: lines are released by hardware
– If Master: a Stop condition must be generated by software

Arbitration lost (ARLO)

This error occurs when the I2C interface detects an arbitration lost condition. In this case,
● The ARLO bit is set by hardware (and an interrupt is generated if the ITERREN bit is
set)
● The I2C Interface goes automatically back to slave mode (the M/SL bit is cleared)
● Lines are released by hardware

Overrun/underrun error (OVR)

An Overrun error can occur in slave mode when clock stretching is disabled and the I2C
interface is receiving data. The interface has received a byte (RxNE=1) and the data in DR
has not been read, before the next byte is received by the interface. In this case,
● The last received byte is lost.
● In case of Overrun error, software should clear the RxNE bit and the transmitter should
re-transmit the last received byte.
Underrun error can occur in slave mode when clock stretching is disabled and the I2C
interface is transmitting data. The interface has not updated the DR with the next byte
(TxE=1), before the clock comes for the next byte. In this case,
● The same byte in the DR register will be sent again
● The user should make sure that data received on the receiver side during an underrun
error is discarded and that the next bytes are written within the clock low time specified
in the I2C bus standard.

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15.4.4 SDA/SCL line control

● If clock stretching is enabled:
– Transmitter mode: If TxE=1 and BTF=1: the interface holds the clock line low
before transmission to wait for the microcontroller to read SR1 and then write the
byte in the Data Register (both buffer and shift register are empty).
– Receiver mode: If RxNE=1 and BTF=1: the interface holds the clock line low after
reception to wait for the microcontroller to read SR1 and then read the byte in the
Data Register (both buffer and shift register are full).
● If clock stretching is disabled in Slave mode:
– Overrun Error in case of RxNE=1 and no read of DR has been done before the
next byte is received. The last received byte is lost.
– Underrun Error in case TxE=1 and no write into DR has been done before the next
byte must be transmitted. The same byte will be sent again.
– Write Collision not managed.

15.4.5 SMBus
Introduction
The System Management Bus (SMBus) is a two-wire interface through which various
devices can communicate with each other and with the rest of the system. It is based on I2C
principles of operation. SMBus provides a control bus for system and power management
related tasks. A system may use SMBus to pass messages to and from devices instead of
toggling individual control lines.
The System Management Bus Specification refers to three types of devices. A slave is a
device that is receiving or responding to a command. A master is a device that issues
commands, generates the clocks, and terminates the transfer. A host is a specialized master
that provides the main interface to the system's CPU. A host must be a master-slave and
must support the SMBus host notify protocol. Only one host is allowed in a system.

Similarities between SMBus and I2C

● 2 wire bus protocol (1 Clk, 1 Data) + SMBus Alert line optional
● Master-slave communication, Master provides clock
● Multi master capability
● SMBus data format similar to I2C 7-bit addressing format (Figure 133).

Differences between SMBus and I2C

The following table describes the differences between SMBus and I2C.
Table 45. SMBus vs I2C
SMBus I2C

Max. speed 100 kHz Max. speed 400 kHz

Min. clock speed 10 kHz No minimum clock speed
35 ms clock low time-out No time-out
Logic levels are fixed Logic levels are VDD dependent

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Table 45. SMBus vs I2C

SMBus I2C

7-bit, 10-bit and general call slave address

Different address types (reserved, dynamic etc.)
types
Different bus protocols (quick command, process
No bus protocols
call etc.)

SMBus application usage

With System Management Bus, a device can provide manufacturer information, tell the
system what its model/part number is, save its state for a suspend event, report different
types of errors, accept control parameters, and return its status. SMBus provides a control
bus for system and power management related tasks.

Device identification
Any device that exists on the System Management Bus as a slave has a unique address
called the Slave Address. For the list of reserved slave addresses, refer to the SMBus
specification ver. 2.0 (http://smbus.org/specs/).

Bus protocols
The SMBus specification supports up to 9 bus protocols. For more details of these protocols
and SMBus address types, refer to SMBus specification ver. 2.0 (http://smbus.org/specs/).
These protocols should be implemented by the user software.

Address resolution protocol (ARP)

SMBus slave address conflicts can be resolved by dynamically assigning a new unique
address to each slave device. The Address Resolution Protocol (ARP) has the following
attributes:
● Address assignment uses the standard SMBus physical layer arbitration mechanism
● Assigned addresses remain constant while device power is applied; address retention
through device power loss is also allowed
● No additional SMBus packet overhead is incurred after address assignment. (i.e.
subsequent accesses to assigned slave addresses have the same overhead as
accesses to fixed address devices.)
● Any SMBus master can enumerate the bus

Unique device identifier (UDID)

In order to provide a mechanism to isolate each device for the purpose of address
assignment, each device must implement a unique device identifier (UDID).
For the details on 128 bit UDID and more information on ARP, refer to SMBus specification
ver. 2.0 (http://smbus.org/specs/).

SMBus alert mode

SMBus Alert is an optional signal with an interrupt line for devices that want to trade their
ability to master for a pin. SMBALERT is a wired-AND signal just as the SCL and SDA
signals are. SMBALERT is used in conjunction with the SMBus General Call Address.
Messages invoked with the SMBus are 2 bytes long.

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A slave-only device can signal the host through SMBALERT that it wants to talk by setting
ALERT bit in I2C_CR1 register. The host processes the interrupt and simultaneously
accesses all SMBALERT devices through the Alert Response Address (known as ARA
having a value 0001 100X). Only the device(s) which pulled SMBALERT low will
acknowledge the Alert Response Address. This status is identified using SMBALERT Status
flag in I2C_SR1 register. The host performs a modified Receive Byte operation. The 7 bit
device address provided by the slave transmit device is placed in the 7 most significant bits
of the byte. The eighth bit can be a zero or one.
If more than one device pulls SMBALERT low, the highest priority (lowest address) device
will win communication rights via standard arbitration during the slave address transfer. After
acknowledging the slave address the device must disengage its SMBALERT pull-down. If
the host still sees SMBALERT low when the message transfer is complete, it knows to read
the ARA again.
A host which does not implement the SMBALERT signal may periodically access the ARA.
For more details on SMBus Alert mode, refer to SMBus specification ver. 2.0
(http://smbus.org/specs/).

Time-out error
There are differences in the timing specifications between I2C and SMBus.
SMBus defines a clock low time-out, TIMEOUT of 35 ms. Also SMBus specifies TLOW:
SEXT as the cumulative clock low extend time for a slave device. SMBus specifies TLOW:
MEXT as the cumulative clock low extend time for a master device. For more details on
these time-outs, refer to SMBus specification ver. 2.0 (http://smbus.org/specs/).
The status flag Timeout or Tlow Error in I2C_SR1 shows the status of this feature.

How to use the interface in SMBus mode

To switch from I2C mode to SMBus mode, the following sequence should be performed.
● Set the SMBus bit in the I2C_CR1 register
● Configure the SMBTYPE and ENARP bits in the I2C_CR1 register as required for the
application
If you want to configure the device as a master, follow the Start condition generation
procedure in Section 15.4.2: I2C master mode. Otherwise, follow the sequence in
Section 15.4.1: I2C slave mode.
The application has to control the various SMBus protocols by software.
● SMB Device Default Address acknowledged if ENARP=1 and SMBTYPE=0
● SMB Host Header acknowledged if ENARP=1 and SMBTYPE=1
● SMB Alert Response Address acknowledged if SMBALERT=1

15.4.6 DMA requests

DMA requests (when enabled) are generated only for data transfer. DMA requests are
generated by Data Register becoming empty in transmission and Data Register becoming
full in reception. When the number of data transfers which has been programmed for the

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corresponding DMA channel is reached, the DMA controller sends an End of Transfer EOT
signal to the I2C interface and generates a Transfer Complete interrupt if enabled:
● Master Transmitter: In the interrupt routine after the EOT interrupt, disable DMA
requests then wait for a BTF event before programming the STOP condition.
● Master Receiver: The DMA controller sends a hardware signal EOT_1 corresponding
to the (number of bytes -1). If, in the I2C_CR2 register, the LAST bit is set, I2C
automatically sends a NACK after the next byte following EOT_1. The user can
generate a Stop condition in the DMA Transfer Complete interrupt routine if enabled.
Note: Please refer to the product specs for availability DMA controller. If DMA is not available in
the product, the user should use I2C as explained in section 1.4. In the I2C ISR, the user can
clear TxE/ RxNE flags to achieve continuous communication.

Transmission using DMA

DMA mode can be enabled for transmission by setting the DMAEN bit in the I2C_CR2
register. The DMAEN bit must be set only after receiving the address sequence, when
ADDR is cleared. Data will be loaded from a Memory area configured using the DMA
peripheral (refer to the DMA specification) to the I2C_DR register whenever the TxE bit is
set. To map a DMA channel for I2C transmission, perform the following sequence. Here x is
the channel number.
1. Set the I2C_DR register address in the DMA_CPARx register. The data will
be moved to this address from the memory after each TxE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded into I2C_DR from this memory after each TxE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx
register. After each TxE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx
register
5. Set the DIR bit and, in the DMA_CCRx register, configure interrupts after half
transfer or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I2C interface and the DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITEVTEN bit in the I2C_CR2 register if DMA is used for transmission.

Reception using DMA

DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
The DMAEN bit must be set only after receiving the address sequence, when ADDR is
cleared. Data will be loaded from the I2C_DR register to a Memory area configured using
the DMA peripheral (refer to the DMA specification) whenever a data byte is received. To
map a DMA channel for I2C reception, perform the following sequence. Here x is the
channel number.
1. Set the I2C_DR register address in DMA_CPARx register. The data will be
moved from this address to the memory after each RxNE event.
2. Set the memory address in the DMA_CMARx register. The data will be
loaded from the I2C_DR register to this memory area after each RxNE event.

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3. Configure the total number of bytes to be transferred in the DMA_CNDTRx

register. After each RxNE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx
register
5. Reset the DIR bit and configure interrupts in the DMA_CCRx register after
half transfer or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I2C interface and DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITEVTEN bit in the I2C_CR2 register if DMA is used for reception.

15.4.7 Packet error checking

A PEC calculator has been implemented to improve the reliability of communication. The
PEC is calculated by using a programmable polynomial serially on each bit.
● PEC calculation is enabled by setting the ENPEC bit in the I2C_CR1 register. PEC is a
CRC-8 calculated on all message bytes including addresses and R/W bits.
– In transmission: in the last TxE event: set the PEC transfer bit in the I2C_CR1
register. The PEC will be transferred after the current byte.
– In reception: in the last RxNE event: set the PEC bit in the I2C_CR1 register so
that receiver sends a NACK if the next received byte is not equal to the internally
calculated PEC. In case of Master-Receiver, a NACK must follow the PEC
whatever the check result.
● A PECERR error flag/interrupt is also available in the I2C_SR1 register.
● If DMA and PEC calculation are both enabled:-
– In transmission: when the I2C interface receives an EOT signal from the DMA
controller, it automatically sends a PEC after the last byte.
– In reception: when the I2C interface receives an EOT_1 signal from the DMA
controller, it will automatically consider the next byte as a PEC and will check it. A
DMA request is generated after PEC reception.
● To allow intermediate PEC transfers, a control bit is available in the I2C_CR2 register
(LAST bit) to determine if it is really the last DMA transfer or not. If it is the last DMA
request for a master receiver, a NACK is automatically sent after the last received byte.
● PEC calculation is corrupted by an arbitration loss.

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15.5 Interrupt requests

Table 46. I2C Interrupt requests
Enable
Event
Interrupt Event Control
Flag
Bit

Start bit sent (Master) SB

Address sent (Master) or Address matched (Slave) ADDR
10-bit header sent (Master) ADD10 ITEVFEN
Stop received (Slave) STOPF
Data Byte Transfer Finished BTF
Receive buffer not empty RxNE ITEVFEN and
Transmit buffer empty TxE ITBUFEN

Bus error BERR

Arbitration loss (Master) ARLO
Acknowledge failure AF
Overrun/Underrun OVR ITERREN
PEC error PECERR
Timeout/Tlow error TIMEOUT
SMBus Alert SMBALERT

Note: 1 SB, ADDR, ADD10, STOPF, BTF, RxNE and TxE are logically ORed on the same interrupt
channel.
2 BERR, ARLO, AF, OVR, PECERR, TIMEOUT and SMBALERT are logically ORed on the
same interrupt channel.

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Figure 139. I2C interrupt mapping diagram

ITEVFEN
SB
ADDR
ADD10

STOPF
it_event
BTF

TxE

ITBUFEN

RxNE

ITERREN

BERR
ARLO
it_error
AF
OVR
PECERR
TIMEOUT
SMBAlert

15.6 I2C register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

15.6.1 Control register 1(I2C_CR1)

Address offset: 00h
Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SW NO EN EN SMB SM
Res. ALERT PEC POS ACK STOP START ENGC Res. PE
RST STRETCH PEC ARP TYPE BUS

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

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SWRST: Software Reset

When set, the I2C is under reset state. Before resetting this bit, make sure the
I2C lines are released and the bus is free.
0: I2C Peripheral not under reset
Bit 15
1: I2C Peripheral under reset state
Note:
This bit can be used in case the BUSY bit is set to ‘1’ when no stop condition has
been detected on the bus.
Bit 14 Reserved, forced by hardware to 0.
ALERT: SMBus Alert
This bit is set and cleared by software, and cleared by hardware when PE=0.
Bit 13 0: Releases SMBAlert pin high. Alert Response Address Header followed by
NACK.
1: Drives SMBAlert pin low. Alert Response Address Header followed by ACK.
PEC: Packet Error Checking.
This bit is set and cleared by software, and cleared by hardware when PEC is
transferred or by a START or STOP condition or when PE=0.
Bit 12
0: No PEC transfer
1: PEC transfer (in Tx or Rx mode)
Note: PEC calculation is corrupted by an arbitration loss.
POS: Acknowledge/PEC Position (for data reception).
This bit is set and cleared by software and cleared by hardware when PE=0.
0: ACK bit controls the (N)ACK of the current byte being received in the shift
register. The PEC bit indicates that current byte in shift register is a PEC.
1: ACK bit controls the (N)ACK of the next byte which will be received in the shift
Bit 11
register. The PEC bit indicates that the next byte in the shift register is a PEC
Note:
This bit must be configured before data reception starts.
This configuration must be used only in ADDR stretch event in case there are only
2 data bytes
ACK: Acknowledge Enable
This bit is set and cleared by software and cleared by hardware when PE=0.
Bit 10
0: No acknowledge returned
1: Acknowledge returned after a byte is received (matched address or data)
STOP: Stop Generation
The bit is set and cleared by software, cleared by hardware when a Stop
condition is detected, set by hardware when a timeout error is detected.
In Master Mode:
0: No Stop generation.
1: Stop generation after the current byte transfer or after the current Start
condition is sent.
Bit 9
In Slave mode:
0: No Stop generation.
1: Release the SCL and SDA lines after the current byte transfer.

Note:
In Master mode, the BTF bit of the I2C_SR1 register must be cleared when
STOP is requested.

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START: Start Generation

This bit is set and cleared by software and cleared by hardware when start is
sent or PE=0.
In Master Mode:
Bit 8 0: No Start generation
1: Repeated start generation
In Slave mode:
0: No Start generation
1: Start generation when the bus is free
NOSTRETCH: Clock Stretching Disable (Slave mode)
This bit is used to disable clock stretching in slave mode when ADDR or BTF
Bit 7 flag is set, until it is reset by software.
0: Clock stretching enabled
1: Clock stretching disabled
ENGC: General Call Enable
Bit 6 0: General call disabled. Address 00h is NACKed.
1: General call enabled. Address 00h is ACKed.
ENPEC: PEC Enable
Bit 5 0: PEC calculation disabled
1: PEC calculation enabled
ENARP: ARP Enable
0: ARP disable
Bit 4 1: ARP enable
SMBus Device default address recognized if SMBTYPE=0
SMBus Host address recognized if SMBTYPE=1
SMBTYPE: SMBus Type
Bit 3 0: SMBus Device
1: SMBus Host
Bit 2 Reserved, forced by hardware to 0.
SMBUS: SMBus Mode
Bit 1 0: I2C mode
1: SMBus mode
PE: Peripheral Enable
0: Peripheral disable
1: Peripheral enable: the corresponding I/Os are selected as alternate functions
depending on SMBus bit.
Bit 0 Note:
If this bit is reset while a communication is on going, the peripheral is disabled at
the end of the current communication, when back to IDLE state.
All bit resets due to PE=0 occur at the end of the communication.
In master mode, this bit must not be reset before the end of the communication.

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15.6.2 Control register 2 (I2C_CR2)

Address offset: 04h
Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DMA ITBUF ITEVT ITER

Reserved LAST Reserved FREQ[5:0]
EN EN EN REN

rw rw rw rw rw rw rw rw rw rw rw

Bits 15:13 Reserved, forced by hardware to 0.

LAST: DMA Last Transfer
0: Next DMA EOT is not the last transfer
1: Next DMA EOT is the last transfer
Bit 12
Note:
This bit is used in master receiver mode to permit the generation of a NACK on the
last received data.
DMAEN: DMA Requests Enable
0: DMA requests disabled
Bit 11 1: DMA request enabled when TxE=1 or RxNE =1
Note: The DMAEN bit must be set only after receiving the address sequence,
when ADDR is cleared.
ITBUFEN: Buffer Interrupt Enable

Bit 10 0: TxE = 1 or RxNE = 1 does not generate any interrupt.

1:TxE = 1 or RxNE = 1 generates Event Interrupt (whatever the state of
DMAEN)
ITEVTEN: Event Interrupt Enable
0: Event interrupt disabled
1: Event interrupt enabled
This interrupt is generated when:
– SB = 1 (Master)
Bit 9 – ADDR = 1 (Master/Slave)
– ADD10= 1 (Master)
– STOPF = 1 (Slave)
– BTF = 1 with no TxE or RxNE event
– TxE event to 1 if ITBUFEN = 1
– RxNE event to 1if ITBUFEN = 1
ITERREN: Error Interrupt Enable
0: Error interrupt disabled
1: Error interrupt enabled
This interrupt is generated when:
– BERR = 1
Bit 8 – ARLO = 1
– AF = 1
– OVR = 1
– PECERR = 1
– TIMEOUT = 1
– SMBAlert = 1

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Bits 7:6 Reserved, forced by hardware to 0.

FREQ[5:0]: Peripheral Clock Frequency
Input clock frequency must be programmed to generate correct timings
The allowed range is between 2 MHz and 50 MHz
000000: Not allowed
Bits 5:0 000001: Not allowed
000010: 2 MHz
...
110010: 50 MHz
Higher than 110010: Not allowed

15.6.3 Own address register 1 (I2C_OAR1)

Reset Address offset: 08h
Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADD
Res. Reserved ADD[9:8] ADD[7:1] ADD0
MODE

rw rw rw rw rw rw rw rw rw rw rw rw

ADDMODE Addressing Mode (Slave mode)

Bit 15 0: 7-bit slave address (10-bit address not acknowledged)
1: 10-bit slave address (7-bit address not acknowledged)
Bit 14 Must be configured and kept at 1.
Bits 13:10 Reserved, forced by hardware to 0.
ADD[9:8]: Interface Address
Bits 9:8 7-bit addressing mode: don’t care
10-bit addressing mode: bits9:8 of address
ADD[7:1]: Interface Address
Bits 7:1
bits 7:1 of address
ADD0: Interface Address
Bit 0 7-bit addressing mode: don’t care
10-bit addressing mode: bit 0 of address

15.6.4 Own address register 2 (I2C_OAR2)

Address offset: 0Ch
Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved ADD2[7:1] ENDUAL

rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, forced by hardware to 0.

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ADD2[7:1]: Interface address

Bits 7:1
bits 7:1 of address in dual addressing mode
ENDUAL: Dual addressing mode enable
Bit 0 0: Only OAR1 is recognized in 7-bit addressing mode
1: Both OAR1 and OAR2 are recognized in 7-bit addressing mode

15.6.5 Data register (I2C_DR)

Address offset: 10h
Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved DR[7:0]

rw rw rw rw rw rw rw rw

Bits 15:8 Reserved, forced by hardware to 0.

DR[7:0] 8-bit Data Register (1)(2)(3)

Byte received or to be transmitted to the bus.
– Transmitter mode: Byte transmission starts automatically when a byte is
written in the DR register. A continuous transmit stream can be maintained if
Bits 7:0 the next data to be transmitted is put in DR once the transmission is started
(TxE=1)
– Receiver mode: Received byte is copied into DR (RxNE=1). The received data
in the DR register must be read before the next data reception, otherwise an
overrun occurs and the last byte will be lost.
1. In slave mode, the address is not copied into DR.
2. Write collision is not managed (DR can be written if TxE=0).
3. If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so cannot be read.

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15.6.6 Status register 1 (I2C_SR1)

Address offset: 14h
Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SMB TIME PEC STOP

Res. OVR AF ARLO BERR TxE RxNE Res. ADD10 BTF ADDR SB
ALERT OUT ERR F

rc rc rc rc rc rc rc r r r r r r r

SMBALERT: SMBus Alert

In SMBus host mode:
0: no SMBAlert
1: SMBAlert event occurred on pin
Bit 15
In SMBus slave mode:
0: no SMBAlert response address header
1: SMBAlert response address header to SMBAlert LOW received
– Cleared by software writing 0, or by hardware when PE=0.
TIMEOUT: Timeout or Tlow Error
0: No time-out error
1: SCL remained LOW for 25 ms (Timeout)
or
Master cumulative clock low extend time more than 10 ms (Tlow:mext)
Bit 14 or
Slave cumulative clock low extend time more than 25 ms (Tlow:sext)
– When set in slave mode: slave resets the communication and lines are released
by hardware
– When set in master mode: Stop condition sent by hardware
– Cleared by software writing 0, or by hardware when PE=0.
Bit 13 Reserved, forced by hardware to 0.
PECERR: PEC Error in reception
0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
Bit 12
1: PEC error: receiver returns NACK after PEC reception (whatever ACK)
– Cleared by software writing 0, or by hardware when PE=0.
OVR: Overrun/Underrun
0: No overrun/underrun
1: Overrun or underrun
– Set by hardware in slave mode when NOSTRETCH=1 and:
– In reception when a new byte is received (including ACK pulse) and the DR
register has not been read yet. New received byte is lost.
Bit 11
– In transmission when a new byte should be sent and the DR register has not
been written yet. The same byte is sent twice.
– Cleared by software writing 0, or by hardware when PE=0.
Note:
If the DR write occurs very close to SCL rising edge, the sent data is unspecified
and a hold timing error occurs

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AF: Acknowledge Failure.

0: No acknowledge failure
Bit 10 1: Acknowledge failure
– Set by hardware when no acknowledge is returned.
– Cleared by software writing 0, or by hardware when PE=0.
ARLO: Arbitration Lost (master mode)
0: No Arbitration Lost detected
1: Arbitration Lost detected
Set by hardware when the interface loses the arbitration of the bus to another
master
Bit 9 – Cleared by software writing 0, or by hardware when PE=0.
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
Note:
In SMBUS, the arbitration on the data in slave mode occurs only during the data
phase, or the acknowledge transmission (not on the address acknowledge).
BERR: Bus Error
0: No misplaced Start or Stop condition
Bit 8 1: Misplaced Start or Stop condition
– Set by hardware when the interface detects a misplaced Start or Stop condition
– Cleared by software writing 0, or by hardware when PE=0.
TxE: Data Register Empty (transmitters)
0: Data register not empty
1: Data register empty
Bit 7 – Set when DR is empty in transmission. TxE is not set during address phase.
– Cleared by software writing to the DR register or by hardware after a start or a
stop condition or when PE=0.
TxE is not set if either a NACK is received, or if next byte to be transmitted is PEC (PEC=1)

RxNE: Data Register not Empty (receivers).

0: Data register empty
1: Data register not empty
Bit 6 – Set when data register is not empty in receiver mode. RxNE is not set during
address phase.
– Cleared by software reading or writing the DR register or by hardware when
PE=0.
RxNE is not set in case of ARLO event.

Bit 5 Reserved, forced by hardware to 0.

STOPF: Stop detection (Slave mode)
0: No Stop condition detected
1: Stop condition detected
– Set by hardware when a Stop condition is detected on the bus by the slave
Bit 4 after an acknowledge (if ACK=1).
– Cleared by software reading the SR1 register followed by a write in the CR1
register, or by hardware when PE=0
Note:
The STOPF bit is not set after a NACK reception

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ADD10: 10-bit header sent (Master mode)

0: No ADD10 event occurred.
1: Master has sent first address byte (header).
– Set by hardware when the master has sent the first byte in 10-bit address
Bit 3 mode.
– Cleared by software reading the SR1 register followed by a write in the DR
register of the second address byte, or by hardware when PE=0.
Note:
ADD10 bit is not set after a NACK reception
BTF: Byte Transfer Finished.
0: Data Byte transfer not done
1: Data Byte transfer succeeded
– Set by hardware when NOSTRETCH=0 and:
– In reception when a new byte is received (including ACK pulse) and DR has
not been read yet (RxNE=1).
– In transmission when a new byte should be sent and DR has not been
Bit 2 written yet (TxE=1).
– Cleared by software reading SR1 followed by either a read or write in the DR
register or by hardware after a start or a stop condition in transmission or
when PE=0.
Note:
The BTF bit is not set after a NACK reception
The BTF bit is not set if next byte to be transmitted is the PEC (TRA=1 in I2C_SR2
register and PEC=1 in I2C_CR1 register)
ADDR: Address sent (master mode)/matched (slave mode)
This bit is cleared by software reading SR1 register followed reading SR2, or by
hardware when PE=0.
Address Matched (Slave)
0: Address mismatched or not received.
1: Received address matched.
– Set by hardware as soon as the received slave address matched with the OAR
registers content or a general call or a SMBus Device Default Address or
Bit 1 SMBus Host or SMBus Alert is recognized. (when enabled depending on
configuration).
Address Sent (Master)
0: No end of address transmission
1: End of address transmission
– For 10-bit addressing, the bit is set after the ACK of the 2nd byte.
– For 7-bit addressing, the bit is set after the ACK of the byte.
Note:
ADDR is not set after a NACK reception
SB: Start Bit (Master mode).
0: No Start condition
1: Start condition generated.
Bit 0
– Set when a Start condition generated.
– Cleared by software by reading the SR1 register followed by writing the DR
register, or by hardware when PE=0

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15.6.7 Status register 2 (I2C_SR2)

Address offset: 18h
Reset Value:0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SMB
SMB GEN
PEC[7:0] DUALF DEF Res. TRA BUSY MSL
HOST CALL
AULT

r r r r r r r r r r r r r r r

PEC[7:0] Packet Error Checking Register

Bits 15:8
This register contains the internal PEC when ENPEC=1.
DUALF: Dual Flag (Slave mode)
0: Received address matched with OAR1
Bit 7 1: Received address matched with OAR2
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
SMBHOST: SMBus Host Header (Slave mode)
0: No SMBus Host address
Bit 6 1: SMBus Host address received when SMBTYPE=1 and ENARP=1.
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
SMBDEFAULT: SMBus Device Default Address (Slave mode)
0: No SMBus Device Default address
Bit 5 1: SMBus Device Default address received when ENARP=1
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
GENCALL: General Call Address(Slave mode)
0: No General Call
Bit 4 1: General Call Address received when ENGC=1
– Cleared by hardware after a Stop condition or repeated Start condition, or
when PE=0.
Bit 3 Reserved, forced by hardware to 0.
TRA: Transmitter/Receiver
0: Data bytes received
1: Data bytes transmitted
Bit 2 This bit is set depending on R/W bit of address byte, at the end of total address
phase.
It is also cleared by hardware after detection of Stop condition (STOPF=1),
repeated Start condition, loss of bus arbitration (ARLO=1), or when PE=0.

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BUSY: Bus Busy

0: No communication on the bus
1: Communication ongoing on the bus
Bit 1 – Set by hardware on detection of SDA or SCL low
– cleared by hardware on detection of a Stop condition.
It indicates a communication in progress on the bus. This information is still
updated when the interface is disabled (PE=0).
MSL: Master/Slave
0: Slave Mode
1: Master Mode
Bit 0
– Set by hardware as soon as the interface is in Master mode (SB=1).
– Cleared by hardware after detecting a Stop condition on the bus or a loss of
arbitration (ARLO=1), or by hardware when PE=0.

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15.6.8 Clock control register (I2C_CCR)

Address offset: 1Ch
Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

F/S DUTY Reserved CCR[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

F/S I2C Master Mode Selection

Bit 15 0: Standard Mode I2C
1: Fast Mode I2C
DUTY Fast Mode Duty Cycle
Bit 14 0: Fast Mode tlow/thigh = 2
1: Fast Mode tlow/thigh = 16/9 (see CCR)

Bits 13:12 Reserved, forced by hardware to 0.

CCR[11:0] Clock Control Register in Fast/Standard mode (Master mode)
Controls the SCL clock in master mode.
Standard Mode or SMBus:
Thigh = CCR * TCK
Tow = CCR * TCK
Fast Mode:
If DUTY = 0:
Thigh = CCR * TCK
Tow = 2 * CCR * TCK
If DUTY = 1: (to reach 400 kHz)
Bits 11:0
Thigh = 9 * CCR * TCK
Tow = 16 * CCR * TCK
For instance: in standard mode, to generate a 100kHz SCL frequency:
If FREQR = 08, Tck = 125ns so CCR must be programmed with 28h
(28h <=> 40d x 125ns = 5000 ns.)
Notes:
1. The minimum allowed value is 04h, except in FAST DUTY mode where the
minimum allowed value is 01h
2. thigh includes the SCLH rising edge
3. tlow includes the SCLH falling edge
4. These timings are without filters.

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15.6.9 TRISE Register (I2C_TRISE)

Address offset: 20h
Reset Value: 0002h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved TRISE[5:0]

rw rw rw rw rw rw

Bits 15:6 Reserved, forced by hardware to 0.

TRISE[5:0]: Maximum Rise Time in Fast/Standard mode (Master mode)
These bits must be programmed with the maximum SCL rise time given in the I2C
bus specification, incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If, in the I2C_CR2 register, the value of FREQ[5:0] bits is equal to 08h and tCK =
125 ns therefore the TRISE[5:0] bits must be programmed with 09h.
Bits 5:0
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part,
in order to respect the tHIGH parameter.
Note:
TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).

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15.7 I2C register map

Table 47. I2C register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
NOSTRETCH

SMBTYPE
SWRST

SMBUS
ENARP
ENPEC
ALERT

START
Reserved

Reserved
ENGC
STOP
POS
PEC

ACK

PE
I2C_CR1
00h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ITERREN
ITBUFEN
ITEVTEN
DMAEN

Reserved
LAST
I2C_CR2 FREQ[5:0]
04h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0

ADDMODE
Reserved

ADD0
I2C_OAR1 ADD[9:8] ADD[7:1]
08h Reserved Reserved

Reset Value 0 1 0 0 0 0 0 0 0 0 0 0

ENDUAL
I2C_OAR2 ADD2[7:1]
0Ch Reserved

Reset Value 0 0 0 0 0 0 0 0

I2C_DR DR[7:0]
10h Reserved

Reset Value 0 0 0 0 0 0 0 0
SMBALERT
TIMEOUT

PECERR

STOPF
ADD10
Reserved

Reserved

ADDR
BERR
ARLO

RxNE
OVR

BTF
TxE

SB
AF
I2C_SR1
14h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

SMBDEFAULT
SMBHOST

GENCALL
DUALF

Reserved

BUSY
MSL
TRA
I2C_SR2 PEC[7:0]
18h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved
DUTY
F/S

I2C_CCR CCR[11:0]
1Ch Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

I2C_TRISE TRISE[5:0]
20h Reserved

Reset Value 0 0 0 0 1 0

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 Serial peripheral interface (SPI)

16 Serial peripheral interface (SPI)

16.1 Introduction
The Serial Peripheral Interface (SPI) allows half/ full-duplex, synchronous, serial
communication with external devices. The interface can be configured as the master and in
this case it provides the communication clock (SCK) to the external slave device. The
interface is also capable of operating in multi-master configuration.
It may be used for a variety of purposes, including Simplex synchronous transfers on 2 lines
with a possible bidirectional data line or reliable communication using CRC checking.

16.2 Main features

● Full duplex synchronous transfers on 3 lines
● Simplex synchronous transfers on 2 lines with or without a bidirectional data line
● 8- or 16-bit transfer frame format selection
● Master or slave operation
● Multi-master mode capability
● 8 Master mode baud rate prescalers (fPCLK/2 max.)
● Slave mode frequency (fCPU/2 max.)
● Faster communication for both master and slave: Max. SPI speed up to 18 MHz
● NSS management by hardware or software for both master and slave: dynamic change
of master/slave operations
● Programmable clock polarity and phase
● Programmable data order with MSB-first or LSB-first shifting
● Dedicated transmission and reception flags with interrupt capability
● SPI bus busy status flag
● Hardware CRC feature for reliable communication:
– CRC value can be transmitted as last byte in Tx mode
– Automatic CRC error checking for last received byte in full duplex mode
● Master mode fault, overrun and CRC error flags with interrupt capability
● 1-byte transmission and reception buffer with DMA capability: Tx and Rx requests

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16.3 Functional description

16.3.1 General description

The block diagram of the SPI is shown in Figure 140.

Figure 140. SPI block diagram

ADDRESS AND DATA BUS

READ

RX BUFFER
SPI_CR2
MOSI
TXE RXNE ERR TXDM RXDM
0 0 SSOE AEN AEN
SHIFT REGISTER IE IE IE
MISO
LsbFirst SPI_SR
CRC
BSY OVR MOD ERR 0 0 TXE RXNE
TX BUFFER F

WRITE

0
COMMUNICATION
CONTROL 1
SCK
BR[2:0]
BAUD RATE GENERATOR

LSB SPE BR2 BR1 BR0 MSTRCPOL CPHA

FIRST
SPI_CR1

MASTER CONTROL LOGIC BIDI BIDI CRC CRC RX

MODE OE EN Next DFF ONLY SSM SSI

NSS

Usually, the SPI is connected to external devices through 4 pins:

● MISO: Master In / Slave Out data. This pin can be used to transmit data in slave mode
and receive data in master mode.
● MOSI: Master Out / Slave In data. This pin can be used to transmit data in master
mode and receive data in slave mode.
● SCK: Serial Clock out by SPI masters and input by SPI slaves.
● NSS: Slave select. This is a optional pin to select master/ slave mode. This pin acts as
a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid
contention on the data lines. Slave NSS inputs can be driven by standard I/O ports on
the master Device. The NSS pin may also be used as an output if enabled (SSOE bit)
and driven low if the SPI is in master configuration. In this manner, all NSS pins from
devices connected to the Master NSS pin see a low level become slaves when they are
configured in NSS hardware mode.
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 141.

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Figure 141. Single master/ single slave application

MASTER SLAVE
MSBit LSBit MSBit LSBit
MISO MISO
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI
SCK SCK
CLOCK
GENERATOR
NSS NSS
VDD
Not used if NSS is managed
by software
Note: Here, the NSS pin is configured as input

The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds the MISO pin. This implies
full duplex communication with both data out and data in synchronized with the same clock
signal (which is provided by the master device via the SCK pin).

Slave select (NSS) pin management

The NSS pin can be used for both input (in hardware mode) and output. SS output is
enabled or disabled through the SSOE bit in the SPI_CR2 register. Multi-master
configurations are only possible when SS output is disabled. The NSS pin is driven low
when used as an output (SSOE bit) and the SPI is in master mode configuration. Thus all
NSS pins in SPI devices become slaves when they are configured in NSS mode.
As an alternative to using the NSS pin to control the Slave Select signal (NSS pin), the
application can choose to manage the Slave Select signal by software. This is configured by
the SSM bit in the SPI_CR1 register (see Figure 142). In software management, the
external NSS pin is free for other application uses and the internal NSS signal level is driven
by writing to the SSI bit in the SPI_CR1 register.

Figure 142. Hardware/software slave select management

SSM bit

SSI bit 1
NSS Internal
NSS external pin 0

Clock phase and clock polarity

Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits in the SPI_CR1 register. The CPOL (clock polarity) bit controls the steady state value of
the clock when no data is being transferred. This bit affects both master and slave modes. If
CPOL is reset, SCK pin has a low level idle state. If CPOL is set, SCK pin has a high level
idle state.

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If CPHA (clock phase) bit is set, the second edge on the SCK pin (falling edge if the CPOL
bit is reset, rising edge if the CPOL bit is set) is the MSBit capture strobe. Data is latched on
the occurrence of the first clock transition. If CPHA bit is reset, the first edge on the SCK pin
(falling edge if CPOL bit is set, rising edge if CPOL bit is reset) is the MSBit capture strobe.
Data is latched on the occurrence of the second clock transition.
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 143, shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin, the MOSI pin are directly connected between the master and the slave device.
Note: 1 Prior to changing the CPOL/CPHA bits the SPI must be disabled by resetting the SPE bit.
2 Master and slave must be programmed with the same timing mode.
3 The idle state of SCK must correspond to the polarity selected in the SPI_CR1 register (by
pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0).
4 The Data Frame Format (8- or 16-bit) is selected through the DFF bit in SPI_CR1 register,
and determines the data length during transmission/reception.

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Figure 143. Data clock timing diagram

CPHA =1
CPOL = 1

CPOL = 0

MISO LSBit
MSBit
(from master)
8 or 16 bits depending on Data Frame Format (see SPI_CR1)
MOSI
MSBit LSBit
(from slave)

NSS
(to slave)
CAPTURE STROBE

CPHA =0

CPOL = 1

CPOL = 0

MISO MSBit LSBit

(from master) 8 or 16 bits depending on Data Frame Format (see SPI_CR1)

MOSI MSBit LSBit

(from slave)

NSS
(to slave)
CAPTURE STROBE

Note: These timings are shown with the LSBFIRST bit reset in the SPI_CR1 register.

Data frame format

Data can be shifted out either MSB-first or LSB-first depending on the value of the
LSBFIRST bit in the SPI_CR1 Register.
Each data frame is 8 or 16 bits long depending on the size of the data programmed using
the DFF bit in the SPI_CR1 register. The selected data frame format is applicable for
transmission and/or reception.

16.3.2 SPI slave mode

In slave configuration, the serial clock is received on the SCK pin from the master device.
The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer
rate.

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Procedure
1. Set the DFF bit to define 8- or 16-bit data frame format
2. Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see Figure 143). For correct data transfer, the CPOL
and CPHA bits must be configured the same way in the slave device and the master
device.
3. The frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in
the SPI_CR1 register) must be same as the master device.
4. In Hardware mode (refer to Slave select (NSS) pin management on page 361), the
NSS pin must be connected to a low level signal during the complete byte transmit
sequence. In Software mode, set the SSM bit and clear the SSI bit in the SPI_CR1
register.
5. Clear the MSTR bit and set the SPE bit (both in the SPI_CR1 register) to assign the
pins to alternate functions.
In this configuration the MOSI pin is a data input and the MISO pin is a data output.

Transmit sequence
The data byte is parallel loaded into the Tx buffer during a write cycle.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin. The remaining bits (the 7 bits in 8-bit data frame
format, and the 15 bits in 16-bit data frame format) are loaded into the shift-register. The
TXE flag in the SPI_SR register is set on the transfer of data from the Tx Buffer to the shift
register and an interrupt will be generated if TXEIE bit in the SPI_CR2 register is set.
For the receiver, when data transfer is complete:
● The Data in shift register is transferred to Rx Buffer and the RXNE flag (SPI_SR
register) is set
● An Interrupt is generated if the RXEIE bit is set in the SPI_CR2 register.
After the last sampling clock edge the RXNE bit is set, a copy of the data byte received in
the shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI
peripheral returns this buffered value.
Clearing of the RXNE bit is performed by reading the SPI_DR register.

16.3.3 SPI master mode

In a master configuration, the serial clock is generated on the SCK pin.

Procedure
1. Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).
2. Select the CPOL and CPHA bits to define one of the four relationships between the
data transfer and the serial clock (see Figure 143).
3. Set the DFF bit to define 8- or 16-bit data frame format
4. Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format
5. If the NSS pin is required in input mode, in Hardware mode, connect the NSS pin to a
high level signal during the complete byte transmit sequence. In software mode, set the

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SSM and SSI bits in the SPI_CR1 register.

If the NSS pin is required in output mode, just the SSOE bit should be set.
6. The MSTR and SPE bits must be set (they remain set only if the NSS pin is connected
to a high level signal).
In this configuration the MOSI pin is a data output and to the MISO pin is a data input.

Transmit sequence
The transmit sequence begins when a byte is written in the Tx Buffer.
The data byte is parallel loaded into the shift register (from the internal bus) during first bit
transmission and then shifted out serially to the MOSI pin MSB first or LSB first depending
on the LSBFIRST bit in the SPI_CR1 register. The TXE flag will be set on the transfer of
data from the Tx Buffer to the shift register and an interrupt will be generated if TXEIE bit in
the SPI_CR2 register is set.
For the receiver, when data transfer is complete
● The Data in shift register is transferred to RX Buffer and the RXNE flag is set.
● An Interrupt is generated if the RXEIE bit is set in the SPI_CR2 register
At the last sampling clock edge the RXNE bit is set, a copy of the data byte received in the
shift register is moved to the Rx buffer. When the SPI_DR register is read, the SPI
peripheral returns this buffered value.
Clearing the RXNE bit is performed by reading the SPI_DR register.
A continuous transmit stream can be maintained if the next data to be transmitted is put in
the Tx buffer once the transmission is started. Note that TXE flag should be ‘1’ before an
attempt to write the Tx buffer.

16.3.4 Simplex communication

The SPI is capable of operating in simplex mode in 2 configurations.
● 1 clock and 1 bidirectional data wire
● 1 clock and 1 data wire (Rx-only or full duplex)

1 Clock and 1 bidirectional data wire

This mode is enabled by setting the BIDIMODE bit in the SPI_CR2 register. In this mode
SCK is used for the clock and MOSI in master or MISO in slave mode is used for data
communication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the
SPI_CR2 register. When this bit is 1, the data line is output otherwise it is input.

1 Clock and 1 data wire (Rx-only or full duplex)

In order to free an I/O pin so it can be used for other purposes, it is possible to disable the
SPI output function by setting the RXONLY bit in the SPI_CR1 register. In this case, SPI will
function in Receive-only mode. When the RXONLY bit is reset, the SPI will function in full
duplex mode.

Receive-only mode
To start the communication in receive-only mode, it is necessary to enable the SPI. In the
master mode, the communication starts immediately and will stop when the SPE bit is reset

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and the current reception terminates. In slave mode, the SPI will continue to receive as long
as the NSS is pulled down (or the SSI bit is reset) and the SCK is running.
Note: The SPI can be used in Tx-only mode when the RXONLY bit in the SPI_CR1 register is
reset, the RX pin (MISO in master or MOSI in slave) can be used as GPIO. In this case,
when the data register is read, it does not contain the received value.

16.3.5 Status flags

There are three status flags to allow the application to completely monitor the state of the
SPI bus.

Busy flag
This flag indicates the state of the communication layer of the SPI. When it is set, it indicates
that the SPI is busy communicating and/or there is a valid data byte in the Tx buffer waiting
to be transmitted. The purpose of this flag is to indicate if there is any communication
ongoing on the SPI bus or not. This flag will be set as soon as:
1. Data is written in the SPI_DR register in master mode
2. The SCK clock is present in slave mode
The BUSY flag will reset as soon as a byte is transmitted/ received. This flag is set and reset
by hardware. This flag can be monitored to avoid write collision errors. Writing to this flag
has no effect. This flag has meaning only when the SPE bit is set.

Tx buffer empty flag (TXE)

This flag when set indicates that the Tx buffer is empty and the next data to be transmitted
can be loaded into the buffer. The TXE flag is reset when the Tx buffer already has a data
which is to be transmitted. This flag is reset when the SPI is disabled (SPE bit is reset).

Rx buffer not empty (RXNE)

This flag when set indicates that there is a valid received data in the Rx Buffer. This flag is
reset when SPI Data register is read.

16.3.6 CRC calculation

A CRC calculator has been implemented for communication reliability. Separate CRC
calculators are implemented for transmitted data and received data. The CRC is calculated
using a programmable polynomial serially on each bit. It is calculated on the sampling clock
edge defined by the CPHA and CPOL bits in the SPI_CR1 register.
Note: This SPI offers two kinds of CRC calculation standard which depend directly on the data
frame format selected for the transmission and/or reception: 8-bit data (CR8) and 16-bit data
(CRC16-CCITT).
CRC calculation is enabled by setting the CRCEN bit in the SPI_CR1 register. This action
resets the CRC registers (SPI_RXCRCR and SPI_TXCRCR).
In full-duplex mode, the CRC is automatically verified. However, in simplex mode, CRC
verification is performed through software by the receiver.
Note: Please refer to the product specs for availability of this feature.

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SPI communication using CRC is possible through the following procedure:

● Program the polynomial in the SPI_CRCPOLYR register
● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This
also clears the SPI_RXCRCR and SPI_TXCRCR registers
● Program the CPOL, CPHA, LSBfirst, DFF, BR, SSM, SSI and MSTR values.
● Enable the SPI by setting the SPE bit in SPI_CR1
● Start the communication and sustain the communication until all but one byte or half-
word have been transmitted or received.
● In full-duplex mode:
– On writing the last byte of half-word to the Txbuffer, set the CRCNext bit in the
SPI_CR1 register to indicate that after transmission of the last byte, the CRC
should be transmitted. The CRC calculation will be frozen during the CRC
transmission.
– After transmitting the last byte or half word, the SPI transmits the CRC. CRCNext
bit is reset. The CRC is also received and compared against the SPI_RXCRCR
value. If the value does not match, the CRCERR flag in SPI_SR is set and an
interrupt can be generated when the ERRIE in the SPI_CR2 register is set.
● In simplex mode:
– At the end of the last byte or half word transmission, the transmitter needs to write
the SPI_TXCRC register into the SPI_DR register.
– As soon as the reception buffer of the receiver is loaded with the CRC value sent
by the transmitter, the software has to read the SPI_RXCRC content. If it is equal
to 00 (in 8-bit mode) or 0000 (in 16-bit mode) the transfer is successful. For all
other values, the data transfer has been corrupted.
Note: With high bit rate frequencies, the user must take care when transmitting CRC. As the
number of used CPU cycles has to be as low as possible in the CRC transfer phase, the
calling of software functions in the CRC transmission sequence is forbidden to avoid errors
in the last data and CRC reception. This applies to only full-duplex mode since, in simplex
mode, the transfer of CRC is done by software and not automatically via the CRCNEXT bit.
For high bit rate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.

16.3.7 SPI communication using DMA

To operate at its maximum speed, the SPI needs to be fed with the data for transmission and
the data received on the Rx buffer should be read to avoid overrun. To facilitate the transfers,
SPI is implemented with a DMW facility with a simple request/acknowledge protocol. The
DMA access is requested when the enable bit in the SPI_CR2 register is enabled. There are
separate requests for the Tx buffer and the Rx buffer.
Note: For high bit rate frequencies, the DMA mode is advised to avoid degradation of SPI speed
performance due to CPU accesses impacting the SPI bandwidth.

DMA capability with CRC (full-duplex mode)

When the SPI communication is enabled with the CRC communication along with the DMA
mode, the transmission and reception of the CRC bytes at the end of communication is
done automatically in full-duplex mode.

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At the end of data and CRC transfers, the flag CRCERR of SPI-SR is set if corruption occurs
during the transfer

DMA capability with CRC (simplex mode)

In simplex together with DMA, the CRC is transmitted automatically to the receiver at the
end of the last DMA data transmission.
As soon as the reception buffer of the receiver is loaded with the CRC value sent by the
transmitter, the software has to read the SPI_RXCRC content. If it is equal to 00 (in 8-bit
mode) or 0000 (in 16-bit mode) the transfer is successful. For all other values, the data
transfer has been corrupted.

16.3.8 Error flags

Master mode fault (MODF)
Master mode fault occurs when the master device has its NSS pin pulled low (in hardware
mode) or SSI bit low (in software mode), this automatically sets the MODF bit. Master mode
fault affects the SPI peripheral in the following ways:
● The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.
● The SPE bit is reset. This blocks all output from the device and disables the SPI
interface.
● The MSTR bit is reset, thus forcing the device into slave mode.
Use the following software sequence to clear the MODF bit:
1. Make a read or write access to the SPI_SR register while the MODF bit is set.
2. Then write to the SPI_CR1 register.
To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin
must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can
be restored to their original state during or after this clearing sequence.
As a security, hardware does not allow the setting of the SPE and MSTR bits while the
MODF bit is set.
In a slave device the MODF bit cannot be set. However, in a multi-master configuration, the
device can be in slave mode with this MODF bit set. In this case, the MODF bit indicates that
there might have been a multi-master conflict for system control. An interrupt routine can be
used to recover cleanly from this state by performing a reset or returning to a default state.

Overrun condition
An overrun condition occurs when the master device has sent data bytes and the slave
device has not cleared the RXNE bit resulting from the previous data byte transmitted.
When an overrun condition occurs:
● OVR bit is set and an interrupt is generated if the ERRIE bit is set.
In this case, the receiver buffer contents will not be updated with the newly received data
from the master device. A read to the SPI_DR register returns this byte. All other
subsequently transmitted bytes are lost.
Clearing the OVR bit is done by a read of the SPI_DR register followed by a read access to
the SPI_SR register.

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CRC error
This flag is used to verify the validity of the value received when the CRCEN bit in the
SPI_CR1 register is set. In full-duplex mode, the CRCERR flag in the SPI_SR register is set
if the value received in the shift register (after transmission of the transmitter SPI_TXCRCR
value) does not match the receiver SPI_RXCRCR value.

16.3.9 Interrupts

Table 48. SPI interrupt requests

Enable
Event
Interrupt Event Control
Flag
Bit

Transmit buffer empty Flag TXE TXEIE

Receive buffer Not empty Flag RXNE RXNEIE
Master Mode Fault Event MODF
Overrun Error OVR ERRIE
CRC Error Flag CRCERR

16.4 SPI register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

16.4.1 SPI control register 1 (SPI_CR1)

Address Offset: 00h
Reset Value: 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIDI BIDI CRC CRC RX LSB

DFF SSM SSI SPE BR [2:0] MSTR CPOL CPHA
MODE OE EN NEXT ONLY FIRST

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

BIDIMODE: Bidirectional data mode enable

Bit 15 0: 2-line uni-directional data mode selected
1: 1-line bidirectional data mode selected
BIDIOE: Output enable in bidirectional mode
This bit combined with BIDImode bit selects the direction of transfer in
bidirectional mode
Bit 14
0: Output disabled (receive-only mode)
1: Output enabled (transmit-only mode)
In master mode, the MOSI pin is used and in slave mode, MISO pin is used.
CRCEN: Hardware CRC calculation enable
0: CRC calculation disabled
Bit 13 1: CRC calculation Enabled
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for
correct operation

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CRCNEXT: Transmit CRC next

0: Next transmit value is from Tx buffer
1: Next transmit value is from Tx CRC register
Bit 12 Notes:
This bit has to be written as soon as the last data is written into the SPI_DR
register.
This bit is only used in full-duplex mode.
DFF: Data Frame Format
0: 8-bit data frame format is selected for transmission/reception
Bit 11 1: 16-bit data frame format is selected for transmission/reception
Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for
correct operation
RXONLY: Receive only
This bit combined with BIDImode bit selects the direction of transfer in 2 line
uni-directional mode. This bit is also useful in a multi-slave system in which
Bit 10 this particular slave is not accessed, the output from the accessed slave is
not corrupted.
0: Full duplex (Transmit and receive)
1: Output disabled (Receive only mode)
SSM: Software slave management
When the SSM bit is set, the NSS pin input is replaced with the value from
Bit 9 the SSI bit.
0: Software slave management disabled
1: Software slave management enabled
SSI: Internal slave select
Bit 8 This bit has effect only when SSM bit is set. The value of this bit is forced
onto the NSS pin and the I/O value of the NSS pin is ignored.
LSBFIRST: Frame Format
0: MSB transmitted first
Bit 7
1: LSB transmitted first
Note: This bit should not be changed when the communication is ongoing.
SPE: SPI Enable
Bit 6 0: Peripheral disabled
1: Peripheral enabled
BR[2:0]: Baud Rate Control
000: fCPU/2
001: fCPU/4
010: fCPU/8
011: fCPU/16
Bits 5:3
100: fCPU/32
101: fCPU/64
110: fCPU/128
111: fCPU/256
Note: These bits should not be changed when the communication is ongoing.
MSTR: Master Selection
0: Slave configuration
Bit 2
1: Master configuration
Note: This bit should not be changed when the communication is ongoing.

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CPOL: Clock Polarity

0: SCK to 0 when idle
Bit1
1: SCK to 1 when idle
Note: This bit should not be changed when the communication is ongoing.
CPHA: Clock Phase
0: The first clock transition is the first data capture edge
Bit 0
1: The second clock transition is the first data capture edge
Note: This bit should not be changed when the communication is ongoing.

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16.4.2 SPI control register 2 (SPI_CR2)

Address Offset: 04h
Reset Value: 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXNE TXDMA RXDMA

Reserved TXEIE ERRIE Reserved SSOE
IE EN EN

rw rw rw rw rw rw

Bits 15:8 Reserved. Forced to 0 by hardware.

TXEIE: Tx buffer empty interrupt enable
0: TXE interrupt masked
1: TXE interrupt not masked. This allows a interrupt request to be
Bit 7
generated when the TXE flag is set.
Note: To function correctly, the TXEIE and TXDMAEN bits should not be set
at the same time.
RXNEIE: RX buffer not empty interrupt enable
0: RXNE interrupt masked
1: RXNE interrupt not masked. This allows a interrupt request to be
Bit 6
generated when the RXNE flag is set.
Note: To function correctly, the TXEIE and TXDMAEN bits should not be set
at the same time.
ERRIE: Error interrupt enable
This bit controls the generation of an interrupt when an error condition
Bit 5 occurs (CRCERR, OVR, MODF).
0: Error interrupt is masked
1: Error interrupt is enabled.
Bits 4:3 Reserved. Forced to 0 by hardware.
SSOE: SS Output Enable
0: SS output is disabled in master mode and the cell can work in multi-
Bit 2 master configuration
1: SS output is enabled in master mode and when the cell is enabled. The
cell cannot work in a multi-master environment.
TXDMAEN: Tx Buffer DMA Enable
When this bit is set, the DMA request is made whenever the TXE flag is set.
Bit 1
0: Tx buffer DMA disabled
1: Tx buffer DMA enabled
RXDMAEN: Rx Buffer DMA Enable
When this bit is set, the DMA request is made whenever the RXNE flag is
Bit 0 set.
0: Rx buffer DMA disabled
1: Rx buffer DMA enabled

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16.4.3 SPI status register (SPI_SR)

Address Offset: 08h
Reset Value: 0000 0010 (0002h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRC
Reserved BSY OVR MODF Reserved TXE RXNE
ERR

r rc rc rc r r

Bits 15:8 Reserved. Forced to 0 by hardware.

BSY: Busy flag
0: SPI not busy
Bit 7
1: SPI is busy in communication or Tx buffer is not empty
This flag is set and reset by hardware.
OVR: Overrun flag
0: No Overrun occurred
Bit 6 1: Overrun occurred
This flag is set by hardware and reset by a software sequence. Refer to
Section 16.3.8 on page 368 for software sequence.
MODF: Mode fault
0: No Mode fault occurred
Bit 5 1: Mode fault occurred
This flag is set by hardware and reset by a software sequence. Refer to
Section 16.3.8 on page 368 for software sequence.
CRCERR: CRC error flag
0: CRC value received matches the SPI_RXCRCR value
1: CRC value received does not match the SPI_RXCRCR value
Bit 4
This flag is set by hardware and cleared by software writing 0.
Note:
This bit is only used in full-duplex mode.
Bit 3:2 Reserved. Forced to 0 by hardware.
TXE: Transmit buffer empty
Bit 1 0: Tx buffer not empty
1: Tx buffer empty
RXNE: Receive buffer not empty
Bit 0 0: Rx buffer empty
1: Rx buffer not empty

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16.4.4 SPI data register (SPI_DR)

Address Offset: 0Ch
Reset Value: 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DR[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

DR[15:0]: Data register

Data received or to be transmitted.
The data register is split into 2 buffers - one for writing (Transmit Buffer) and
another one for reading (Receive buffer). A write to the data register will write
into the Tx buffer and a read from the data register will return the value held
in the Rx buffer.
Notes:
Bits 15:0 Depending on the data frame format selection bit (DFF in SPI_CR1 register),
the data sent or received is either 8-bit or 16-bit. This selection has to be made
before enabling SPI to ensure correct operation.
For an 8-bit data frame, the buffers are 8-bit and only the LSB of the register
(SPI_DR[7:0]) is used for transmission/reception. When in reception mode, the
MSB of the register (SPI_DR[15:8]) is forced to 0.
For a 16-bit data frame, the buffers are 16-bit and the entire register,
SPI_DR[15:0] is used for transmission/reception.

16.4.5 SPI CRC polynomial register (SPI_CRCPR)

Address Offset: 10h
Reset Value: 0000 0111 (0007h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CRCPOLY[15:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

CRCPOLY[15:0]: CRC polynomial register

This register contains the polynomial for the CRC calculation.
Bits 15:0
The CRC polynomial (0007h) is the reset value of this register. Another
polynomial can be configured as required.

16.4.6 SPI Rx CRC register (SPI_RXCRCR)

Address Offset: 14h
Reset Value: 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RxCRC[15:0]

r r r r r r r r r r r r r r r r

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RXCRC[15:0]: Rx CRC Register

When CRC calculation is enabled, the RxCRC[15:0] bits contain the
computed CRC value of the subsequently received bytes. This register is
reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is
calculated serially using the polynomial programmed in the SPI_CRCPR
register.
Only the 8 LSB bits are considered when the data frame format is set to be
Bits 15:0
8-bit data (DFF bit of SPI_CR1 is cleared). CRC calculation is done based
on CRC8.
The entire 16-bits of this register are considered when a 16-bit data frame
format is selected (DFF bit of the SPI_CR1 register is set). CRC calculation
is done based on CRC16 - CCITT standard.
Note: A read to this register when the BSY Flag is set could return an incorrect
value.

16.4.7 SPI Tx CRC register (SPI_TXCRCR)

Address Offset: 18h
Reset Value: 0000 0000 (0000h)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

TxCRC[15:0]

r r r r r r r r r r r r r r r r

TxCRC[15:0]: Tx CRC register

When CRC calculation is enabled, the TxCRC[7:0] bits contain the
computed CRC value of the subsequently transmitted bytes. This register
is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is
calculated serially using the polynomial programmed in the SPI_CRCPR
register.
Only the 8 LSB bits are considered when the data frame format is set to be
Bits 15:0
8-bit data (DFF bit of SPI_CR1 is cleared). CRC calculation is done based
on CRC8.
The entire 16-bits of this register are considered when a 16-bit data frame
format is selected (DFF bit of the SPI_CR1 register is set). CRC
calculation is done based on CRC16 - CCITT standard.
Note: A read to this register when the BSY flag is set could return a incorrect
value

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16.5 SPI register map

Table 49. SPI register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
BIDIMODE

CRCNEXT

LSBFIRST
CRCEN

RXOnly
BIDIOE

MSTR

CPHA
CPOL
SSM

SPE
DFF

SSI
SPI_CR1 BR [2:0]
00h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXDMAEN
TXDMAEN
RXNEIE
ERRIE

Reserved
TXEIE

SSOE
SPI_CR2
04h Reserved

Reset Value 0 0 0 0 0 0

CRCERR

Reserved
MODF

RXNE
OVR
BSY

TXE
SPI_SR
08h Reserved

Reset Value 0 0 0 0 1 0
SPI_DR DR[15:0]
0Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPI_CRCPR CRCPOLY[15:0]
10h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
SPI_RXCRCR RxCRC[15:0]
14h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPI_TXCRCR TxCRC[15:0]
18h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 Universal synchronous asynchronous receiver transmitter (USART)

17 Universal synchronous asynchronous receiver

transmitter (USART)

17.1 Introduction
The Universal Synchronous Asynchronous Receiver Transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format. The USART offers a very wide range of baud rates
using a fractional baud rate generator.
It supports synchronous one-way communication and half-duplex single wire
communication. It also supports the LIN (Local Interconnection Network), Smartcard
Protocol and IrDA (Infrared Data Association) SIR ENDEC specifications, and modem
operations (CTS/RTS). It allows multi-processor communication.

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High speed data communication is possible by using the DMA for multi-buffer
configuration.Main features
● Full duplex, asynchronous communications
● NRZ standard format (Mark/Space)
● Fractional baud rate generator systems
– A common programmable transmit and receive baud rates up to 4.5 MBits/s
● Programmable data word length (8 or 9 bits)
● Configurable stop bits - support for 1 or 2 stop bits
● LIN Master Synchronous Break send capability and LIN slave break detection
capability
– 13-bit break generation and 10/11 bit break detection when USART is hardware
configured for LIN
● Transmitter clock output for synchronous transmission
● IrDA SIR Encoder Decoder
– Support for 3/16 bit duration for normal mode
● Smartcard Emulation Capability
– The Smartcard interface supports the asynchronous protocol Smartcards as
defined in ISO 7816-3 standards
– 0.5, 1.5 Stop Bits for Smartcard operation
● Single wire Half Duplex Communication
● Configurable Multi-Buffer communication using DMA (Direct Memory Access)
– Buffering of Received/Transmitted bytes in Reserved SRAM using centralized
DMA
● Separate enable bits for Transmitter and Receiver
● Transfer detection flags:
– Receive buffer full
– Transmit buffer empty
– End of Transmission flags
● Parity control:
– Transmits parity bit
– Checks parity of received data byte
● Four error detection flags:
– Overrun error
– Noise error
– Frame error
– Parity error
● Ten interrupt sources with flags:
– CTS changes
– LIN break detection
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received

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– Overrun error
– Framing error
– Noise error
– Parity error
● Multi-Processor communication - enter into mute mode if address match does not
occur
● Wake up from mute mode (by idle line detection or address mark detection)
● Two receiver wake-up modes:
– Address bit (MSB)
– Idle line

17.2 General description

The interface is externally connected to another device by three pins (see Figure 144). Any
USART bidirectional communication requires a minimum of two pins: Receive Data In (RX)
and Transmit Data Out (TX):
RX: Receive Data Input is the serial data input. Oversampling techniques are used for data
recovery by discriminating between valid incoming data and noise.
TX: Transmit Data Output. When the transmitter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is enabled and nothing is to be transmitted, the TX
pin is at high level. In single-wire and smartcard modes, this I/O is used to transmit and
receive the data (at USART level, data are then received on SW_RX).
Through these pins, serial data is transmitted and received in normal USART mode as
frames comprising:
● An Idle Line prior to transmission or reception
● A start bit
● A data word (8 or 9 bits) least significant bit first
● 0.5,1, 1.5, 2 Stop bits indicating that the frame is complete
● This interface uses a fractional baud rate generator - with a 12-bit mantissa and 4-bit
fraction
● A status register (USART_SR)
● Data Register (USART_DR)
● A baud rate register (USART_BRR) - 12-bit mantissa and 4-bit fraction.
● A Guardtime Register (USART_GTPR) in case of Smartcard mode.
Refer to the register description for the definitions of each bit.
Following pin is required to interface in synchronous mode.
SCLK: Transmitter clock output. This pin outputs the transmitter data clock for synchronous
transmission corresponding to SPI master mode (no clock pulses on start bit and stop bit,
and a software option to send a clock pulse on the last data bit). In parallel data can be
received synchronously on RX. This can be used to control peripherals that have shift
registers (e.g. LCD drivers). The clock phase and polarity are software programmable. In
smartcard mode, SCLK can provide the clock to the smartcard.
Following pins are required to interface in IrDA mode.

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IrDA_RDI: Receive Data Input is the data input in IrDA mode.

IrDA_TDO: Transmit Data Output in IrDA mode.
Following pins are required in modem mode:
nCTS: Clear To Send blocks the data transmission at the end of the current transfer when
high
nRTS: Request to send indicates that the USART is ready to receive a data (when low).

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17.2.1 Block diagram

Figure 144. USART block diagram

PWDATA PRDATA
Write Read (DATA REGISTER) DR

(CPU or DMA) (CPU or DMA)

Transmit Data Register (TDR) Receive Data Register (RDR)

TX

RX IrDA
SIR
SW_RX ENDEC Receive Shift Register
Transmit Shift Register
BLOCK

IRDA_OUT
IRDA_IN GTPR
GT PSC SCLK CONTROL SCLK
CR3 CR2
DMAT DMAR SCEN NACK HD IRLP IREN LINE STOP[1:0] CKEN CPOL CPHA LBCL

CR2 CR1
USART Address UE M WAKE PCE PS PEIE

nRTS Hardware
flow
nCTS controller

WAKE RECEIVER
TRANSMIT UP RECEIVER CLOCK
CONTROL UNIT CONTROL

CR1 SR
TXEIE TCIE RXNE
IE
IDLE TE RE RWU SBK CTS LBD TXE TC RXNE IDLE ORE NE FE PE
IE

USART
INTERRUPT
CONTROL

USART_BRR

TE TRANSMITTER RATE
TRANSMITTER
CONTROL
CLOCK

/16 /DIV
BRR (Mantissa)
15 0
fCPU

RECEIVER RATE
RE CONTROL
CONVENTIONAL BAUD RATE GENERATOR

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17.2.2 USART character description

Word length may be selected as being either 8 or 9 bits by programming the M bit in the
USART_CR1 register (see Figure 145).
The TX pin is in low state during the start bit. It is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data (The number of “1” ‘s will include the number of stop bits).
A Break character is interpreted on receiving “0”s for a frame period. At the end of the
break frame the transmitter inserts either 1 or 2 stop bits (logic “1” bit) to acknowledge the
start bit.
Transmission and reception are driven by a common baud rate generator, the clock for each
is generated when the enable bit is set respectively for the transmitter and receiver.
The details of each block is given below.

Figure 145. Word length programming

9-bit Word length (M bit is set), 1 stop bit
Possible Next Data Frame
Parity
Data Frame Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit
Bit
CLOCK
**

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

** LBCL bit controls last data clock pulse

8-bit Word length (M bit is reset), 1 stop bit
Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit
CLOCK ****
**

Start
Idle Frame Bit

Break Frame Extra Start

’1’ Bit

** LBCL bit controls last data clock pulse

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17.2.3 Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the transmit enable bit (TE) is set, the data in the transmit shift register is output on
the TX pin and the corresponding clock pulses are output on the SCLK pin.

Character transmission
During an USART transmission, data shifts out least significant bit first on the TX pin. In this
mode, the USART_DR register consists of a buffer (TDR) between the internal bus and the
transmit shift register (see Figure 144).
Every character is preceded by a start bit which is a logic level low for one bit period. The
character is terminated by a configurable number of stop bits.
The following stop bits are supported by USART.
Note: 1 The TE bit should not be reset during transmission of data. Resetting the TE bit during the
transmission will corrupt the data on the TX pin as the baud rate counters will get frozen.
The current data being transmitted will be lost.
2 An idle frame will be sent after the TE bit is enabled.

Configurable stop bits

The number of stop bits to be transmitted with every character can be programmed in
Control register 2, bits 13,12.
1. 1 stop bit: This is the default value of number of stop bits.
2. 2 Stop bits: This will be supported by normal USART, single-wire and modem modes.
3. 0.5 stop bit: To be used when receiving data in Smartcard mode.
4. 1.5 stop bits: To be used when transmitting data in Smartcard mode.
An idle frame transmission will include the stop bits.
A break transmission will be 10 low bits followed by the configured number of stop bits
(when m = 0) and 11 low bits followed by the configured number of stop bits (when m = 1). It
is not possible to transmit long breaks (break of length greater than 10/11 low bits).

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Figure 146. Configurable stop bits

8-bit Word length (M bit is reset)
Possible Next Data Frame
Data Frame Parity
Bit Next
Start Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
Bit
CLOCK ****
**
** LBCL bit controls last data clock pulse

a) 1 Stop Bit
Possible Next Data Frame
Parity
Data Frame
Bit Next
Start Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
1 1/2 stop bits
b) 1 1/2 stop Bits
Possible Next Data Frame
Parity
Data Frame
Bit Next
Start 2 Stop Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bits Bit

Possible Next Data Frame

c) 2 Stop Bits Parity
Data Frame
Bit Next
Start Start
Bit Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit
1/2 stop bit
d) 1/2 Stop Bit

Procedure:
1. Enable the USART by writing the UE bit in USART_CR1 register to 1.
2. Program the M bit in USART_CR1 to define the word length.
3. Program the number of stop bits in USART_CR2.
4. Select DMA enable (DMAT) in USART_CR3 if Multi buffer Communication is to take
place. Configure the DMA register as explained in multi-buffer communication.
5. Set the TE bit in USART_CR1 to send an idle frame as first transmission.
6. Select the desired baud rate using the USART_BRR register.
7. Write the data to send in the USART_DR register (this clears the TXE bit). Repeat this
for each data to be transmitted in case of single buffer.

Single byte communication

Clearing the TXE bit is always performed by a write to the data register.
The TXE bit is set by hardware and it indicates:
● The data has been moved from TDR to the shift register and the data transmission has
started.
● The TDR register is empty.
● The next data can be written in the USART_DR register without overwriting the
previous data.
This flag generates an interrupt if the TXEIE bit is set.
When a transmission is taking place, a write instruction to the USART_DR register stores
the data in the TDR register and which is copied in the shift register at the end of the current
transmission.

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When no transmission is taking place, a write instruction to the USART_DR register places
the data directly in the shift register, the data transmission starts, and the TXE bit is
immediately set.
When a frame transmission is complete (after the stop bit) the TC bit is set and an interrupt
is generated if the TCIE is set in the USART_CR1 register.
Clearing the TC bit is performed by the following software sequence:
1. A read to the USART_SR register
2. A write to the USART_DR register
Note: The TC bit can also be cleared by writing a ‘0’ to it. This clearing sequence is recommended
only for Multi-buffer communication.

Break characters
Setting the SBK bit transmits a break character. The break frame length depends on the M
bit (see Figure 145).
If the SBK bit is set to ‘1’ a break character is sent on the TX line after completing the current
character transmission. This bit is reset by hardware when the break character is completed
(during the stop bit of the break character). The USART inserts a logic 1 bit at the end of the
last break frame to guarantee the recognition of the start bit of the next frame.
Note: If the software resets the SBK bit before the commencement of break transmission, the
break character will not be transmitted. For two consecutive breaks, the SBK bit should be
set after the stop bit of the previous break.

Idle characters
Setting the TE bit drives the USART to send an idle frame before the first data frame.

17.2.4 Receiver
The USART can receive data words of either 8 or 9 bits depending on the M bit in the
USART_CR1 register.

Character reception
During an USART reception, data shifts in least significant bit first through the RX pin. In this
mode, the USART_DR register consists of a buffer (RDR) between the internal bus and the
received shift register.
Procedure:
1. Enable the USART by writing the UE bit in USART_CR1 register to 1.
2. Program the M bit in USART_CR1 to define the word length.
3. Program the number of stop bits in USART_CR2.
4. Select DMA enable (DMAT) in USART2_CR3 if Multi-buffer Communication is to take
place. Configure the DMA register as explained in multi-buffer communication. STEP 3
5. Select the desired baud rate using the baud rate register USART_BRR
6. Set the RE bit USART_CR1. This enables the receiver which begins searching for a
start bit.

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When a character is received

● The RXNE bit is set. It indicates that the content of the shift register is transferred to the
RDR. In other words, data has been received and can be read (as well as its
associated error flags).
● An interrupt is generated if the RXNEIE bit is set.
● The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
● In Multi-buffer, RXNE is set after every byte received and is cleared by the DMA read to
the Data Register.
● In single buffer mode, clearing the RXNE bit is performed by a software read to the
USART_DR register. The RXNE flag can also be cleared by writing a zero to it. The
RXNE bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Note: The RE bit should not be reset while receiving data. If the RE bit is disabled during
reception, the reception of the current byte will be aborted.

Break character
When a break character is received, the USART handles it as a framing error.

Idle character
When an idle frame is detected, there is the same procedure as a data received character
plus an interrupt if the IDLEIE bit is set.

Overrun error
An overrun error occurs when a character is received when RXNE has not been reset. Data
can not be transferred from the shift register to the RDR register until the RXNE bit is
cleared.
The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set
when the next data is received or the previous DMA request has not been serviced. When
an overrun error occurs:
● The ORE bit is set.
● The RDR content will not be lost. The previous data is available when a read to
USART_DR is performed.
● The shift register will be overwritten. After that point, any data received during overrun
is lost.
● An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits
are set.
● The ORE bit is reset by a read to the USART_SR register followed by a USART_DR
register read operation.
Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two
possibilities:
- if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,
- if RXNE=0, then it means that the last valid data has already been read and thus there is
nothing to be read in the RDR. This case can occur when the last valid data is read in the
RDR at the same time as the new (and lost) data is received. It may also occur when the

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new data is received during the reading sequence (between the USART_SR register read
access and the USART_DR read access).

Noise error
Over-sampling techniques are used (except in synchronous mode) for data recovery by
discriminating between valid incoming data and noise.

Figure 147. Data sampling for noise detection

RX LINE

sampled values
Sample
clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

6/16

7/16 7/16
One bit time

Table 50. Noise detection from sampled data

Sampled Value NE Status Received bit value Data Validity
000 0 0 Valid
001 1 0 Not Valid
010 1 0 Not Valid
011 1 1 Not Valid
100 1 0 Not Valid
101 1 1 Not Valid
110 1 1 Not Valid
111 0 1 Valid

When noise is detected in a frame:

● The NE is set at the rising edge of the RXNE bit.
● The invalid data is transferred from the Shift register to the USART_DR register.
● No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of multi-
buffer communication an interrupt will be issued if the EIE bit is set in the USART_CR3
register.
The NE bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.

Framing error
A framing error is detected when:
The stop bit is not recognized on reception at the expected time, following either a de-
synchronization or excessive noise.

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When the framing error is detected:

● The FE bit is set by hardware
● The invalid data is transferred from the Shift register to the USART_DR register.
● No interrupt is generated in case of single byte communication. However this bit rises
at the same time as the RXNE bit which itself generates an interrupt. In case of multi-
buffer communication an interrupt will be issued if the EIE bit is set in the USART_CR3
register.
The FE bit is reset by a USART_SR register read operation followed by a USART_DR
register read operation.

Configurable stop bits during reception:

The number of stop bits to be received can be configured through the control bits of Control
Register 2 - it can be either 1 or 2 in normal mode and 0.5 or 1.5 in Smartcard mode.
1. 0.5 stop Bit (reception in Smartcard mode): No sampling is done for 0.5 stop bit. As
a consequence, no framing error and no break frame can be detected when 0.5 stop bit
is selected.
2. 1 stop Bit: Sampling for 1 stop Bit is done on the 8th, 9th and 10th samples.
3. 1.5 stop Bits (transmission in Smartcard mode): When transmitting in smartcard
mode, the device must check that the data is correctly sent. Thus the receiver block
must be enabled (RE =1 in the USART_CR1 register) and the stop bit is checked to test
if the smartcard has detected a parity error. In the event of a parity error, the smartcard
forces the data signal low during the sampling - NACK signal-, which is flagged as a
framing error. Then, the FE flag is set with the RXNE at the end of the 1.5 stop bit.
Sampling for 1.5 stop bits is done on the 16th, 17th and 18th samples (1 baud clock
period after the beginning of the stop bit). The 1.5 stop bit can be decomposed into 2
parts: one 0.5 baud clock period during which nothing happens, followed by 1 normal
stop bit period during which sampling occurs halfway through. Refer to Section 17.2.11:
Smartcard on page 398 for more details.
4. 2 stop Bits: Sampling for 2 stop bits is done on the 8th, 9th and 10th samples of the
first stop bit. If a framing error is detected during the first stop bit the framing error flag
will be set. The second stop bit is not checked for framing error. The RXNE flag will be
set at the end of the first stop bit.

17.2.5 Fractional baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as
programmed in the Mantissa and Fraction Registers of USARTDIV.
fCK
Tx/ Rx baud =
(16*USARTDIV)
legend: fCK -Input clock to the peripheral

USARTDIV is an unsigned fixed point number. The 12-bit mantissa is coded on the
USART_BRR register.

How to derive USARTDIV from BRR register values:

Example 1:
If DIV_Mantissa = 27d and DIV_Fraction= 12d (BRR=1BCh), then

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Mantissa (USARTDIV) = 27d

Fraction (USARTDIV) = 12/16 = 0.75d
Therefore USARTDIV = 27.75d

Example 2:
To program USARTDIV = 25.62d,
This leads to:
DIV_Fraction = 16*0.62d = 9.92d, nearest real number 10d = Ah
DIV_Mantissa = mantissa (25.620d) = 25d = 19h
Then, BRR = 19Ah

Example 3:
To program USARTDIV = 50.99d
This leads to:
DIV_Fraction = 16*0.99d = 15.84d => nearest real number, 16d = 10h
DIV_Mantissa = mantissa (50.990d) = 50d = 32h
Note: The Baud Counters will be updated with the new value of the Baud Registers after a write to
BRR. Hence the Baud Register value should not be changed during a transaction.

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Table 51. Error Calculation for Programmed Baud Rates

Baud Rate fCPU = 10 Mhz fCPU = 40 MHz
Value
% Error Value
programmed
in =(Calculated - programmed in
S.No Actual in the Baud Actual % Error
Kbps Desired)B.Rate the Baud Rate
Rate
/Desired B.Rate Register
Register
1. 2.4 2.399 260.4375 -0.04% 2.3999 1041.6875 0.04%
2. 9.6 9.596 65.125 -0.04% 9.599 260.4375 -0.01%
3. 19.2 19.193 32.5625 -0.03% 19.203 130.1875 -0.02%
4. 57.6 57.471 10.875 -0.22% 57.637 43.375 0.06%
5. 115.2 114.942 5.4375 -0.22% 115.274 21.6875 0.06%
6. 230.4 232.558 2.6875 -0.94% 229.885 10.875 -0.22%
7. 460.8 454.545 1.375 -1.36% 459.77 5.4375 -0.22%
8. 921.6 NA NA NA 930.232 2.6875 0.94%

Note: The lower the CPU clock the lower will be the accuracy for a particular Baud rate. The upper
limit of the achievable baud rate can be fixed with this data.

17.2.6 Multi-processor communication

There is a possibility of performing multi-processor communication with the USART (several
USARTs connected in a network). For instance one of the USARTs can be the master, its
TX output is connected to the RX input of the other USART. The others are slaves, their
respective TX outputs are logically ANDed together and connected to the RX input of the
master.
In multi-processor configurations it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant USART
service overhead for all non addressed receivers.
The non addressed devices may be placed in mute mode by means of the muting function.
In mute mode:
● None of the reception status bits can be set.
● All the receive interrupts are inhibited.
● The RWU bit in USART_CR1 register is set to 1. RWU can be controlled automatically
by hardware or written by the software under certain conditions.
The USART can enter or exit from mute mode using one of two methods, depending on the
WAKE bit in the USART_CR1 register:
● Idle Line detection if the WAKE bit is reset,
● Address Mark detection if the WAKE bit is set.

Idle line detection (WAKE=0)

The USART enters mute mode when the RWU bit is written to 1.
It wakes up when an Idle frame is detected. Then the RWU bit is cleared by hardware but
the IDLE bit is not set in the USART_SR register. RWU can also be written to 0 by software.
An example of mute mode behavior using idle line detection is given in Figure 148.

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Figure 148. Mute mode using Idle line detection

RXNE RXNE

RX Data 1 Data 2 Data 3 Data 4 IDLE Data 5 Data 6

RWU Mute Mode Normal Mode

RWU written to 1 Idle frame detected

Address mark detection (WAKE=1)

In this mode, bytes are recognized as addresses if their MSB is a ‘1’ else they are
considered as data. In an address byte, the address of the targeted receiver is put on the 4
LSB. This 4-bit word is compared by the receiver with its own address which is programmed
in the ADD bits in the USART_CR2 register.
The USART enters mute mode when an address character is received which does not
match its programmed address. The RXNE flag is not set for this address byte and no
interrupt nor DMA request is issued as the USART would have entered mute mode.
It exits from mute mode when an address character is received which matches the
programmed address. Then the RWU bit is cleared and subsequent bytes are received
normally. The RXNE bit is set for the address character since the RWU bit has been cleared.
The RWU bit can be written to as 0 or 1 when the receiver buffer contains no data (RXNE=0
in the USART_SR register). Otherwise the write attempt is ignored.
An example of mute mode behavior using address mark detection is given in Figure 149.

Figure 149. Mute mode using Address mark detection

In this example, the current address of the receiver is 1 RXNE RXNE

(programmed in the USART_CR2 register)

RX IDLE Addr=0 Data 1 Data 2 IDLE Addr=1 Data 3 Data 4 Addr=2 Data 5

RWU Mute Mode Normal Mode Mute Mode

Non-matching address Matching address Non-matching address

RWU written to 1
(RXNE was cleared)

17.2.7 Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame
length defined by the M bit, the possible USART frame formats are as listed in Table 52.

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Table 52. Frame formats

M bit PCE bit USART frame

0 0 | SB | 8 bit data | STB |

0 1 | SB | 7-bit data | PB | STB |
1 0 | SB | 9-bit data | STB |
1 1 | SB | 8-bit data PB | STB |

Legends: SB: Start Bit, STB: Stop Bit, PB: Parity Bit
Note: In case of wake up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Even parity: the parity bit is calculated to obtain an even number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in
USART_CR1 = 0).
Odd parity: the parity bit is calculated to obtain an odd number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in
USART_CR1 = 1).
Transmission mode: If the PCE bit is set in USART_CR1, then the MSB bit of the data
written in the data register is transmitted but is changed by the parity bit (even number of
“1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected
(PS=1)). If the parity check fails, the PE flag is set in the USART_SR register and an
interrupt is generated if PEIE is set in the USART_CR1 register.

17.2.8 LIN (local interconnection network) mode

The LIN mode is selected by setting the LINEN bit in the USART_CR2 register. In LIN mode,
the following bits must be kept cleared:
● CLKEN in the USART_CR2 register,
● STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.

LIN transmission
The same procedure explained in Section 17.2.3 has to be applied for LIN Master
transmission than for normal USART transmission with the following differences:
● Clear the M bit to configure 8-bit word length.
● Set the LINEN bit to enter LIN mode. In this case, setting the SBK bit sends 13 ‘0’ bits
as a break character. Then a bit of value ‘1’ is sent to allow the next start detection.

LIN reception
When the LIN mode is enabled, the break detection circuit is activated. The detection is
totally independent from the normal USART receiver. A break can be detected whenever it
occurs, during idle state or during a frame.
When the receiver is enabled (RE=1 in USART_CR1), the circuit looks at the RX input for a
start signal. The method for detecting start bits is the same when searching break

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characters or data. After a start bit has been detected, the circuit samples the next bits
exactly like for the data (on the 8th, 9th and 10th samples). If 10 (when the LBDL = 0 in
USART_CR2) or 11 (when LBDL=1 in USART_CR2) consecutive bits are detected as ‘0’,
and are followed by a delimiter character, the LBD flag is set in USART_SR. If the LBDIE
bit=1, an interrupt is generated. Before validating the break, the delimiter is checked for as it
signifies that the RX line has returned to a high level.
If a ‘1’ is sampled before the 10 or 11 have occurred, the break detection circuit cancels the
current detection and searches for a start bit again.
If the LIN mode is disabled (LINEN=0), the receiver continues working as normal USART,
without taking into account the break detection.
If the LIN mode is enabled (LINEN=1), as soon as a framing error occurs (i.e. stop bit
detected at ‘0’, which will be the case for any break frame), the receiver stops until the break
detection circuit receives either a ‘1’, if the break word was not complete, or a delimiter
character if a break has been detected.
The behavior of the break detector state machine and the break flag is shown on the
Figure 150: Break detection in LIN mode (11-bit break length - LBDL bit is set) on page 394.
Examples of break frames are given on Figure 151: Break detection in LIN mode vs Framing
error detection on page 395.

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Figure 150. Break detection in LIN mode (11-bit break length - LBDL bit is set)
Case 1: break signal not long enough => break discarded, LBD is not set

RX line “Short” Break Frame

Capture Strobe

Break State machine Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Idle

Read Samples 0 0 0 0 0 0 0 0 0 0 1

Case 2: break signal just long enough => break detected, LBD is set

RX line “Short” Break Frame

Capture Strobe
delimiter is immediate
Break State machine Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 B10 Idle

Read Samples 0 0 0 0 0 0 0 0 0 0 0

LBD

Case 3: break signal long enough => break detected, LBD is set

RX line “Short” Break Frame

Capture Strobe

Break State machine Idle Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 wait delimiter Idle

Read Samples 0 0 0 0 0 0 0 0 0 0 0

LBD

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Figure 151. Break detection in LIN mode vs Framing error detection

In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data)

Case 1: break occurring after an Idle

RX line data 1 IDLE BREAK data2 (0x55) data 3 (header)

1 data time 1 data time

RXNE / FE

LBD

Case 1: break occurring while a data is being received

RX line data 1 data 2 BREAK data2 (0x55) data 3 (header)

1 data time 1 data time

RXNE / FE

LBD

17.2.9 USART synchronous mode

The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to
1. In synchronous mode, the following bits must be kept cleared:
● LINEN bit in the USART_CR2 register,
● SCEN, HDSEL and IREN bits in the USART_CR3 register.
The USART allows the user to control a bidirectional synchronous serial communications in
master mode. The SCLK pin is the output of the USART transmitter clock. No clock pulses
are sent to the SCLK pin during start bit and stop bit. Depending on the state of the LBCL bit
in the USART_CR2 register clock pulses will or will not be generated during the last valid
data bit (address mark). The CPOL bit in the USART_CR2 register allows the user to select
the clock polarity, and the CPHA bit in the USART_CR2 register allows the user to select the
phase of the external clock (see Figure 152, Figure 153 & Figure 154).
During idle, preamble and send break, the external SCLK clock is not activated.
In synchronous mode the USART transmitter works exactly like in asynchronous mode. But
as SCLK is synchronized with TX (according to CPOL and CPHA), the data on TX is
synchronous.
In this mode the USART receiver works in a different manner compared to the
asynchronous mode. If RE=1, the data is sampled on SCLK (rising or falling edge,
depending on CPOL and CPHA), without any oversampling. A setup and a hold time must
be respected (which depends on the baud rate: 1/16 bit time).
Note: 1 The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the
transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR

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has been written). This means that it is not possible to receive a synchronous data without
transmitting data.
2 The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These
bits should not be changed while the transmitter or the receiver is enabled.
3 It is advised that TE and RE are set in the same instruction in order to minimize the setup
and the hold time of the receiver.
4 The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).

Figure 152. USART example of synchronous transmission

RX Data out
TX Data in

USART Synchronous device

(e.g. slave SPI)

SCLK Clock

Figure 153. USART data clock timing diagram (M=0)

Idle or preceding Idle or next

transmission Start M=0 (8 data bits) Stop transmission

Clock (CPOL=0, CPHA=0)

*

Clock (CPOL=0, CPHA=1)

*

Clock (CPOL=1, CPHA=0) *

Clock (CPOL=1, CPHA=1) *

Data on TX 0 1 2 3 4 5 6 7
(from master)
Start LSB MSB Stop

Data on RX 0 1 2 3 4 5 6 7
(from slave)
LSB MSB
*
Capture Strobe

* LBCL bit controls last data clock pulse

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Figure 154. USART data clock timing diagram (M=1)

Idle or preceding
transmission Start M=1 (9 data bits) Idle or next
Stop
transmission
Clock (CPOL=0, CPHA=0)
*

Clock (CPOL=0, CPHA=1)

*

Clock (CPOL=1, CPHA=0) *

Clock (CPOL=1, CPHA=1) *

Data on TX 0 1 2 3 4 5 6 7 8
(from master)
Start LSB MSB Stop

Data on RX 0 1 2 3 4 5 6 7 8
(from slave)
LSB MSB
*
Capture Strobe

* LBCL bit controls last data clock pulse

Figure 155. RX data setup/hold time

SCLK (capture strobe on SCLK

rising edge in this example)
Data on RX valid DATA bit
(from slave)

tSETUP tHOLD

tSETUP = tHOLD 1/16 bit time

Note: The function of SCLK is different in Smartcard mode. Refer to the Smartcard mode chapter
for more details.

17.2.10 Single wire half duplex communication

The single-wire half-duplex mode is selected by setting the HDSEL bit in the USART_CR3
register. In this mode, the following bits must be kept cleared:
● LINEN and CLKEN bits in the USART_CR2 register,
● SCEN and IREN bits in the USART_CR3 register.
The USART can be configured to follow a single wire half duplex protocol. The selection
between half and full duplex communication is done with a control bit ‘HALF DUPLEX SEL’
(HDSEL in USART_CR3).
As soon as HDSEL is written to 1:
● RX is no longer used,
● TX is always released when no data is transmitted. Thus, it acts as a standard I/O in
idle or in reception. It means that the I/O must be configured so that TX is configured as
floating input (or output high open-drain) when not driven by the USART.
Apart from this, the communications are similar to what is done in normal USART mode.
The conflicts on the line must be managed by the software (by the use of a centralized

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arbiter, for instance). In particular, the transmission is never blocked by hardware and
continue to occur as soon as a data is written in the data register while the TE bit is set.

17.2.11 Smartcard
The smartcard mode is selected by setting the SCEN bit in the USART_CR3 register. In
smartcard mode, the following bits must be kept cleared:
● LINEN bit in the USART_CR2 register,
● HDSEL and IREN bits in the USART_CR3 register.
Moreover, the CLKEN bit may be set in order to provide a clock to the smartcard.
The Smartcard interface is designed to support asynchronous protocol Smartcards as
defined in the ISO7816-3 standard. USART should be configured as:
● 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register and either:
– 0.5 stop bits when receiving: where STOP=’01’ in the USART_CR2 register
– 1.5 stop bits when transmitting: where STOP=’11’ in the USART_CR2 register.
Figure 156 shows examples of what can be seen on the data line with and without parity
error.

Figure 156. ISO 7816-3 asynchronous protocol

Without Parity error

Guard time

S 0 1 2 3 4 5 6 7 P

Start
bit

With Parity error Guard time

S 0 1 2 3 4 5 6 7 P

Line pulled low

Start by receiver during stop in
bit case of parity error

When connected to a smartcard, the TX output of the USART drives a bidirectional line that
the smartcard also drives into. To do so, SW_RX must be connected on the same I/O than
TX at product level. The Transmitter output enable TX_EN is asserted during the
transmission of the start bit and the data byte, and is deasserted during the stop bit (weak
pull up), so that the receive can drive the line in case of a parity error. If TX_EN is not used,
TX is driven at high level during the stop bit: Thus the receiver can drive the line as long as
TX is configured in open-drain.
Smartcard is a single wire half duplex communication protocol.
● Transmission of data from the transmit shift register is guaranteed to be delayed by a
minimum of 1/2 baud clock. In normal operation a full transmit shift register will start
shifting on the next baud clock edge. In Smartcard mode this transmission is further
delayed by a guaranteed 1/2 baud clock.
● If a parity error is detected during reception of a frame programmed with a 1/2 stop bit
period, the transmit line is pulled low for a baud clock period after the completion of the
receive frame, i.e. at the end of the 1/2 stop bit period. This is to indicate to the
Smartcard that the data transmitted to USART has not been correctly received. This

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NACK signal (pulling transmit line low for 1 baud clock) will cause a framing error on the
transmitter side (configured with 1.5 stop bits). The application can handle re-sending
of data according to the protocol. A parity error is ‘NACK’ed by the receiver if the NACK
control bit is set, otherwise a NACK is not transmitted.
● The assertion of the TC flag can be delayed by programming the Guard Time register.
In normal operation, TC is asserted when the transmit shift register is empty and no
further transmit requests are outstanding. In Smartcard mode an empty transmit shift
register triggers the guard time counter to count up to the programmed value in the
Guard Time register. TC is forced low during this time. When the guard time counter
reaches the programmed value TC is asserted high.
● The de-assertion of TC flag is unaffected by Smartcard mode.
● If a framing error is detected on the transmitter end (due to a NACK from the receiver),
the NACK will not be detected as a start bit by the receive block of the transmitter.
According to the ISO protocol, the duration of the received NACK can be 1 or 2 baud
clock periods.
● On the receiver side, if a parity error is detected and a NACK is transmitted the receiver
will not detect the NACK as a start bit.
Note: 1 A break character is not significant in Smartcard mode. A 00h data with a framing error will
be treated as data and not as a break.
2 No IDLE frame is transmitted when toggling the TE bit. The IDLE frame (as defined for the
other configurations) is not defined by the ISO protocol.
Figure 157 details how the NACK signal is sampled by the USART. In this example the
USART is transmitting a data and is configured with 1.5 stop bits. The receiver part of the
USART is enabled in order to check the integrity of the data and the NACK signal.

Figure 157. Parity error detection using the 1.5 stop bits

Bit 7 Parity Bit 1.5 Stop Bit

1 bit time 1.5 bit time

sampling at sampling at
8th, 9th, 10th 16th, 17th, 18th

0.5 bit time 1 bit time

sampling at sampling at
8th, 9th, 10th 8th, 9th, 10th

The USART can provide a clock to the smartcard through the SCLK output. In smartcard
mode, SCLK is not associated to the communication but is simply derived from the internal
peripheral input clock through a 5-bit prescaler. The division ratio is configured in the
prescaler register USART_GTPR. SCLK frequency can be programmed from fCK/2 to
fCK/62, where fCK is the peripheral input clock.

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17.2.12 IrDA SIR ENDEC block

The IrDA mode is selected by setting the IREN bit in the USART_CR3 register. In IrDA
mode, the following bits must be kept cleared:
● LINEN, STOP and CLKEN bits in the USART_CR2 register,
● SCEN and HDSEL bits in the USART_CR3 register.
The IrDA SIR physical layer specifies use of a Return to Zero, Inverted (RZI) modulation
scheme that represents logic 0 as an infrared light pulse (see Figure 158).
The SIR Transmit encoder modulates the Non Return to Zero (NRZ) transmit bit stream
output from USART. The output pulse stream is transmitted to an external output driver and
infrared LED. USART supports only bit rates up to 115.2Kbps for the SIR ENDEC. In normal
mode the transmitted pulse width is specified as 3/16 of a bit period.
The SIR receive decoder demodulates the return-to-zero bit stream from the infrared
detector and outputs the received NRZ serial bit stream to USART. The decoder input is
normally HIGH (marking state) in the idle state. The transmit encoder output has the
opposite polarity to the decoder input. A start bit is detected when the decoder input is low.
● IrDA is a half duplex communication protocol. If the Transmitter is busy (i.e. the USART
is sending data to the IrDA encoder), any data on the IrDA receive line will be ignored
by the IrDA decoder and if the Receiver is busy (USART is receiving decoded data from
the USART), data on the TX from the USART to IrDA will not be encoded by IrDA.
While receiving data, transmission should be avoided as the data to be transmitted
could be corrupted.
● A ’0’ is transmitted as a high pulse and a ’1’ is transmitted as a ’0’. The width of the
pulse is specified as 3/16th of the selected bit period in normal mode (see Figure 159).
● The SIR decoder converts the IrDA compliant receive signal into a bit stream for
USART.
● The SIR receive logic interprets a high state as a logic one and low pulses as logic
zeros.
● The transmit encoder output has the opposite polarity to the decoder input. The SIR
output is in low state when idle.
● The IrDA specification requires the acceptance of pulses greater than 1.41 us. The
acceptable pulse width is programmable. Glitch detection logic on the receiver end
filters out pulses of width less than 2 PSC periods (PSC is the prescaler value
programmed in the IrDA low-power Baud Register, USART_GTPR). Pulses of width
less than 1 PSC period are always rejected, but those of width greater than one and
less than two periods may be accepted or rejected, those greater than 2 periods will be
accepted as a pulse. The IrDA encoder/decoder doesn’t work when PSC=0.
● The receiver can communicate with a low-power transmitter.
● In IrDA mode, the STOP bits in the USART_CR2 register must be configured to “1 stop
bit”.

IrDA low-power mode

Transmitter:
In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the
width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz.
Generally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode
programmable divisor divides the system clock to achieve this value.

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Receiver:
Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the
USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if
its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in
USART_GTPR).
Note: 1 A pulse of width less than two and greater than one PSC period(s) may or may not be
rejected.
2 The receiver set up time should be managed by software. The IrDA physical layer
specification specifies a minimum of 10 ms delay between transmission and reception (IrDA
is a half duplex protocol).

Figure 158. IrDA SIR ENDEC- block diagram

TX
OR USART_TX

SIR
Transmit IrDA_OUT
SIREN Encoder
USART

SIR
RX Receive IrDA_IN
Decoder

USART_RX

Figure 159. IrDA data modulation (3/16) -Normal Mode

Start stop bit

TX bit
0 1 0 0 1 1 0 1
0 1
bit period

IrDA_OUT
3/16

IrDA_IN

RX 0 1
0 1 0 0 0 1 1
1

17.2.13 Continuous communication using DMA

The USART is capable to continue communication using the DMA. The DMA requests for
Rx buffer and Tx buffer are generated independently.
Note: You should refer to product specs for availability of the DMA controller. If DMA is not
available in the product, you should use the USART as explained in Section 17.2.3 or

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17.2.4. In the USART2_SR register, you can clear the TXE/ RXNE flags to achieve
continuous communication.

Transmission using DMA

DMA mode can be enabled for transmission by setting DMAT bit in the USART_CR3
register. Data is loaded from a SRAM area configured using the DMA peripheral (refer to the
DMA specification) to the USART_DR register whenever the TXE bit is set. To map a DMA
channel for USART transmission, use the following procedure (x denotes the channel
number):
1. Write the USART_DR register address in the DMA control register to configure it as the
destination of the transfer. The data will be moved to this address from memory after
each TXE event.
2. Write the memory address in the DMA control register to configure it as the source of
the transfer. The data will be loaded into the USART_DR register from this memory
area after each TXE event.
3. Configure the total number of bytes to be transferred to the DMA control register.
4. Configure the channel priority in the DMA register
5. Configure DMA interrupt generation after half/ full transfer as required by the
application.
6. Activate the channel in the DMA register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector. The DMAT bit should
be cleared by software in the USART_CR3 register during the interrupt subroutine.
Note: If DMA is used for transmission, do not enable the TXEIE bit.

Reception using DMA

DMA mode can be enabled for reception by setting the DMAR bit in USART_CR3 register.
Data is loaded from the USART_DR register to a SRAM area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
channel for USART reception, use the following procedure (x denotes the channel number):
1. Write the USART_DR register address in the DMA control register to configure it as the
source of the transfer. The data will be moved from this address to the memory after
each RXNE event.
2. Write the memory address in the DMA control register to configure it as the destination
of the transfer. The data will be loaded from USART_DR to this memory area after each
RXNE event.
3. Configure the total number of bytes to be transferred in the DMA control register.
4. Configure the channel priority in the DMA control register
5. Configure interrupt generation after half/ full transfer as required by the application.
6. Activate the channel in the DMA control register.
When the number of data transfers programmed in the DMA Controller is reached, the DMA
controller generates an interrupt on the DMA channel interrupt vector. The DMAR bit should
be cleared by software in the USART_CR3 register during the interrupt subroutine.
Note: If DMA is used for reception, do not enable the RXNEIE bit.

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Error flagging and interrupt generation in multi-buffer communication

In case of multi-buffer communication if any error occurs during the transaction the error flag
will be asserted after the current byte. An interrupt will be generated if the interrupt enable
flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in
case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in
the USART_CR3 register), which if set will issue an interrupt after the current byte with
either of these errors.

17.2.14 Hardware flow control

It is possible to control the serial data flow between 2 devices by using the nCTS input and
the nRTS output. The Figure 160 shows how to connect 2 devices in this mode:

Figure 160. Hardware flow control between 2 USART

USART 1 USART 2
TX RX

TX circuit nCTS nRTS RX circuit

RX TX

RX circuit nCTS TX circuit

nRTS

RTS and CTS flow control can be enabled independently by writing respectively RTSE and
CTSE bits to 1 (in the USART_CR3 register).

RTS flow control

If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the
USART receiver is ready to receive a new data. When the receive register becomes empty,
nRTS is deasserted, indicating that the transmission is expected to stop at the end of the
current frame. Figure 161 shows an example of communication with RTS flow control
enabled.

Figure 161. RTS flow control

Start StopIdle Start Stop

RX Bit Data 1 Data 2
Bit Bit Bit

nRTS

RXNE Data 1 read RXNE

Data 2 can now be transmitted

CTS flow control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input
before transmitting the next frame. If nCTS is asserted (tied low), then the next data is

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transmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the
transmission does not occur. When nCTS is deasserted during a transmission, the current
transmission is completed before the transmitter stops.
When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS
input toggles. It indicates when the receiver becomes ready or not ready for communication.
An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure
below shows an example of communication with CTS flow control enabled.

Figure 162. CTS flow control

CTS CTS

nCTS

Transmit data register

TDR Data 2 empty Data 3 empty

Data 1 StopStart Data 2 Stop Idle Start

TX Bit Bit Bit Bit Data 3

Writing data 3 in TDR

Transmission of Data 3
is delayed until nCTS = 0

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17.3 Interrupt requests

Table 53. USART interrupt requests
Event Enable
Interrupt Event
Flag Control Bit

Transmit Data Register Empty TXE TXEIE

CTS flag CTS CTSIE
Transmission Complete TC TCIE
Received Data Ready to be Read RXNE
RXNEIE
Overrun Error Detected ORE
Idle Line Detected IDLE IDLEIE
Parity Error PE PEIE
Break Flag LBD LBDIE
Noise Flag, Overrun error and Framing Error in multi-buffer
NE or ORE or FE EIE
communication

The USART interrupt events are connected to the same interrupt vector (see Figure 163).
● During transmission: Transmission Complete, Clear to Send or Transmit Data Register
empty interrupt.
● While receiving: Idle Line detection, Overrun error, Receive Data register not empty,
Parity error, LIN break detection, Noise Flag (only in multi buffer communication) and
Framing Error (only in multi buffer communication).
These events generate an interrupt if the corresponding Enable Control Bit is set.

Figure 163. USART interrupt mapping diagram

TC
TCIE
TXE
TXEIE

CTS
CTSIE

USART
IDLE
IDLEIE interrupt
RXNEIE
ORE
RXNEIE
RXNE
PE
PEIE

LBD
LBDIE

FE
NE
OVR EIE
DMAR

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17.4 USART register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

17.4.1 Status register (USART_SR)

Address Offset: 00h
Reset Value: 00C0h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved CTS LBD TXE TC RXNE IDLE ORE NE FE PE

rc rc r rc r r r r r r

Bits 31:10 Reserved, forced by hardware to 0.

CTS: CTS Flag
This bit is set by hardware when the nCTS input toggles, if the CTSE bit is set. It
is cleared by software (by writing it to 0). An interrupt is generated if CTSIE=1 in
Bit 9
the USART_CR3 register.
0: No change occurred on the nCTS status line
1: A change occurred on the nCTS status line
LBD: LIN Break Detection Flag
LIN Break Detection Flag (Status flag)
0: LIN Break not detected
Bit 8
1: LIN break detected
Note:
An interrupt is generated when LBD=1 if LBDIE=1
TXE: Transmit Data Register Empty
This bit is set by hardware when the content of the TDR register has been
transferred into the shift register. An interrupt is generated if the TXEIE bit =1 in
the USART_CR1 register. It is cleared by a write to the USART_DR register.
Bit 7 0: Data is not transferred to the shift register
1: Data is transferred to the shift register)
Note:
This bit is used during single buffer transmission.
TC: Transmission Complete.
This bit is set by hardware when transmission of a frame containing Data is
complete. An interrupt is generated if TCIE=1 in the USART_CR1 register. It is
Bit 6 cleared by a software sequence (an read to the USART_SR register followed by
a write to the USART_DR register).
0: Transmission is not complete
1: Transmission is complete

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RXNE: Read Data Register Not Empty.

This bit is set by hardware when the content of the RDR shift register has been
transferred to the USART_DR register. An interrupt is generated if RXNEIE=1 in
Bit 5
the USART_CR1 register. It is cleared by a read to the USART_DR register.
0: Data is not received
1: Received data is ready to be read.
IDLE: IDLE line detected.
This bit is set by hardware when an Idle Line is detected. An interrupt is
generated if the IDLEIE=1 in the USART_CR1 register. It is cleared by a software
sequence (an read to the USART_SR register followed by a read to the
USART_DR register).
Bit 4 0: No Idle Line is detected
1: Idle Line is detected
Note:
The IDLE bit will not be set again until the RXNE bit has been set itself (i.e. a new
idle line occurs)
ORE: OverRun Error.
This bit is set by hardware when the word currently being received in the shift
register is ready to be transferred into the RDR register while RXNE=1. An
interrupt is generated if RXNEIE=1 in the USART_CR1 register. It is cleared by a
software sequence (an read to the USART_SR register followed by a read to the
USART_DR register).
Bit 3
0: No Overrun error
1: Overrun error is detected
Note:
When this bit is set, the RDR register content will not be lost but the shift register
will be overwritten. An interrupt is generated on ORE flag in case of Multi Buffer
communication if the EIE bit is set.
NE: Noise Error Flag.
This bit is set by hardware when noise is detected on a received frame. It is
cleared by a software sequence (an read to the USART_SR register followed by
a read to the USART_DR register).
0: No noise is detected
Bit 2
1: Noise is detected
Note:
This bit does not generate interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupting interrupt is generated on NE flag in case of
Multi Buffer communication if the EIE bit is set.

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FE: Framing Error.

This bit is set by hardware when a de-synchronization, excessive noise or a
break character is detected. It is cleared by a software sequence (an read to the
USART_SR register followed by a read to the USART_DR register).
0: No Framing error is detected
1: Framing error or break character is detected
Bit 1 Note:
This bit does not generate interrupt as it appears at the same time as the RXNE bit
which itself generates an interrupt. If the word currently being transferred causes
both frame error and overrun error, it will be transferred and only the ORE bit will be
set.
An interrupt is generated on FE flag in case of Multi Buffer communication if the EIE
bit is set.
PE: Parity Error.
This bit is set by hardware when a parity error occurs in receiver mode. It is
cleared by a software sequence (a read to the status register followed by a read
Bit 0 to the USART_DR data register). An interrupt is generated if PEIE=1 in the
USART_CR1 register.
0: No parity error
1: Parity error

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17.4.2 Data register (USART_DR)

Address Offset: 04h
Reset Value: Undefined
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved DR[8:0]

rw rw rw rw rw rw rw rw rw

Bits 31:9 Reserved, forced by hardware to 0.

DR[8:0]: Data value.
Contains the Received or Transmitted data character, depending on whether it is
read from or written to.
The Data register performs a double function (read and write) since it is
composed of two registers, one for transmission (TDR) and one for reception
(RDR)
The TDR register provides the parallel interface between the internal bus and the
Bits 8:0 output shift register (see Figure 1).
The RDR register provides the parallel interface between the input shift register
and the internal bus.
When transmitting with the parity enabled (PCE bit set to 1 in the USART_CR1
register), the value written in the MSB (bit 7 or bit 8 depending on the data length)
has no effect because it is replaced by the parity.
When receiving with the parity enabled, the value read in the MSB bit is the
received parity bit.

17.4.3 Baud rate register (USART_BRR)

Note: The baud counters stop counting if the TE or RE bits are disabled respectively.
Address Offset: 08h
Reset Value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DIV_Mantissa[11:0] DIV_Fraction[3:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, forced by hardware to 0.

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DIV_Mantissa[11:0]: mantissa of DIV.

Bits 15:4
These 12 bits define the mantissa of the USART Divider (DIV)
DIV_Fraction[3:0]: fraction of DIV.
Bits 3:0
These 4 bits define the fraction of the USART Divider (DIV)

17.4.4 Control register 1 (USART_CR1)

Address Offset: 0Ch
Reset Value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXNE
Reserved UE M WAKE PCE PS PEIE TXEIE TCIE IDLEIE TE RE RWU SBK
IE

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:14 Reserved, forced by hardware to 0.

UE: USART Enable.
When this bit is cleared the USART prescalers and outputs are stopped and the
end of the current
Bit 13 byte transfer in order to reduce power consumption. This bit is set and cleared by
software.
0: USART prescaler and outputs disabled
1: USART enabled
M: word length.
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, n Stop bit
Bit 12 1: 1 Start bit, 9 Data bits, 1 Stop bit
Note:
The M bit must not be modified during a data transfer (both transmission and
reception)
WAKE: Wake-up method.
This bit determines the USART Wake-Up method, it is set or cleared by software.
Bit 11
0: Idle Line
1: Address Mark
PCE: Parity Control Enable.
This bit selects the hardware parity control (generation and detection). When the
parity control is enabled, the computed parity is inserted at the MSB position (9th
bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set
Bit 10
and cleared by software. Once it is set, PCE is active after the current byte (in
reception and in transmission).
0: Parity control disabled
1: Parity control enabled

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PS: Parity Selection.

This bit selects the odd or even parity when the parity generation/detection is
enabled (PCE bit set). It is set and cleared by software. The parity will be
Bit 9
selected after the current byte.
0: Even parity
1: Odd parity
PEIE: PE Interrupt Enable.
This bit is set and cleared by software.
Bit 8
0: Interrupt is inhibited
1: An USART interrupt is generated whenever PE=1 in the USART_SR register
TXEIE: TXE Interrupt Enable.
This bit is set and cleared by software.
Bit 7
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TXE=1 in the USART_SR register
TCIE: Transmission Complete Interrupt Enable.
This bit is set and cleared by software.
Bit 6
0: Interrupt is inhibited
1: An USART interrupt is generated whenever TC=1 in the USART_SR register
RXNEIE: RXNE Interrupt Enable.
This bit is set and cleared by software.
Bit 5 0: Interrupt is inhibited
1: An USART interrupt is generated whenever ORE=1 or RXNE=1 in the
USART_SR register
IDLEIE: IDLE Interrupt Enable.
This bit is set and cleared by software.
Bit 4
0: Interrupt is inhibited
1: An USART interrupt is generated whenever IDLE=1 in the USART_SR register
TE: Transmitter Enable.
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Bit 3
Notes:
1: During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a
preamble (idle line) after the current word, except in smartcard mode.
2: When TE is set there is a 1 bit-time delay before the transmission starts.
RE: Receiver Enable.
This bit enables the receiver. It is set and cleared by software.
Bit 2
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit

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RWU: Receiver Wake-Up.

This bit determines if the USART is in mute mode or not. It is set and cleared by
software and can be cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode
Bit 1
Notes:
1: Before selecting Mute mode (by setting the RWU bit) the USART must first
receive a data byte, otherwise it cannot function in Mute mode with wake-up by Idle
line detection.
2: In Address Mark Detection Wake-Up configuration (WAKE bit=1) the RWU bit
cannot be modified by software while the RXNE bit is set.
SBK: Send Break.
This bit set is used to send break characters. It can be set and cleared by
software. It should be set by software, and will be reset by hardware during the
Bit 0
stop bit of break.
0: No break character is transmitted
1: Break character will be transmitted

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17.4.5 Control register 2 (USART_CR2)

Address Offset: 10h
Reset Value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLK
Res. LINEN STOP[1:0] CPOL CPHA LBCL Res. LBDIE LBDL Res. ADD[3:0]
EN

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:15 Reserved, forced by hardware to 0.

LINEN: LIN mode enable
This bit is set and cleared by software.
0: LIN mode disabled
Bit 14
1: LIN mode enabled
The LIN mode enables the capability to send LIN Synch Breaks (13 low bits)
using the SBK bit in the USART_CR1 register, and to detect LIN Sync breaks.
STOP: STOP bits.
These bits are used for programming the stop bits.
00: 1 Stop bit
Bits 13:12
01: 0.5 Stop bit
10: 2 Stop bits
11: 1.5 Stop bit
CLKEN: Clock Enable.
This bit allows the user to enable the SCLK pin.
Bit 11
0: SCLK pin disabled
1: SCLK pin enabled
CPOL: Clock Polarity.
This bit allows the user to select the polarity of the clock output on the SCLK pin
in synchronous mode. It works in conjunction with the CPHA bit to produce the
Bit 10
desired clock/data relationship
0: Steady low value on SCLK pin outside transmission window.
1: Steady high value on SCLK pin outside transmission window.
CPHA: Clock Phase
This bit allows the user to select the phase of the clock output on the SCLK pin in
synchronous mode. It works in conjunction with the CPOL bit to produce the
Bit 9
desired clock/data relationship (see figures 152 to 155)
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first data capture edge.

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LBCL: Last Bit Clock pulse.

This bit allows the user to select whether the clock pulse associated with the last
data bit transmitted (MSB) has to be output on the SCLK pin in synchronous
mode.
Bit 8 0: The clock pulse of the last data bit is not output to the SCLK pin.
1: The clock pulse of the last data bit is output to the SCLK pin.
Note:
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format
selected by the M bit in the USART_CR1 register.
Bit 7 Reserved, forced by hardware to 0.
LBDIE: LIN Break Detection Interrupt Enable.
Break interrupt mask (break detection using break delimiter).
Bit 6
0: Interrupt is inhibited
1: An interrupt is generated whenever LBD=1 in the USART_SR register
LBDL: LIN Break Detection Length.
This bit is for selection between 11 bit or 10 bit break detection.
Bit 5
0: 10 bit break detection
1: 11 bit break detection
Bit 4 Reserved, forced by hardware to 0.
ADD[3:0]: Address of the USART node.
This bit-field gives the address of the USART node.
Bits 3:0
This is used in multi-processor communication during mute mode, for wake up
with address mark detection.

Note: These 3 bits (CPOL, CPHA, LBCL) should not be written while the transmitter is enabled.

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17.4.6 Control register 3 (USART_CR3)

Address Offset: 14h
Reset Value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

HD
Reserved CTSIE CTSE RTSE DMAT DMAR SCEN NACK IRLP IREN EIE
SEL

rw rw rw rw rw rw rw rw rw rw rw

Bits 31:11 Reserved, forced by hardware to 0.

CTSIE: CTS Interrupt Enable.
Bit 10 0: Interrupt is inhibited
1: An interrupt is generated whenever CTS=1 in the USART_SR register
CTSE: CTS Enable.
0: CTS hardware flow control disabled
1: CTS mode enabled, data is only transmitted when the nCTS input is asserted
Bit 9 (tied to 0). If the nCTS input is deasserted while a data is being transmitted, then
the transmission is completed before stopping. If a data is written into the data
register while nCTS is asserted, the transmission is postponed until nCTS is
asserted.
RTSE: RTS Enable.
0: RTS hardware flow control disabled
Bit 8 1: RTS interrupt enabled, data is only requested when there is space in the
receive buffer. The transmission of data is expected to cease after the current
character has been transmitted. The nRTS output is asserted (tied to 0) when a
data can be received.
DMAT: DMA Enable Transmitter.
This bit is set/reset by software
Bit 7
1: DMA mode is enabled for transmission.
0: DMA mode is disabled for transmission.
DMAR: DMA Enable Receiver.
This bit is set/reset by software
Bit 6
1: DMA mode is enabled for reception.
0: DMA mode is disabled for reception.
SCEN: Smartcard mode enable.
This bit is used for enabling Smartcard mode.
Bit 5
0: Smartcard Mode disabled
1: Smartcard Mode enabled
NACK: Smartcard NACK enable.
Bit 4 0: NACK transmission in case of parity error is disabled
1: NACK transmission during parity error is enabled.

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HDSEL: Half-Duplex Selection.

Selection of Single-wire Half-duplex mode
Bit 3
0: Half duplex mode is not selected
1: Half duplex mode is selected
IRLP: IrDA Low-Power.
This bit is used for selecting between normal and low-power IrDA modes
Bit 2
0: Normal mode
1: Low-power mode
IREN: IrDA mode Enable.
This bit is set and cleared by software.
Bit 1
0: IrDA disabled
1: IrDA enabled
EIE: Error Interrupt Enable.
Error Interrupt Enable Bit is required to enable interrupt generation in case of a
framing error, overrun error or noise error (FE=1 or ORE=1 or NE=1 in the
USART_SR register) in case of Multi Buffer Communication (DMAR=1 in the
Bit 0
USART_CR3 register).
0: Interrupt is inhibited
1: An interrupt is generated whenever DMAR=1 in the USART_CR3 register and
FE=1 or ORE=1 or NE=1 in the USART_SR register.

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17.4.7 Guard time and prescaler register (USART_GTPR)

Address Offset: 18h
Reset Value: 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

GT[7:0] PSC[7:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:16 Reserved, forced by hardware to 0.

GT[7:0]: Guard time value.
This bit-field gives the Guard time value in terms of number of baud clocks.
Bits 15:8
This is used in Smartcard mode. The Transmission Complete flag is set after this
guard time value.
PSC[7:0]: Prescaler value.
– In IrDA Low-power mode:
PSC[7:0] = IrDA Low-Power Baud Rate
Used for programming the prescaler for dividing the system clock to achieve the
low-power frequency:
The source clock is divided by the value given in the register (8 significant bits):
00000000: Reserved - do not program this value
00000001: divides the source clock by 1
00000010: divides the source clock by 2
...
– In normal IrDA mode: PSC must be set to 00000001.

Bits 7:0 – In smartcard mode:

PSC[4:0]: Prescaler value.
Used for programming the prescaler for dividing the system clock to provide the
smartcard clock.
The value given in the register (5 significant bits) is multiplied by 2 to give the
division factor of the source clock frequency:
00000: Reserved - do not program this value
00001: divides the source clock by 2
00010: divides the source clock by 4
00011: divides the source clock by 6
...
Note:
1: Bits [7:5] have no effect if Smartcard mode is used.

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17.5 USART register map

Table 54. USART register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
RXNE
IDLE
ORE
CTS

TXE
LBD

NE
TC

PE
FE
USART_SR
00h Reserved

Reset Value 0 0 1 1 0 0 0 0 0 0

USART_DR DR[8:0]
04h Reserved

Reset Value 0 0 0 0 0 0 0 0 0

DIV_Fraction
USART_BRR DIV_Mantissa[15:4]
08h Reserved [3:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXNEIE
IDLEIE
WAKE

TXEIE

RWU
PEIE

TCIE
PCE

SBK
UE

RE
PS

TE
USART_CR1

M
0Ch Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CLKEN

Reserved

Reserved
LINEN

LBDIE
CPHA
CPOL

LBCL

LBDL
STOP
USART_CR2 ADD[3:0]
10h Reserved [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0

HDSEL
CTSIE

DMAR
SCEN
NACK
DMAT
CTSE
RTSE

IREN
IRLP

EIE
USART_CR3
14h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0

USART_GTPR GT[7:0] PSC[7:0]

18h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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UM0306 USB full speed device interface (USB)

18 USB full speed device interface (USB)

18.1 Introduction
The USB Peripheral implements an interface between a full-speed USB 2.0 bus and the
APB1 bus.
USB suspend/resume are supported which allows to stop the device clocks for low-power
consumption.

18.2 Main features

● USB specification version 2.0 Full speed compliant
● Configurable number of endpoints from 1 to 8
● Cyclic Redundancy Check (CRC) generation/checking, Non-Return-to-Zero Inverted
(NRZI) encoding/decoding and bit-stuffing
● Isochronous transfers support
● Double-buffered bulk/isochronous endpoint support
● USB Suspend/Resume operations
● Frame locked clock pulse generation

18.3 Block diagram

Figure 164 shows the block diagram of the USB Peripheral.

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Figure 164. USB Peripheral block diagram

D+ D-

Analog USB Clock (48MHz)

Transceiver PCLK1

USB
Control
RX-TX Clock
registers & logic
Suspend Recovery
Timer Control
Endpoint Interrupt
Selection registers & logic
S.I.E.

Packet
Buffer Endpoint Endpoint
Interface Registers Registers

Packet
Register Interrupt
Arbiter Buffer
Mapper Mapper
Memory

APB1 wrapper
APB1 Interface
PCLK1 APB1 bus IRQs to NVIC

18.4 Functional description

The USB Peripheral provides an USB compliant connection between the host PC and the
function implemented by the microcontroller. Data transfer between the host PC and the
system memory occurs through a dedicated packet buffer memory accessed directly by the
USB Peripheral. The size of this dedicated buffer memory must be according to the number
of endpoints used and the maximum packet size. This dedicated memory is sized to 512
bytes and up to 8 mono-directional/single-buffered endpoints can be used. The USB
Peripheral interfaces with the USB host, detecting token packets, handling data
transmission/reception, and processing handshake packets as required by the USB
standard. Transaction formatting is performed by the hardware, including CRC generation
and checking.
Each endpoint is associated with a buffer description block indicating where the endpoint
related memory area is located, how large it is or how many bytes must be transmitted.

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When a token for a valid function/endpoint pair is recognized by the USB Peripheral, the
related data transfer (if required and if the endpoint is configured) takes place. The data
buffered by the USB Peripheral is loaded in an internal 16 bit register and memory access to
the dedicated buffer is performed. When all the data has been transferred, if needed, the
proper handshake packet over the USB is generated or expected according to the direction
of the transfer.
At the end of the transaction, an endpoint-specific interrupt is generated, reading status
registers and/or using different interrupt response routines. The microcontroller can
determine:
● Which endpoint has to be served
● Which type of transaction took place, if errors occurred (bit stuffing, format, CRC,
protocol, missing ACK, over/underrun, etc.)
USB Peripheral
Special support is offered to Isochronous transfers and high throughput bulk transfers,
implementing a double buffer usage, which allows to always have an available buffer for the
USB Peripheral while the microcontroller uses the other one.
The unit can be placed in low-power mode (SUSPEND mode), by writing in the control
register, whenever required. At this time, all static power dissipation is avoided, and the USB
clock can be slowed down or stopped. The detection of activity at the USB inputs, while in
low-power mode, wakes the device up asynchronously. A special interrupt source can be
connected directly to a wake-up line to allow the system to immediately restart the normal
clock generation and/or support direct clock start/stop.

18.4.1 Description of USB blocks

The USB Peripheral implements all the features related to USB interfacing, which include
the following blocks:
● Serial Interface Engine (SIE): The functions of this block include: synchronization
pattern recognition, bit-stuffing, CRC generation and checking, PID
verification/generation, and handshake evaluation. It must interface with the USB
transceivers and uses the virtual buffers provided by the packet buffer interface for local
data storage,. This unit also generates signals according to USB Peripheral events,
such as Start of Frame (SOF), USB_Reset, Data errors etc. and to Endpoint related
events like end of transmission or correct reception of a packet; these signals are then
used to generate interrupts.
● Timer: This block generates the frame locked clock pulse for any external device
requiring Start-of-Frame synchronization and it detects a global suspend (from the
host) when no traffic has been received for 3 mS.
● Packet Buffer Interface: This block manages the local memory implementing a set of
buffers in a flexible way, both for transmission and reception. It can choose the proper
buffer according to requests coming from the SIE and locate them in the memory
addresses pointed by the Endpoint registers. It increments the address after each
exchanged word until the end of packet, keeping track of the number of exchanged
bytes and preventing the buffer to overrun the maximum capacity.
● Endpoint-Related Registers: Each endpoint has an associated register containing the
endpoint type and its current status. For mono-directional/single-buffer endpoints, a
single register can be used to implement two distinct endpoints. The number of
registers is 8, allowing up to 16 mono-directional/single-buffer or up to 7 double-buffer

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endpoints* in any combination. For example the USB Peripheral can be programmed to
have 4 doublebuffer endpoints and 8 single-buffer/mono-directional endpoints.
● Control Registers: These are the registers containing information about the status of
the whole USB Peripheral and used to force some USB events, such as resume and
power-down.
● Interrupt Registers: These contain the Interrupt masks and a record of the events. They
can be used to inquire an interrupt reason, the interrupt status or to clear the status of a
pending interrupt.
Note: * Endpoint 0 is always used for control transfer in single-buffer mode.
The USB Peripheral is connected to the APB1 bus through an APB1 interface, containing
the following blocks:
● Packet Memory: This is the local memory that physically contains the Packet Buffers. It
can be used by the Packet Buffer interface, which creates the data structure and can be
accessed directly by the application software. The size of the Packet Memory is 512
bytes, structured as 256 words by 16 bits.
● Arbiter: This block accepts memory requests coming from the APB1 bus and from the
USB interface. It resolves the conflicts by giving priority to APB1 accesses, while
always reserving half of the memory bandwidth to complete all USB transfers. This
time-duplex scheme implements a virtual dual-port SRAM that allows memory access,
while an USB transaction is happening. Multi-word APB1 transfers of any length are
also allowed by this scheme.
● Register Mapper: This block collects the various byte-wide and bit-wide registers of the
USB Peripheral in a structured 16-bit wide word set addressed by the APB1.
● Interrupt Mapper: This block is used to select how the possible USB events can
generate interrupts and map them to IRQ lines of the NVIC.
● APB1 Wrapper: This provides an interface to the APB1 for the memory and register. It
also maps the whole USB Peripheral in the APB1 address space.

18.5 Programming considerations

In the following sections, the expected interactions between the USB Peripheral and the
application program are described, in order to ease application software development.

18.5.1 Generic USB device programming

This part describes the main tasks required of the application software in order to obtain
USB compliant behavior. The actions related to the most general USB events are taken into
account and paragraphs are dedicated to the special cases of double-buffered endpoints
and Isochronous transfers. Apart from system reset, action is always initiated by the USB
Peripheral, driven by one of the USB events described below.

18.5.2 System and power-on reset

Upon system and power-on reset, the first operation the application software should perform
is to provide all required clock signals to the USB Peripheral and subsequently de-assert its
reset signal so to be able to access its registers. The whole initialization sequence is
hereafter described.

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As a first step application software needs to activate register macrocell clock and de-assert
macrocell specific reset signal using related control bits provided by device clock
management logic.
After that the analog part of the device related to the USB transceiver must be switched on
using the PDWN bit in CNTR register which requires a special handling. This bit is intended
to switch on the internal voltage references supplying the port transceiver. Since this circuits
have a defined startup time, during which the behavior of USB transceiver is not defined, it is
necessary to wait this time, after having set the PDWN bit in CNTR register, then the reset
condition on the USB part can be removed (clearing of FRES bit in CNTR register) and the
ISTR register can be cleared, removing any spurious pending interrupt, before enabling any
other macrocell operation.
As a last step the USB specific 48 MHz clock needs to be activated, using the related
control bits provided by device clock management logic.
At system reset, the microcontroller must initialize all required registers and the packet
buffer description table, to make the USB Peripheral able to properly generate interrupts and
data transfers. All registers not specific to any endpoint must be initialized according to the
needs of application software (choice of enabled interrupts, chosen address of packet
buffers, etc.). Then the process continues as for the USB reset case (see further
paragraph).

USB reset (RESET interrupt)

When this event occurs, the USB Peripheral is put in the same conditions it is left by the
system reset after the initialization described in the previous paragraph: communication is
disabled in all endpoint registers (the USB Peripheral will not respond to any packet). As a
response to the USB reset event, USB function must be enabled, having as USB address 0,
implementing only the default control endpoint (endpoint address is 0 too). This is
accomplished by setting the Enable Function (EF) bit of the register and initializing the
EP0R register and its related packet buffers accordingly. During USB enumeration process,
the host assigns a unique address to this device, which must be written in the ADD[6:0] bits
of the register, and configures any other necessary endpoint.
When a RESET interrupt is received, the application software is responsible to enable again
the default endpoint of USB function 0 within 10mS from the end of reset sequence which
triggered the interrupt.

Structure and usage of packet buffers

Each bidirectional endpoint may receive or transmit data from/to the host. The received data
is stored in a dedicated memory buffer reserved for that endpoint, while another memory
buffer contains the data to be transmitted by the endpoint. Access to this memory is
performed by the packet buffer interface block, which delivers a memory access request and
waits for its acknowledgement. Since the packet buffer memory has to be accessed by the
microcontroller also, an arbitration logic takes care of the access conflicts, using half APB1
cycle for microcontroller access and the remaining half for the USB Peripheral access. In
this way, both the agents can operate as if the packet memory is a dual-port SRAM, without
being aware of any conflict even when the microcontroller is performing back-to-back
accesses. The USB Peripheral logic uses a dedicated clock. The frequency of this dedicated
clock is fixed by the requirements of the USB standard at 48 MHz, and this can be different
from the clock used for the interface to the APB1 bus. Different clock configurations are
possible where the APB1 clock frequency can be higher or lower than the USB Peripheral
one.

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Note: Due to USB data rate and packet memory interface requirements, the APB1 clock frequency
must be greater than 8 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory at the address indicated by the register. Each table entry is
associated to an endpoint register and it is composed of four 16-bit words so that table start
address must always be aligned to an 8-byte boundary (the lowest three bits of register are
always “000”). Buffer descriptor table entries are described in the Section 18.6.3: Buffer
descriptor table. If an endpoint is unidirectional and it is neither an Isochronous nor a
double-buffered bulk, only one packet buffer is required (the one related to the supported
transfer direction). Other table locations related to unsupported transfer directions or unused
endpoints, are available to the user. isochronous and double-buffered bulk endpoints have
special handling of packet buffers (Refer to Section 18.5.4: Isochronous transfers and
Section 18.5.3: Double-buffered endpoints respectively). The relationship between buffer
description table entries and packet buffer areas is depicted in Figure 165.

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Figure 165. Packet buffer areas with examples of buffer description table locations

Buffer for
double-buffered
IN Endpoint 3

0001_1110 (1E) COUNT3_TX_1

0001_1100 (1C) ADDR3_TX_1
0001_1010 (1A) COUNT3_TX_0 Buffer for
0001_1000 (18) double-buffered
ADDR3_TX_0
OUT Endpoint 2
0001_0110 (16) COUNT2_RX_1
0001_0100 (14) ADDR2_RX_1
0001_0010 (12) COUNT2_RX_0
0001_0000 (10) ADDR2_RX_0 Transmission
buffer for
0000_1110 (0E) COUNT1_RX
single-buffered
0000_1100 (0C) ADDR1_RX Endpoint 1

0000_1010 (0A) COUNT1_TX

0000_1000 (08) ADDR1_TX Reception buffer
for
0000_0110 (06) COUNT0_RX
Endpoint 0
0000_0100 (04) ADDR0_RX
Transmission
0000_0010 (02) COUNT0_TX buffer for
Endpoint 0
0000_0000 (00) ADDR0_TX

Buffer description table locations Packet buffers

Each packet buffer is used either during reception or transmission starting from the bottom.
The USB Peripheral will never change the contents of memory locations adjacent to the
allocated memory buffers; if a packet bigger than the allocated buffer length is received
(buffer overrun condition) the data will be copied to the memory only up to the last available
location.

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Endpoint initialization
The first step to initialize an endpoint is to write appropriate values to the
ADDRn_TX/ADDRn_RX registers so that the USB Peripheral finds the data to be
transmitted already available and the data to be received can be buffered. The EP_TYPE
bits in the register must be set according to the endpoint type, eventually using the
EP_KIND bit to enable any special required feature. On the transmit side, the endpoint must
be enabled using the STAT_TX bits in the register and COUNTn_TX must be initialized. For
reception, STAT_RX bits must be set to enable reception and COUNTn_RX must be written
with the allocated buffer size using the BL_SIZE and NUM_BLOCK fields. Unidirectional
endpoints, except Isochronous and double-buffered bulk endpoints, need to initialize only
bits and registers related to the supported direction. Once the transmission and/or reception
are enabled, register and locations ADDRn_TX/ADDRn_RX, COUNTn_TX/COUNTn_RX
(respectively), should not be modified by the application software, as the hardware can
change their value on the fly. When the data transfer operation is completed, notified by a
CTR interrupt event, they can be accessed again to re-enable a new operation.

IN packets (data transmission)

When receiving an IN token packet, if the received address matches a configured and valid
endpoint one, the USB Peripheral accesses the contents of ADDRn_TX and COUNTn_TX
locations inside buffer descriptor table entry related to the addressed endpoint. The content
of these locations is stored in its internal 16 bit registers ADDR and COUNT (not accessible
by software). The packet memory is accessed again to read the first word to be transmitted
(Refer to Structure and usage of packet buffers on page 423) and starts sending a DATA0 or
DATA1 PID according to bit DTOG_TX. When the PID is completed, the first byte from the
word, read from buffer memory, is loaded into the output shift register to be transmitted on
the USB bus. After the last data byte is transmitted, the computed CRC is sent. If the
addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the
data packet, according to STAT_TX bits in the register.
The ADDR internal register is used as a pointer to the current buffer memory location while
COUNT is used to count the number of remaining bytes to be transmitted. Each word read
from the packet buffer memory is transmitted over the USB bus starting from the least
significant byte. Transmission buffer memory is read starting from the address pointed by
ADDRn_TX for COUNTn_TX/2 words. If a transmitted packet is composed of an odd
number of bytes, only the lower half of the last word accessed will be used.
On receiving the ACK receipt by the host, the register is updated in the following way:
DTOG_TX bit is toggled, the endpoint is made invalid by setting STAT_TX=10 (NAK) and bit
CTR_TX is set. The application software must first identify the endpoint, which is requesting
microcontroller attention by examining the EP_ID and DIR bits in the register. Servicing of
the CTR_TX event starts clearing the interrupt bit; the application software then prepares
another buffer full of data to be sent, updates the COUNTn_TX table location with the
number of byte to be transmitted during the next transfer, and finally sets STAT_TX to ‘11’
(VALID) to re-enable transmissions. While the STAT_TX bits are equal to ‘10’ (NAK), any IN
request addressed to that endpoint is NAKed, indicating a flow control condition: the USB
host will retry the transaction until it succeeds. It is mandatory to execute the sequence of
operations in the above mentioned order to avoid losing the notification of a second IN
transaction addressed to the same endpoint immediately following the one which triggered
the CTR interrupt.

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OUT and SETUP packets (data reception)

These two tokens are handled by the USB Peripheral more or less in the same way; the
differences in the handling of SETUP packets are detailed in the following paragraph about
control transfers. When receiving an OUT/SETUP PID, if the address matches a valid
endpoint, the USB Peripheral accesses the contents of the ADDRn_RX and COUNTn_RX
locations inside the buffer descriptor table entry related to the addressed endpoint. The
content of the ADDRn_RX is stored directly in its internal register ADDR. While COUNT is
now reset and the values of BL_SIZE and NUM_BLOCK bit fields, which are read within
COUNTn_RX content are used to initialize BUF_COUNT, an internal 16 bit counter, which is
used to check the buffer overrun condition (all these internal registers are not accessible by
software). Data bytes subsequently received by the USB Peripheral are packed in words
(the first byte received is stored as least significant byte) and then transferred to the packet
buffer starting from the address contained in the internal ADDR register while BUF_COUNT
is decremented and COUNT is incremented at each byte transfer. When the end of DATA
packet is detected, the correctness of the received CRC is tested and only if no errors
occurred during the reception, an ACK handshake packet is sent back to the transmitting
host. In case of wrong CRC or other kinds of errors (bit-stuff violations, frame errors, etc.),
data bytes are still copied in the packet memory buffer, at least until the error detection point,
but ACK packet is not sent and the ERR bit in register is set. However, there is usually no
software action required in this case: the USB Peripheral recovers from reception errors and
remains ready for the next transaction to come. If the addressed endpoint is not valid, a NAK
or STALL handshake packet is sent instead of the ACK, according to bits STAT_RX in the
register and no data is written in the reception memory buffers.
Reception memory buffer locations are written starting from the address contained in the
ADDRn_RX for a number of bytes corresponding to the received data packet length, CRC
included (i.e. data payload length + 2), or up to the last allocated memory location, as
defined by BL_SIZE and NUM_BLOCK, whichever comes first. In this way, the USB
Peripheral never writes beyond the end of the allocated reception memory buffer area. If the
length of the data packet payload (actual number of bytes used by the application) is greater
than the allocated buffer, the USB Peripheral detects a buffer overrun condition. in this case,
a STALL handshake is sent instead of the usual ACK to notify the problem to the host, no
interrupt is generated and the transaction is considered failed.
When the transaction is completed correctly, by sending the ACK handshake packet, the
internal COUNT register is copied back in the COUNTn_RX location inside the buffer
description table entry, leaving unaffected BL_SIZE and NUM_BLOCK fields, which
normally do not require to be re-written, and the register is updated in the following way:
DTOG_RX bit is toggled, the endpoint is made invalid by setting STAT_RX = ‘10’ (NAK) and
bit CTR_RX is set. If the transaction has failed due to errors or buffer overrun condition,
none of the previously listed actions take place. The application software must first identify
the endpoint, which is requesting microcontroller attention by examining the EP_ID and DIR
bits in the register. The CTR_RX event is serviced by first determining the transaction type
(SETUP bit in the register); the application software must clear the interrupt flag bit and get
the number of received bytes reading the COUNTn_RX location inside the buffer description
table entry related to the endpoint being processed. After the received data is processed,
the application software should set the STAT_RX bits to ‘11’ (Valid) in the , enabling further
transactions. While the STAT_RX bits are equal to ‘10’ (NAK), any OUT request addressed
to that endpoint is NAKed, indicating a flow control condition: the USB host will retry the
transaction until it succeeds. It is mandatory to execute the sequence of operations in the
above mentioned order to avoid losing the notification of a second OUT transaction
addressed to the same endpoint following immediately the one which triggered the CTR
interrupt.

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Control transfers
Control transfers are made of a SETUP transaction, followed by zero or more data stages,
all of the same direction, followed by a status stage (a zero-byte transfer in the opposite
direction). SETUP transactions are handled by control endpoints only and are very similar to
OUT ones (data reception) except that the values of DTOG_TX and DTOG_RX bits of the
addressed endpoint registers are set to 1 and 0 respectively, to initialize the control transfer,
and both STAT_TX and STAT_RX are set to ‘10’ (NAK) to let software decide if subsequent
transactions must be IN or OUT depending on the SETUP contents. A control endpoint must
check SETUP bit in the register at each CTR_RX event to distinguish normal OUT
transactions from SETUP ones. A USB device can determine the number and direction of
data stages by interpreting the data transferred in the SETUP stage, and is required to
STALL the transaction in the case of errors. To do so, at all data stages before the last, the
unused direction should be set to STALL, so that, if the host reverses the transfer direction
too soon, it gets a STALL as a status stage. While enabling the last data stage, the opposite
direction should be set to NAK, so that, if the host reverses the transfer direction (to perform
the status stage) immediately, it is kept waiting for the completion of the control operation. If
the control operation completes successfully, the software will change NAK to VALID,
otherwise to STALL. At the same time, if the status stage will be an OUT, the STATUS_OUT
(EP_KIND in the register) bit should be set, so that an error is generated if a status
transaction is performed with not-zero data. When the status transaction is serviced, the
application clears the STATUS_OUT bit and sets STAT_RX to VALID (to accept a new
command) and STAT_TX to NAK (to delay a possible status stage immediately following the
next setup).
Since the USB specification states that a SETUP packet cannot be answered with a
handshake different from ACK, eventually aborting a previously issued command to start the
new one, the USB logic doesn’t allow a control endpoint to answer with a NAK or STALL
packet to a SETUP token received from the host.
When the STAT_RX bits are set to ‘01’ (STALL) or ‘10’ (NAK) and a SETUP token is
received, the USB accepts the data, performing the required data transfers and sends back
an ACK handshake. If that endpoint has a previously issued CTR_RX request not yet
acknowledged by the application (i.e. CTR_RX bit is still set from a previously completed
reception), the USB discards the SETUP transaction and does not answer with any
handshake packet regardless of its state, simulating a reception error and forcing the host to
send the SETUP token again. This is done to avoid losing the notification of a SETUP
transaction addressed to the same endpoint immediately following the transaction, which
triggered the CTR_RX interrupt.

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18.5.3 Double-buffered endpoints

All different endpoint types defined by the USB standard represent different traffic models,
and describe the typical requirements of different kind of data transfer operations. When
large portions of data are to be transferred between the host PC and the USB function, the
bulk endpoint type is the most suited model. This is because the host schedules bulk
transactions so as to fill all the available bandwidth in the frame, maximizing the actual
transfer rate as long as the USB function is ready to handle a bulk transaction addressed to
it. If the USB function is still busy with the previous transaction when the next one arrives, it
will answer with a NAK handshake and the host PC will issue the same transaction again
until the USB function is ready to handle it, reducing the actual transfer rate due to the
bandwidth occupied by re-transmissions. For this reason, a dedicated feature called
‘double-buffering’ can be used with bulk endpoints.
When ‘double-buffering’ is activated, data toggle sequencing is used to select, which buffer
is to be used by the USB Peripheral to perform the required data transfers, using both
‘transmission’ and ‘reception’ packet memory areas to manage buffer swapping on each
successful transaction in order to always have a complete buffer to be used by the
application, while the USB Peripheral fills the other one. For example, during an OUT
transaction directed to a ‘reception’ double-buffered bulk endpoint, while one buffer is being
filled with new data coming from the USB host, the other one is available for the
microcontroller software usage (the same would happen with a ‘transmission’ double-
buffered bulk endpoint and an IN transaction).
Since the swapped buffer management requires the usage of all 4 buffer description table
locations hosting the address pointer and the length of the allocated memory buffers, the
registers used to implement double-buffered bulk endpoints are forced to be used as uni-
directional ones. Therefore, only one STAT bit pair must be set at a value different from ‘00’
(Disabled): STAT_RX if the double-buffered bulk endpoint is enabled for reception, STAT_TX
if the double-buffered bulk endpoint is enabled for transmission. In case it is required to have
double-buffered bulk endpoints enabled both for reception and transmission, two registers
must be used.
To exploit the double-buffering feature and reach the highest possible transfer rate, the
endpoint flow control structure, described in previous chapters, has to be modified, in order
to switch the endpoint status to NAK only when a buffer conflict occurs between the USB
Peripheral and application software, instead of doing it at the end of each successful
transaction. The memory buffer which is currently being used by the USB Peripheral is
defined by the DTOG bit related to the endpoint direction: DTOG_RX (bit 14 of register) for
‘reception’ double-buffered bulk endpoints or DTOG_TX (bit 6 of register) for ‘transmission’
double-buffered bulk endpoints. To implement the new flow control scheme, the USB
Peripheral should know which packet buffer is currently in use by the application software,
so to be aware of any conflict. Since in the register, there are two DTOG bits but only one is
used by USB Peripheral for data and buffer sequencing (due to the uni-directional constraint
required by double-buffering feature) the other one can be used by the application software
to show which buffer it is currently using. This new buffer flag is called SW_BUF. In the
following table the correspondence between register bits and DTOG/SW_BUF definition is
explained, for the cases of ‘transmission’ and ‘reception’ double-buffered bulk endpoints.

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Table 55. Double-buffering buffer flag definition

Buffer flag ‘Transmission’ endpoint ‘Reception’ endpoint

DTOG DTOG_TX ( bit 6) DTOG_RX ( bit 14)

SW_BUF bit 14 bit 6

The memory buffer which is currently being used by the USB Peripheral is defined by DTOG
buffer flag, while the buffer currently in use by application software is identified by SW_BUF
buffer flag. The relationship between the buffer flag value and the used packet buffer is the
same in both cases, and it is listed in the following table.

Table 56. Bulk double-buffering memory buffers usage

Endpoint Packet buffer used by USB Packet buffer used by
DTOG SW_BUF
Type Peripheral Application Software

ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1

0 1
Buffer description table locations. Buffer description table locations.
ADDRn_TX_1 / COUNTn_TX_1 ADDRn_TX_0 / COUNTn_TX_0
1 0
Buffer description table locations Buffer description table locations.
IN
ADDRn_TX_0 / COUNTn_TX_0
0 0 None *
Buffer description table locations.
ADDRn_TX_0 / COUNTn_TX_0
1 1 None *
Buffer description table locations.
ADDRn_RX_0 / COUNTn_RX_0 ADDRn_RX_1 / COUNTn_RX_1
0 1
Buffer description table locations. Buffer description table locations.
ADDRn_RX_1 / COUNTn_RX_1 ADDRn_RX_0 / COUNTn_RX_0
1 0
Buffer description table locations. Buffer description table locations.
OUT
ADDRn_RX_0 / COUNTn_RX_0
0 0 None *
Buffer description table locations.
ADDRn_RX_1 / COUNTn_RX_1
1 1 None *
Buffer description table locations.

Note: * Endpoint in NAK Status.

Double-buffering feature for a bulk endpoint is activated by:
● Writing EP_TYPE bit field at ‘00’ in its register, to define the endpoint as a bulk, and
● Setting EP_KIND bit at ‘1’ (DBL_BUF), in the same register.
The application software is responsible for DTOG and SW_BUF bits initialization according
to the first buffer to be used; this has to be done considering the special toggle-only property
that these two bits have. The end of the first transaction occurring after having set
DBL_BUF, triggers the special flow control of double-buffered bulk endpoints, which is used
for all other transactions addressed to this endpoint until DBL_BUF remain set. At the end of
each transaction the CTR_RX or CTR_TX bit of the addressed endpoint register is set,
depending on the enabled direction. At the same time, the affected DTOG bit in the register
is hardware toggled making the USB Peripheral buffer swapping completely software
independent. Unlike common transactions, and the first one after DBL_BUF setting, STAT
bit pair is not affected by the transaction termination and its value remains ‘11’ (Valid).
However, as the token packet of a new transaction is received, the actual endpoint status will

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be masked as ‘10’ (NAK) when a buffer conflict between the USB Peripheral and the
application software is detected (this condition is identified by DTOG and SW_BUF having
the same value, see Table 56 on page 430). The application software responds to the CTR
event notification by clearing the interrupt flag and starting any required handling of the
completed transaction. When the application packet buffer usage is over, the software
toggles the SW_BUF bit, writing ‘1’ to it, to notify the USB Peripheral about the availability of
that buffer. In this way, the number of NAKed transactions is limited only by the application
elaboration time of a transaction data: if the elaboration time is shorter than the time
required to complete a transaction on the USB bus, no re-transmissions due to flow control
will take place and the actual transfer rate will be limited only by the host PC.
The application software can always override the special flow control implemented for
double-buffered bulk endpoints, writing an explicit status different from ‘11’ (Valid) into the
STAT bit pair of the related register. In this case, the USB Peripheral will always use the
programmed endpoint status, regardless of the buffer usage condition.

18.5.4 Isochronous transfers

The USB standard supports full speed peripherals requiring a fixed and accurate data
production/consume frequency, defining this kind of traffic as ‘Isochronous’. Typical
examples of this data are: audio samples, compressed video streams, and in general any
sort of sampled data having strict requirements for the accuracy of delivered frequency.
When an endpoint is defined to be ‘isochronous’ during the enumeration phase, the host
allocates in the frame the required bandwidth and delivers exactly one IN or OUT packet
each frame, depending on endpoint direction. To limit the bandwidth requirements, no re-
transmission of failed transactions is possible for Isochronous traffic; this leads to the fact
that an isochronous transaction does not have a handshake phase and no ACK packet is
expected or sent after the data packet. For the same reason, Isochronous transfers do not
support data toggle sequencing and always use DATA0 PID to start any data packet.
The Isochronous behavior for an endpoint is selected by setting the EP_TYPE bits at ‘10’ in
its register; since there is no handshake phase the only legal values for the
STAT_RX/STAT_TX bit pairs are ‘00’ (Disabled) and ‘11’ (Valid), any other value will produce
results not compliant to USB standard. Isochronous endpoints implement double-buffering
to ease application software development, using both ‘transmission’ and ‘reception’ packet
memory areas to manage buffer swapping on each successful transaction in order to have
always a complete buffer to be used by the application, while the USB Peripheral fills the
other.
The memory buffer which is currently used by the USB Peripheral is defined by the DTOG
bit related to the endpoint direction (DTOG_RX for ‘reception’ isochronous endpoints,
DTOG_TX for ‘transmission’ isochronous endpoints, both in the related register) according
to Table 57.

Table 57. Isochronous memory buffers usage

Endpoint DTOG bit Packet buffer used by the Packet buffer used by the
Type value USB Peripheral application software

ADDRn_TX_0 / COUNTn_TX_0 ADDRn_TX_1 / COUNTn_TX_1

0 buffer description table buffer description table
locations. locations.
IN
ADDRn_TX_1 / COUNTn_TX_1 ADDRn_TX_0 / COUNTn_TX_0
1 buffer description table buffer description table
locations. locations.

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Table 57. Isochronous memory buffers usage

Endpoint DTOG bit Packet buffer used by the Packet buffer used by the
Type value USB Peripheral application software

ADDRn_RX_0 / COUNTn_RX_0 ADDRn_RX_1 / COUNTn_RX_1

0 buffer description table buffer description table
locations. locations.
OUT
ADDRn_RX_1 / COUNTn_RX_1 ADDRn_RX_0 / COUNTn_RX_0
1 buffer description table buffer description table
locations. locations.

As it happens with double-buffered bulk endpoints, the registers used to implement

Isochronous endpoints are forced to be used as uni-directional ones. In case it is required to
have Isochronous endpoints enabled both for reception and transmission, two registers
must be used.
The application software is responsible for the DTOG bit initialization according to the first
buffer to be used; this has to be done considering the special toggle-only property that these
two bits have. At the end of each transaction, the CTR_RX or CTR_TX bit of the addressed
endpoint register is set, depending on the enabled direction. At the same time, the affected
DTOG bit in the register is hardware toggled making buffer swapping completely software
independent. STAT bit pair is not affected by transaction completion; since no flow control is
possible for Isochronous transfers due to the lack of handshake phase, the endpoint
remains always ‘11’ (Valid). CRC errors or buffer-overrun conditions occurring during
Isochronous OUT transfers are anyway considered as correct transactions and they always
trigger an CTR_RX event. However, CRC errors will anyway set the ERR bit in the register
to notify the software of the possible data corruption.

18.5.5 Suspend/Resume events

The USB standard defines a special peripheral state, called SUSPEND, in which the
average current drawn from the USB bus must not be greater than 500 µA. This requirement
is of fundamental importance for bus-powered devices, while self-powered devices are not
required to comply to this strict power consumption constraint. In suspend mode, the host
PC sends the notification to not send any traffic on the USB bus for more than 3mS: since a
SOF packet must be sent every mS during normal operations, the USB Peripheral detects
the lack of 3 consecutive SOF packets as a suspend request from the host PC and set the
SUSP bit to ‘1’ in register, causing an interrupt if enabled. Once the device is suspended, its
normal operation can be restored by a so called RESUME sequence, which can be started
from the host PC or directly from the peripheral itself, but it is always terminated by the host
PC. The suspended USB Peripheral must be anyway able to detect a RESET sequence,
reacting to this event as a normal USB reset event.
The actual procedure used to suspend the USB peripheral is device dependent since
according to the device composition, different actions may be required to reduce the total
consumption.
A brief description of a typical suspend procedure is provided below, focused on the USB-
related aspects of the application software routine responding to the SUSP notification of
the USB Peripheral:
1. Set the FSUSP bit in the register to 1. This action activates the suspend mode within
the USB Peripheral. As soon as the suspend mode is activated, the check on SOF

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reception is disabled to avoid any further SUSP interrupts being issued while the USB
is suspended.
2. Remove or reduce any static power consumption in blocks different from the USB
Peripheral.
3. Set LP_MODE bit in register to 1 to remove static power consumption in the analog
USB transceivers but keeping them able to detect resume activity.
4. Optionally turn off external oscillator and device PLL to stop any activity inside the
device.
When an USB event occurs while the device is in SUSPEND mode, the RESUME procedure
must be invoked to restore nominal clocks and regain normal USB behavior. Particular care
must be taken to insure that this process does not take more than 10mS when the wakening
event is an USB reset sequence (See “Universal Serial Bus Specification” for more details).
The start of a resume or reset sequence, while the USB Peripheral is suspended, clears the
LP_MODE bit in register asynchronously. Even if this event can trigger an WKUP interrupt
if enabled, the use of an interrupt response routine must be carefully evaluated because of
the long latency due to system clock restart; to have the shorter latency before re-activating
the nominal clock it is suggested to put the resume procedure just after the end of the
suspend one, so its code is immediately executed as soon as the system clock restarts. To
prevent ESD discharges or any other kind of noise from waking-up the system (the exit from
suspend mode is an asynchronous event), a suitable analog filter on data line status is
activated during suspend; the filter width is about 70ns.
The following is a list of actions a resume procedure should address:
1. Optionally turn on external oscillator and/or device PLL.
2. Clear FSUSP bit of register.
3. If the resume triggering event has to be identified, bits RXDP and RXDM in the register
can be used according to Table 58, which also lists the intended software action in all
the cases. If required, the end of resume or reset sequence can be detected monitoring
the status of the above mentioned bits by checking when they reach the “10”
configuration, which represent the Idle bus state; moreover at the end of a reset
sequence the RESET bit in register is set to 1, issuing an interrupt if enabled, which
should be handled as usual.

Table 58. Resume event detection

[RXDP,RXDM] Status Wake-up event Required resume software action

“00” Root reset None

None
“10” Go back in Suspend mode
(noise on bus)
“01” Root resume None
Not Allowed
“11” Go back in Suspend mode
(noise on bus)

A device may require to exit from suspend mode as an answer to particular events not
directly related to the USB protocol (e.g. a mouse movement wakes up the whole system).
In this case, the resume sequence can be started by setting the RESUME bit in the register
to ‘1’ and resetting it to 0 after an interval between 1mS and 15mS (this interval can be
timed using ESOF interrupts, occurring with a 1mS period when the system clock is running
at nominal frequency). Once the RESUME bit is clear, the resume sequence will be

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completed by the host PC and its end can be monitored again using the RXDP and RXDM
bits in the register.
Note: The RESUME bit must be anyway used only after the USB Peripheral has been put in
suspend mode, setting the FSUSP bit in register to 1.

18.6 USB register description

The USB Peripheral registers can be divided into the following groups:
● Common Registers: Interrupt and Control registers
● Endpoint Registers: Endpoint configuration and status
● Buffer Descriptor Table: Location of packet memory used to locate data buffers
All register addresses are expressed as offsets with respect to the USB Peripheral registers
base address 0xC000 8000, except the buffer descriptor table locations, which starts at the
address specified by the register. Due to the common limitation of APB1 bridges on word
addressability, all register addresses are aligned to 32-bit word boundaries although they
are 16-bit wide. The same address alignment is used to access packet buffer memory
locations, which are located starting from 0xC000 8800.
Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

18.6.1 Common registers

These registers affect the general behavior of the USB Peripheral defining operating mode,
interrupt handling, device address and giving access to the current frame number updated
by the host PC.

USB control register ()

Address Offset: 40h
Reset Value: 0000 0000 0000 0011b (0003h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rw rw rw rw rw rw rw rw rw rw rw rw rw

CTRM: Correct Transfer Interrupt Mask

0: Correct Transfer (CTR) Interrupt disabled.
Bit 15
1: CTR Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.
PMAOVRM: Packet Memory Area Over / Underrun Interrupt Mask
0: PMAOVR Interrupt disabled.
Bit 14
1: PMAOVR Interrupt enabled, an interrupt request is generated when the
corresponding bit in the register is set.
ERRM: Error Interrupt Mask
0: ERR Interrupt disabled.
Bit 13
1: ERR Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.

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WKUPM: Wake-up Interrupt Mask

0: WKUP Interrupt disabled.
Bit 12
1: WKUP Interrupt enabled, an interrupt request is generated when the
corresponding bit in the register is set.
SUSPM: Suspend mode Interrupt Mask
0: Suspend Mode Request (SUSP) Interrupt disabled.
Bit 11
1: SUSP Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.
RESETM: USB Reset Interrupt Mask
0: RESET Interrupt disabled.
Bit 10
1: RESET Interrupt enabled, an interrupt request is generated when the
corresponding bit in the register is set.
SOFM: Start Of Frame Interrupt Mask
0: SOF Interrupt disabled.
Bit 9
1: SOF Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.
ESOFM: Expected Start Of Frame Interrupt Mask
0: Expected Start of Frame (ESOF) Interrupt disabled.
Bit 8
1: ESOF Interrupt enabled, an interrupt request is generated when the corresponding
bit in the register is set.
RESUME: Resume request
The microcontroller can set this bit to send a Resume signal to the host. It must be
Bit 4
activated, according to USB specifications, for no less than 1mS and no more than
15mS after which the Host PC is ready to drive the resume sequence up to its end.
FSUSP: Force suspend
Software must set this bit when the SUSP interrupt is received, which is issued when
no traffic is received by the USB Peripheral for 3 mS.
Bit 3 0: No effect.
1: Enter suspend mode. Clocks and static power dissipation in the analog transceiver
are left unaffected. If suspend power consumption is a requirement (bus-powered
device), the application software should set the LP_MODE bit after FSUSP as
explained below.
LP_MODE: Low-power mode
This mode is used when the suspend-mode power constraints require that all static
power dissipation is avoided, except the one required to supply the external pull-up
resistor. This condition should be entered when the application is ready to stop all
Bit 2 system clocks, or reduce their frequency in order to meet the power consumption
requirements of the USB suspend condition. The USB activity during the suspend
mode (WKUP event) asynchronously resets this bit (it can also be reset by software).
0: No Low-power mode.
1: Enter Low-power mode.

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PDWN: Power down

This bit is used to completely switch off all USB-related analog parts if it is required to
completely disable the USB Peripheral for any reason. When this bit is set, the USB
Bit 1
Peripheral is disconnected from the transceivers and it cannot be used.
0: Exit Power Down.
1: Enter Power down mode.
FRES: Force USB Reset
0: Clear USB reset.
Bit 0 1: Force a reset of the USB Peripheral, exactly like a RESET signalling on the USB.
The USB Peripheral is held in RESET state until software clears this bit. A “USB-
RESET” interrupt is generated, if enabled.

USB interrupt status register ()

Address Offset: 44h
Reset Value: 0000 0000 0000 0000 (0000h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PMA
CTR ERR WKUP SUSP RESET SOF ESOF DIR EP_ID[3:0]
OVR

r rc rc rc rc rc rc rc r r r r r

This register contains the status of all the interrupt sources allowing application software to
determine, which events caused an interrupt request.
The upper part of this register contains single bits, each of them representing a specific
event. These bits are set by the hardware when the related event occurs; if the
corresponding bit in the register is set, a generic interrupt request is generated. The
interrupt routine, examining each bit, will perform all necessary actions, and finally it will
clear the serviced bits. If any of them is not cleared, the interrupt is considered to be still
pending, and the interrupt line will be kept high again. If several bits are set simultaneously,
only a single interrupt will be generated.
Endpoint transaction completion can be handled in a different way to reduce interrupt
response latency. The CTR bit is set by the hardware as soon as an endpoint successfully
completes a transaction, generating a generic interrupt request if the corresponding bit in is
set. An endpoint dedicated interrupt condition is activated independently from the CTRM bit
in the register. Both interrupt conditions remain active until software clears the pending bit in
the corresponding register (the CTR bit is actually a read only bit). USB PeripheralFor
endpoint-related interrupts, the software can use the Direction of Transaction (DIR) and
EP_ID read-only bits to identify, which endpoint made the last interrupt request and called
the corresponding interrupt service routine.
The user can choose the relative priority of simultaneously pending events by specifying the
order in which software checks bits in an interrupt service routine. Only the bits related to
events, which are serviced, are cleared. At the end of the service routine, another interrupt
will be requested, to service the remaining conditions.
To avoid spurious clearing of some bits, it is recommended to clear them with a load
instruction where all bits which must not be altered are written with 1, and all bits to be
cleared are written with ‘0’ (these bits can only be cleared by software). Read-modify-write
cycles should be avoided because between the read and the write operations another bit
could be set by the hardware and the next write will clear it before the microprocessor has
the time to serve the event.

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The following describes each bit in detail:

CTR: Correct Transfer

This bit is set by the hardware to indicate that an endpoint has successfully completed a
Bit 15
transaction; using DIR and EP_ID bits software can determine which endpoint
requested the interrupt. This bit is read-only.
PMAOVR: Packet Memory Area Over / Underrun
This bit is set if the microcontroller has not been able to respond in time to an USB
memory request. The USB Peripheral handles this event in the following way: During
reception an ACK handshake packet is not sent, during transmission a bit-stuff error is
forced on the transmitted stream; in both cases the host will retry the transaction. The
Bit 14 PMAOVR interrupt should never occur during normal operations. Since the failed
transaction is retried by the host, the application software has the chance to speed-up
device operations during this interrupt handling, to be ready for the next transaction
retry; however this does not happen during Isochronous transfers (no isochronous
transaction is anyway retried) leading to a loss of data in this case. This bit is read/write
but only ‘0’ can be written and writing ‘1’ has no effect.
ERR: Error
This flag is set whenever one of the errors listed below has occurred:
NANS: No ANSwer. The timeout for a host response has expired.
CRC: Cyclic Redundancy Check error. One of the received CRCs, either in the token or
in the data, was wrong.
BST: Bit Stuffing error. A bit stuffing error was detected anywhere in the PID, data,
and/or CRC.
Bit 13 FVIO: Framing format Violation. A non-standard frame was received (EOP not in the
right place, wrong token sequence, etc.).
The USB software can usually ignore errors, since the USB Peripheral and the PC host
manage retransmission in case of errors in a fully transparent way. This interrupt can be
useful during the software development phase, or to monitor the quality of transmission
over the USB bus, to flag possible problems to the user (e.g. loose connector, too noisy
environment, broken conductor in the USB cable and so on). This bit is read/write but
only ‘0’ can be written and writing ‘1’ has no effect.
WKUP: Wake up
This bit is set to 1 by the hardware when, during suspend mode, activity is detected that
wakes up the USB Peripheral. This event asynchronously clears the LP_MODE bit in the
Bit 12
CTLR register and activates the USB_WAKEUP line, which can be used to notify the
rest of the device (e.g. wake-up unit) about the start of the resume process. This bit is
read/write but only ‘0’ can be written and writing ‘1’ has no effect.
SUSP: Suspend mode request
This bit is set by the hardware when no traffic has been received for 3mS, indicating a
suspend mode request from the USB bus. The suspend condition check is enabled
Bit 11
immediately after any USB reset and it is disabled by the hardware when the suspend
mode is active (FSUSP=1) until the end of resume sequence. This bit is read/write but
only ‘0’ can be written and writing ‘1’ has no effect.

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RESET: USB RESET request

Set when the USB Peripheral detects an active USB RESET signal at its inputs. The
USB Peripheral, in response to a RESET, just resets its internal protocol state machine,
generating an interrupt if RESETM enable bit in the register is set. Reception and
Bit 10 transmission are disabled until the RESET bit is cleared. All configuration registers do
not reset: the microcontroller must explicitly clear these registers (this is to ensure that
the RESET interrupt can be safely delivered, and any transaction immediately followed
by a RESET can be completed). The function address and endpoint registers are reset
by an USB reset event.
This bit is read/write but only ‘0’ can be written and writing ‘1’ has no effect.
SOF: Start Of Frame
This bit signals the beginning of a new USB frame and it is set when a SOF packet
arrives through the USB bus. The interrupt service routine may monitor the SOF events
Bit 9 to have a 1mS synchronization event to the USB host and to safely read the register
which is updated at the SOF packet reception (this could be useful for isochronous
applications). This bit is read/write but only ‘0’ can be written and writing ‘1’ has no
effect.
ESOF: Expected Start Of Frame
This bit is set by the hardware when an SOF packet is expected but not received. The
host sends an SOF packet each mS, but if the hub does not receive it properly, the
Bit 8 Timer issues this interrupt. If three consecutive ESOF interrupts are generated (i.e. three
SOF packets are lost) without any traffic occurring in between, a SUSP interrupt is
generated. This bit is set even when the missing SOF packets occur while the Timer is
not yet locked. This bit is read/write but only ‘0’ can be written and writing ‘1’ has no
effect.

DIR: Direction of transaction.

This bit is written by the hardware according to the direction of the successful
transaction, which generated the interrupt request.
If DIR bit=0, CTR_TX bit is set in the register related to the interrupting endpoint. The
interrupting transaction is of IN type (data transmitted by the USB Peripheral to the host
PC).
Bit 4 If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX are set in the register related to the
interrupting endpoint. The interrupting transaction is of OUT type (data received by the
USB Peripheral from the host PC) or two pending transactions are waiting to be
processed.
This information can be used by the application software to access the bits related to
the triggering transaction since it represents the direction having the interrupt pending.
This bit is read-only.
EP_ID[3:0]: Endpoint Identifier.
These bits are written by the hardware according to the endpoint number, which
generated the interrupt request. If several endpoint transactions are pending, the
hardware writes the endpoint identifier related to the endpoint having the highest priority
defined in the following way: Two endpoint sets are defined, in order of priority:
Bits 3:0 Isochronous and double-buffered bulk endpoints are considered first and then the other
endpoints are examined. If more than one endpoint from the same set is requesting an
interrupt, the EP_ID bits in register are assigned according to the lowest requesting
endpoint register, EP0R having the highest priority followed by EP1R and so on. The
application software can assign a register to each endpoint according to this priority
scheme, so as to order the concurring endpoint requests in a suitable way. These bits
are read only.

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USB frame number register ()

Address Offset: 48h
Reset Value: 0000 0xxx xxxx xxxxb (0xxxh)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RXDP RXDM LCK LSOF[1:0] FN[10:0]

r r r r r r r r r r r r r r r r

RXDP: Receive Data + Line Status

This bit can be used to observe the status of received data plus upstream port data
Bit 15
line. It can be used during end-of-suspend routines to help determining the wake-up
event.
RXDM: Receive Data - Line Status
This bit can be used to observe the status of received data minus upstream port data
Bit 14
line. It can be used during end-of-suspend routines to help determining the wake-up
event.
LCK: Locked
This bit is set by the hardware when at least two consecutive SOF packets have been
Bit 13 received after the end of an USB reset condition or after the end of an USB resume
sequence. Once locked, the frame timer remains in this state until an USB reset or
USB suspend event occurs.
LSOF[1:0]: Lost SOF
These bits are written by the hardware when an ESOF interrupt is generated, counting
Bits 12:11
the number of consecutive SOF packets lost. At the reception of an SOF packet, these
bits are cleared.
FN[10:0]: Frame Number
This bit field contains the 11-bits frame number contained in the last received SOF
Bits 10:0 packet. The frame number is incremented for every frame sent by the host and it is
useful for Isochronous transfers. This bit field is updated on the generation of an SOF
interrupt.

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USB device address ()

Address Offset: 4Ch
Reset Value: 0000 0000 0000 0000 (0000h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rw rw rw rw rw rw rw rw

EF: Enable Function

This bit is set by the software to enable the USB device. The address of this device is
Bit 7
contained in the following ADD[6:0] bits. If this bit is at ‘0’ no transactions are handled,
irrespective of the settings of registers.
ADD[6:0]: Device Address
These bits contain the USB function address assigned by the host PC during the
Bits 6:0 enumeration process. Both this field and the Endpoint Address (EA) field in the
associated register must match with the information contained in a USB token in
order to handle a transaction to the required endpoint.

Buffer table address ()

Address Offset: 50h
Reset Value: 0000 0000 0000 0000 (0000h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BTABLE[15:3] Reserved

rw rw rw rw rw rw rw rw rw rw rw rw rw

BTABLE[15:3]: Buffer Table.

These bits contain the start address of the buffer allocation table inside the dedicated
packet memory. This table describes each endpoint buffer location and size and it must
Bits 15:3 be aligned to an 8 byte boundary (the 3 least significant bits are always ‘0’). At the
beginning of every transaction addressed to this device, the USP peripheral reads the
element of this table related to the addressed endpoint, to get its buffer start location
and the buffer size (Refer to Structure and usage of packet buffers on page 423).
Bits 2:0 Reserved, forced by hardware to 0.

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18.6.2 Endpoint-specific registers

The number of these registers varies according to the number of endpoints that the USB
Peripheral is designed to handle. The USB Peripheral supports up to 8 bidirectional
endpoints. Each USB device must support a control endpoint whose address (EA bits) must
be set to 0. The USB Peripheral behaves in an undefined way if multiple endpoints are
enabled having the same endpoint number value. For each endpoint, an register is
available to store the endpoint specific information.

USB endpoint n register (), n=[0..7]

Address Offset: 00h to 1Ch
Reset value: 0000 0000 0000 0000b (0000h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CTR_ DTOG EP EP_ CTR_ DTOG_

STAT__X[1:0] SETUP STAT_TX[1:0] EA[3:0]
RX _RX TYPE[1:0] KIND TX TX

r-c t t t r rw rw rw r-c t t t rw rw rw rw

They are also reset when an USB reset is received from the USB bus or forced through bit
FRES in the CTLR register, except the CTR_RX and CTR_TX bits, which are kept
unchanged to avoid missing a correct packet notification immediately followed by an USB
reset event. Each endpoint has its register where n is the endpoint identifier.
Read-modify-write cycles on these registers should be avoided because between the read
and the write operations some bits could be set by the hardware and the next write would
modify them before the CPU has the time to detect the change. For this purpose, all bits
affected by this problem have an ‘invariant’ value that must be used whenever their
modification is not required. It is recommended to modify these registers with a load
instruction where all the bits, which can be modified only by the hardware, are written with
their ‘invariant’ value.

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CTR_RX: Correct Transfer for reception

This bit is set by the hardware when an OUT/SETUP transaction is successfully
completed on this endpoint; the software can only clear this bit. If the CTRM bit in
register is set accordingly, a generic interrupt condition is generated together with the
endpoint related interrupt condition, which is always activated. The type of occurred
Bit 15
transaction, OUT or SETUP, can be determined from the SETUP bit described below.
A transaction ended with a NAK or STALL handshake does not set this bit, since no
data is actually transferred, as in the case of protocol errors or data toggle
mismatches.
This bit is read/write but only ‘0’ can be written, writing 1 has no effect.
DTOG_RX: Data Toggle, for reception transfers
If the endpoint is not Isochronous, this bit contains the expected value of the data
toggle bit (0=DATA0, 1=DATA1) for the next data packet to be received. Hardware
toggles this bit, when the ACK handshake is sent to the USB host, following a data
packet reception having a matching data PID value; if the endpoint is defined as a
control one, hardware clears this bit at the reception of a SETUP PID addressed to this
endpoint.
If the endpoint is using the double-buffering feature this bit is used to support packet
buffer swapping too (Refer to Section 18.5.3: Double-buffered endpoints).
Bit 14 If the endpoint is Isochronous, this bit is used only to support packet buffer swapping
since no data toggling is used for this sort of endpoints and only DATA0 packet are
transmitted (Refer to Section 18.5.4: Isochronous transfers). Hardware toggles this bit
just after the end of data packet reception, since no handshake is used for isochronous
transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force specific data toggle/packet buffer usage.
When the application software writes ‘0’, the value of DTOG_RX remains unchanged,
while writing ‘1’ makes the bit value toggle. This bit is read/write but it can be only
toggled by writing 1.
STAT_RX [1:0]: Status bits, for reception transfers
These bits contain information about the endpoint status, which are listed in Table 59:
Reception status encoding on page 444.These bits can be toggled by software to
initialize their value. When the application software writes ‘0’, the value remains
unchanged, while writing ‘1’ makes the bit value toggle. Hardware sets the STAT_RX
bits to NAK when a correct transfer has occurred (CTR_RX=1) corresponding to a
OUT or SETUP (control only) transaction addressed to this endpoint, so the software
Bits 13:12 has the time to elaborate the received data before it acknowledge a new transaction
Double-buffered bulk endpoints implement a special transaction flow control, which
control the status based upon buffer availability condition (Refer to Section 18.5.3:
Double-buffered endpoints).
If the endpoint is defined as Isochronous, its status can be only “VALID” or
“DISABLED”, so that the hardware cannot change the status of the endpoint after a
successful transaction. If the software sets the STAT_RX bits to ‘STALL’ or ‘NAK’ for an
Isochronous endpoint, the USB Peripheral behavior is not defined. These bits are
read/write but they can be only toggled by writing ‘1’.
SETUP: Setup transaction completed
This bit is read-only and it is set by the hardware when the last completed transaction
is a SETUP. This bit changes its value only for control endpoints. It must be examined,
Bit 11 in the case of a successful receive transaction (CTR_RX event), to determine the type
of transaction occurred. To protect the interrupt service routine from the changes in
SETUP bits due to next incoming tokens, this bit is kept frozen while CTR_RX bit is at
1; its state changes when CTR_RX is at 0. This bit is read-only.

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EP_TYPE[1:0]: Endpoint type

These bits configure the behavior of this endpoint as described in Table 60: Endpoint
type encoding on page 445. Endpoint 0 must always be a control endpoint and each
USB function must have at least one control endpoint which has address 0, but there
may be other control endpoints if required. Only control endpoints handle SETUP
transactions, which are ignored by endpoints of other kinds. SETUP transactions
cannot be answered with NAK or STALL. If a control endpoint is defined as NAK, the
Bits 10:9 USB Peripheral will not answer, simulating a receive error, in the receive direction
when a SETUP transaction is received. If the control endpoint is defined as STALL in
the receive direction, then the SETUP packet will be accepted anyway, transferring
data and issuing the CTR interrupt. The reception of OUT transactions is handled in
the normal way, even if the endpoint is a control one.
Bulk and interrupt endpoints have very similar behavior and they differ only in the
special feature available using the EP_KIND configuration bit.
The usage of Isochronous endpoints is explained in Section 18.5.4: Isochronous
transfers
EP_KIND: Endpoint Kind
The meaning of this bit depends on the endpoint type configured by the EP_TYPE bits.
Table 61 summarizes the different meanings.
DBL_BUF: This bit is set by the software to enable the double-buffering feature for this
bulk endpoint. The usage of double-buffered bulk endpoints is explained in
Bit 8 Section 18.5.3: Double-buffered endpoints.
STATUS_OUT: This bit is set by the software to indicate that a status out transaction is
expected: in this case all OUT transactions containing more than zero data bytes are
answered ‘STALL’ instead of ‘ACK’. This bit may be used to improve the robustness of
the application to protocol errors during control transfers and its usage is intended for
control endpoints only. When STATUS_OUT is reset, OUT transactions can have any
number of bytes, as required.
CTR_TX: Correct Transfer for transmission
This bit is set by the hardware when an IN transaction is successfully completed on
this endpoint; the software can only clear this bit. If the CTRM bit in the register is set
accordingly, a generic interrupt condition is generated together with the endpoint
Bit 7 related interrupt condition, which is always activated.
A transaction ended with a NAK or STALL handshake does not set this bit, since no
data is actually transferred, as in the case of protocol errors or data toggle
mismatches.
This bit is read/write but only ‘0’ can be written.

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DTOG_TX: Data Toggle, for transmission transfers

If the endpoint is non-isochronous, this bit contains the required value of the data
toggle bit (0=DATA0, 1=DATA1) for the next data packet to be transmitted. Hardware
toggles this bit when the ACK handshake is received from the USB host, following a
data packet transmission. If the endpoint is defined as a control one, hardware sets
this bit to 1 at the reception of a SETUP PID addressed to this endpoint.
If the endpoint is using the double buffer feature, this bit is used to support packet
buffer swapping too (Refer to Section 18.5.3: Double-buffered endpoints)
Bit 6 If the endpoint is Isochronous, this bit is used to support packet buffer swapping since
no data toggling is used for this sort of endpoints and only DATA0 packet are
transmitted (Refer to Section 18.5.4: Isochronous transfers). Hardware toggles this bit
just after the end of data packet transmission, since no handshake is used for
Isochronous transfers.
This bit can also be toggled by the software to initialize its value (mandatory when the
endpoint is not a control one) or to force a specific data toggle/packet buffer usage.
When the application software writes ‘0’, the value of DTOG_TX remains unchanged,
while writing ‘1’ makes the bit value toggle. This bit is read/write but it can only be
toggled by writing 1.
STAT_TX [1:0]: Status bits, for transmission transfers
These bits contain the information about the endpoint status, listed in Table 62. These
bits can be toggled by the software to initialize their value. When the application
software writes ‘0’, the value remains unchanged, while writing ‘1’ makes the bit value
toggle. Hardware sets the STAT_TX bits to NAK, when a correct transfer has occurred
(CTR_TX=1) corresponding to a IN or SETUP (control only) transaction addressed to
this endpoint. It then waits for the software to prepare the next set of data to be
Bits 5:4 transmitted.
Double-buffered bulk endpoints implement a special transaction flow control, which
controls the status based on buffer availability condition (Refer to Section 18.5.3:
Double-buffered endpoints).
If the endpoint is defined as Isochronous, its status can only be “VALID” or
“DISABLED”. Therefore, the hardware cannot change the status of the endpoint after a
successful transaction. If the software sets the STAT_TX bits to ‘STALL’ or ‘NAK’ for an
Isochronous endpoint, the USB Peripheral behavior is not defined. These bits are
read/write but they can be only toggled by writing ‘1’.
EA[3:0]: Endpoint Address.
Software must write in this field the 4-bit address used to identify the transactions
Bits 3:0
directed to this endpoint. A value must be written before enabling the corresponding
endpoint.

Table 59. Reception status encoding

STAT_RX[1:0] Meaning

00 DISABLED: all reception requests addressed to this endpoint are ignored.

STALL: the endpoint is stalled and all reception requests result in a STALL
01
handshake.
10 NAK: the endpoint is naked and all reception requests result in a NAK handshake.
11 VALID: this endpoint is enabled for reception.

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Table 60. Endpoint type encoding

EP_TYPE[1:0] Meaning

00 BULK
01 CONTROL
10 ISO
11 INTERRUPT

Table 61. Endpoint kind meaning

EP_TYPE[1:0] EP_KIND Meaning

00 BULK DBL_BUF
01 CONTROL STATUS_OUT
10 ISO Not used
11 INTERRUPT Not used

Table 62. Transmission status encoding

STAT_TX[1:0] Meaning

00 DISABLED: all transmission requests addressed to this endpoint are ignored.

STALL: the endpoint is stalled and all transmission requests result in a STALL
01
handshake.
NAK: the endpoint is naked and all transmission requests result in a NAK
10
handshake.
11 VALID: this endpoint is enabled for transmission.

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18.6.3 Buffer descriptor table

USB PeripheralIn the following pages two location addresses are reported: the one to be
used by application software while accessing the packet memory, and the local one relative
to accessThe buffer description table entry associated with the registers is described
below. A thorough explanation of packet buffers and buffer descriptor table usage can be
found in the Structure and usage of packet buffers on page 423.

Transmission buffer address n ()

Address Offset: [] + n*16
USB local Address: [] + n*8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_TX[15:1] -

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw -

ADDRn_TX[15:1]: Transmission Buffer Address

These bits point to the starting address of the packet buffer containing data to be
Bits 15:1
transmitted by the endpoint associated with the register at the next IN token addressed
to it.
Must always be written as ‘0’ since packet memory is word-wide and all packet buffers
Bit 0
must be word-aligned.

Transmission byte count n ()

Address Offset: [] + n*16 + 4
USB local Address: [] + n*8 + 2

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- COUNTn_TX[9:0]

rw rw rw rw rw rw rw rw rw rw

These bits are not used since packet size is limited by USB specifications to 1023 bytes.
Bits 15:10
Their value is not considered by the USB Peripheral.
COUNTn_TX[9:0]: Transmission Byte Count
Bits 9:0 These bits contain the number of bytes to be transmitted by the endpoint associated
with the register at the next IN token addressed to it.
Double-buffered and Isochronous IN Endpoints have two
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

- COUNTn_TX_1[9:0]

- - - - - - rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

- COUNTn_TX_0[9:0]

- - - - - - rw rw rw rw rw rw rw rw rw rw

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Reception buffer address n ()

Address Offset: [] + n*16 + 8
USB local Address: [] + n*8 + 4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRn_RX[15:1] -

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw -

ADDRn_RX[15:1]: Reception Buffer Address

These bits point to the starting address of the packet buffer, which will contain the
Bits 15:1
data received by the endpoint associated with the register at the next OUT/SETUP
token addressed to it.
This bit must always be written as ‘0’ since packet memory is word-wide and all packet
Bit 0
buffers must be word-aligned.

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Reception byte count n ()

Address Offset: [] + n*16 + 12
USB local Address: [] + n*8 + 6

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLSIZE NUM_BLOCK[4:0] COUNTn_RX[9:0]

rw rw rw rw rw rw r r r r r r r r r r

This table location is used to store two different values, both required during packet
reception. The most significant bits contains the definition of allocated buffer size, to allow
buffer overflow detection, while the least significant part of this location is written back by the
USB Peripheral at the end of reception to give the actual number of received bytes. Due to
the restrictions on the number of available bits, buffer size is represented using the number
of allocated memory blocks, where block size can be selected to choose the trade-off
between fine-granularity/small-buffer and coarse-granularity/large-buffer. The size of
allocated buffer is a part of the endpoint descriptor and it is normally defined during the
enumeration process according to its maxPacketSize parameter value (See “Universal
Serial Bus Specification”).

BL_SIZE: BLock SIZE.

This bit selects the size of memory block used to define the allocated buffer area.
– If BL_SIZE=0, the memory block is 2 byte large, which is the minimum block allowed
in a word-wide memory. With this block size the allocated buffer size ranges from 2 to
Bit 15 62 bytes.
– If BL_SIZE=1, the memory block is 32 byte large, which allows to reach the
maximum packet length defined by USB specifications. With this block size the
allocated buffer size ranges from 32 to 1024 bytes, which is the longest packet size
allowed by USB standard specifications.
NUM_BLOCK[4:0]: Number of blocks.
These bits define the number of memory blocks allocated to this packet buffer. The
Bits 14:10
actual amount of allocated memory depends on the BL_SIZE value as illustrated in
Table 63.
COUNTn_RX[9:0]: Reception Byte Count
Bits 9:0 These bits contain the number of bytes received by the endpoint associated with the
register during the last OUT/SETUP transaction addressed to it.
Double-buffered and Isochronous OUT Endpoints have two
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

BLSIZE
NUM_BLOCK_1[4:0] COUNTn_RX_1[9:0]
_1

rw rw rw rw rw rw r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BLSIZE
NUM_BLOCK_0[4:0] COUNTn_RX_0[9:0]
_0

rw rw rw rw rw rw r r r r r r r r r r

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Table 63. Definition of allocated buffer memory

Value of Memory allocated Memory allocated
NUM_BLOCK[4:0] when BL_SIZE=0 when BL_SIZE=1

0 (‘00000’) Not allowed 32 bytes

1 (‘00001’) 2 bytes 64 bytes
2 (‘00010’) 4 bytes 96 bytes
3 (‘00011’) 6 bytes 128 bytes
... ... ...
15 (‘01111’) 30 bytes 512 bytes
16 (‘10000’) 32 bytes N/A
17 (‘10001’) 34 bytes N/A
18 (‘10010’) 36 bytes N/A
... ... ...
30 (‘11110’) 60 bytes N/A
31 (‘11111’) 62 bytes N/A

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18.7 USB Register map

Table 64. USB register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_

SETUP
USB_EP0R RX TYPE TX EA[3:0]
00h Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_

SETUP
USB_EP1R RX TYPE TX EA[3:0]
04h Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_

SETUP
USB_EP2R RX TYPE TX EA[3:0]
08h Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_

SETUP
USB_EP3R RX TYPE TX EA[3:0]
0Ch Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_

SETUP
USB_EP4R RX TYPE TX EA[3:0]
10h Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0
DTOG_RX 0 0 0 0 0 0 0 0 0 0 0 0 0 0

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_

SETUP
USB_EP5R RX TYPE TX EA[3:0]
14h Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX
STAT_ EP STAT_
SETUP

USB_EP6R RX TYPE TX EA[3:0]

18h Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DTOG_RX

DTOG_TX
EP_KIND
CTR_RX

CTR_TX

STAT_ EP STAT_
SETUP

USB_EP7R RX TYPE TX EA[3:0]

1Ch Reserved
[1:0] [1:0] [1:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
20h-3Fh Reserved
PMAOVRM

RESUME

LPMODE
RESETM
WKUPM

ESOFM
SUSPM

FSUSP

PDWN
ERRM
CTRM

SOFM

FRES
40h Reserved Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 1 1
PMAOVR

RESET
WKUP

ESOF
SUSP
ERR

SOF
CTR

DIR

EP_ID[3:0]
44h Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0
RXDM
RXDP

LSOF
LCK

FN[10:0]
48h Reserved [1:0]
Reset Value 0 0 0 0 0 x x x x x x x x x x x

EF ADD[6:0]
4Ch Reserved Reserved
Reset Value 0 0 0 0 0 0 0 0

BTABLE[15:3]
50h Reserved Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0

Note: Refer to Table 1 on page 27 for the register boundary addresses.

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19 Analog/digital converter (ADC)

19.1 Introduction
The 12-bit ADC is a successive approximation Analog to Digital Converter. It has up to 18
multiplexed channels allowing it measure signals from 16 external and two internal sources.
A/D Conversion of the various channels can be performed in single, continuous, scan or
discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit
data register.
The Analog Watchdog feature allows the application to detect if the input voltage goes
outside the user-defined high or low thresholds.

19.2 Main features

● 12-bit resolution
● Interrupt generation at End of Conversion, End of Injected conversion and Analog
Watchdog event
● Single and continuous conversion modes
● Scan mode for automatic conversion of channel 0 to channel ‘n’
● Self-calibration
● Data alignment with in-built data coherency
● Channel by channel programmable sampling time
● External trigger option for both regular and injected conversion
● Discontinuous mode
● Dual mode (on devices with 2 ADCs)
● ADC conversion rate 1 MHz
● ADC supply requirement: 2.4V to 3.6V
● ADC input range: VREF- ≤ VIN ≤ VREF+
● DMA request generation during regular channel conversion
The block diagram of the ADC is shown in Figure 166.
Note: VREF-,if available (depending on package), must be tied to VSSA.

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Figure 166. Single ADC block diagram

Interrupt
Flags enable bits
End of Conversion
EOC EOCIE
End of Injected Conversion ADC Interrupt to NVIC
JEOC JEOCIE
Analog Watchdog Event
AWD AWDIE

ANALOG WATCHDOG
Compare Result
High Threshold (12 bits)
Low Threshold (12 bits)

Address/data bus
INJECTED DATA REGISTERS
VREF+ (4 x 16 bits)
VREF-
REGULAR DATA REGISTER
VDDA (16 bits)
VSSA
ANALOG DMA request
MUX
ADC_IN0

ADC_IN1
GPIO up to 4 INJECTED
ADCCLK
Ports CHANNELS ANALOG TO DIGITAL

up to 16 CONVERTER
REGULAR
ADC_IN15 CHANNELS

Temp. sensor
VREFINT

From ADC prescaler

JEXTSEL[2:0] bits
TIM1_TRGO
TIM1_CH4 JEXTRIG
TIM2_TRGO bit
TIM2_CH1
Start trigger
TIM3_CH4 EXTRIG
TIM4_TRGO (injected group)
EXTI_15 bit

EXTSEL[2:0] bits
TIM1_CH1
TIM1_CH2 Start trigger
TIM1_CH3 (regular group)
TIM2_CH2
TIM3_TRGO
TIM4_CH4
EXTI_11

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19.3 Pin description

Table 65. ADC pins
Name Signal type Remarks

Input, Analog The higher/positive reference voltage for the ADC,

VREF+
Reference positive VSSA ≤ VREF+ ≤ VDDA
Input, Analog Analog power supply equal to VDD and
VDDA
supply 2.4V ≤ VDDA ≤ VDD (3.6V)
Input, Analog The lower/negative reference voltage for the ADC,
VREF-
Reference negative VREF- = VSSA
Input, Analog
VSSA Ground for analog power supply equal to VSS
supply ground
Analog input
ADC_IN[15:0] 16 analog input channels
signals
EXTSEL[2:0] input, digital Six external triggers for starting regular group conversion
JEXTSEL[2:0] input, digital Six external triggers for starting injected group conversion

19.4 Functional description

19.4.1 ADC on-off control

The ADC can be powered-on by setting the ADON bit in the ADC_CR1 register. When the
ADON bit is set for the first time, it wakes up the ADC from Power Down mode.
Conversion starts when ADON bit is set for a second time by software after ADC power-up
time (tSTAB).
You can stop conversion and put the ADC in power down mode by resetting the ADON bit. In
this mode the ADC consumes almost no power (only a few µA).

19.4.2 ADC clock

The ADCCLK clock provided by the Clock Controller is synchronous with the PCLK2 (APB2
clock). The CLK controller provides has a dedicated programmable prescaler for the ADC
clock, refer to the CLK chapter for more details.

19.4.3 Channel selection

There are 16 multiplexed channels. It is possible to organize the conversions in two groups:
regular and injected. A group consists of a sequence of conversions which can be done on
any channel and in any order. For instance, it is possible to do the conversion in the
following order: Ch3, Ch8, Ch2, Ch2, Ch0, Ch2, Ch2, Ch15.
● The regular group is composed of up to 16 conversions. The regular channels and
their order in the conversion sequence must be selected in the ADC_SQRx registers.
The total number of conversions in the regular group must be written in the L[3:0] bits in
the ADC_SQR1 register.
● The injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.

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The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current
conversion is reset and a new start pulse is sent to the ADC to convert the new chosen
group.

Temperature sensor/VREFINT internal channels

The Temperature sensor is connected to channel ADC_IN16 and the internal reference
voltage VREFINT is connected to ADC_IN17. These two internal channels can be selected
and converted as injected or regular channels.
Note: The sensor and VREFINT are only available on the master ADC peripheral.

19.4.4 Single conversion mode

In Single conversion mode the ADC does one conversion. This mode is started either by
setting the ADON bit in the ADC_CR2 register (for a regular channel only) or by external
trigger (for a regular or injected channel), while the CONT bit is 0.
Once the conversion of the selected channel is complete:
● If a regular channel was converted:
– The converted data is stored in the 16-bit ADC_DR register
– The EOC (End Of Conversion) flag is set
– and an interrupt is generated if the EOCIE is set.
● If an injected channel was converted:
– The converted data is stored in the 16-bit ADC_DRJ1 register
– The JEOC (End Of Conversion Injected) flag is set
– and an interrupt is generated if the JEOCIE bit is set.
The ADC is then stopped.

19.4.5 Continuous conversion mode

In continuous conversion mode ADC starts another conversion as soon as it finishes one.
This mode is started either by external trigger or by setting the ADON bit in the ADC_CR2
register, while the CONT bit is 1.
After each conversion:
● If a regular channel was converted:
– The converted data is stored in the 16-bit ADC_DR register
– The EOC (End Of Conversion) flag is set
– An interrupt is generated if the EOCIE is set.
● If an injected channel was converted:
– The converted data is stored in the 16-bit ADC_DRJ1 register
– The JEOC (End Of Conversion Injected) flag is set
– An interrupt is generated if the JEOCIE bit is set.

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19.4.6 Timing diagram

As shown in Figure 167, the ADC needs a stabilization time of tSTAB before it starts
converting accurately. After the start of ADC conversion and after 14 clock cycles, the EOC
flag is set and the 16-bit ADC Data register contains the result of the conversion.

Figure 167. Timing diagram

ADC_CLK

SET ADON

ADC power on Start 1st conversion Start next conversion

ADC Conversion Next ADC Conversion

ADC
tSTAB
Conversion Time
(total conv time)
EOC

Software resets EOC bit

19.4.7 Analog watchdog

The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a low threshold or above a high threshold. These thresholds are programmed in the
12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be
enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The comparison is done before the alignment (see Section 19.6).
The analog watchdog can be enabled one or more channels by configuring the ADC_CR1
register as shown in Table 66.

Figure 168. Analog watchdog guarded area

Analog voltage

High threshold HTR

Guarded area
Low threshold LTR

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Table 66. Analog watchdog channel selection

ADC_CR1 register control bits (x = don’t care)
Channels to be guarded by Analog
Watchdog
AWDSGL bit AWDEN bit JAWDEN bit

None x 0 0
All injected channels 0 0 1
All regular channels 0 1 0
All regular and injected channels 0 1 1
(1)
Single injected channel 1 0 1
(1)
Single regular channel 1 1 0
Single (1) regular or injected channel 1 1 1
1. Selected by AWDCH[4:0] bits

19.4.8 Scan mode

This mode is used to scan a group of analog channels.
Scan mode can be selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
is set, ADC scans all the channels selected in the ADC_SQRx registers (for regular
channels) or in the ADC_JSQR (for injected channels). A single conversion is performed for
each channel of the group. After each end of conversion the next channel of the group is
converted automatically. If the CONT bit is set, conversion does not stop at the last selected
group channel but continues again from the first selected group channel.
If the DMA bit is set, the direct memory access controller is used to transfer the converted
data of regular group channels to SRAM after each EOC.
The injected channel converted data is always stored in the ADC_JDRx registers.

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19.4.9 Injected channel management

Triggered injection
To use triggered injection, the JAUTO bit must be cleared and SCAN bit must be set in the
ADC_CR1 register.
1. Start conversion of a group of regular channels either by external trigger or by setting
the ADON bit in the ADC_CR2 register.
2. If an external injected trigger occurs during the regular group channel conversion, the
current conversion is reset and the injected channel sequence is converted in Scan
once mode.
3. Then, the regular group channel conversion is resumed from the last interrupted
regular conversion. If a regular event occurs during an injected conversion, it doesn’t
interrupt it but the regular sequence is executed at the end of the injected sequence.
Figure 169 shows the timing diagram.

Auto-injection
If the JAUTO bit is set, then the injected group channels are automatically converted after
the regular group channels. This can be used to convert a sequence of up to 20 conversions
programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note: It is not possible to use both auto-injected and discontinuous modes simultaneously.

Figure 169. Injected Conversion Latency

ADC clock

Inj. event

Reset ADC

SOC
max latency

19.4.10 Discontinuous mode

Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to
convert a short sequence of n conversions (n <=8) which is a part of the sequence of
conversions selected in the ADC_SQRx registers. The value of n is specified by writing to
the DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.

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Example:
n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10
1st trigger: sequence converted 0, 1, 2
2nd trigger: sequence converted 3, 6, 7
3rd trigger: sequence converted 9, 10 and an EOC event generated
4th trigger: sequence converted 0, 1, 2
Note: When a regular group is converted in discontinuous mode, no rollover will occur.
When all sub groups are converted, the next trigger starts conversion of the first sub-group.
In the example above, the 4th trigger reconverts the 1st sub-group channels 0, 1 and 2.

Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to
convert the sequence selected in the ADC_JSQR register, channel by channel, after an
external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
n = 1, channels to be converted = 1, 2, 3
1st trigger: channel 1 converted
2nd trigger: channel 2 converted
3rd trigger: channel 3 converted and EOC and JEOC events generated
4th trigger: channel 1
Note: 1 When all injected channels are converted, the next trigger starts the conversion of the first
injected channel. In the example above, the 4th trigger reconverts the 1st injected channel
1.
2 It is not possible to use both auto-injected and discontinuous modes simultaneously.
3 The user must avoid setting discontinuous mode for both regular and injected groups
together. Discontinuous mode must be enabled only for one group conversion.

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19.5 Calibration
The ADC has an built-in self calibration mode. Calibration significantly reduces accuracy
errors due to internal capacitor bank variations. During calibration, an error-correction code
(digital word) is calculated for each capacitor, and during all subsequent conversions, the
error contribution of each capacitor is removed using this code.
Calibration is started by setting the CAL bit in the ADC_CR2 register. Once calibration is
over, the CAL bit is reset by hardware and normal conversion can be performed. It is
recommended to calibrate the ADC once at power-on. The calibration codes are stored in
the ADC_DR as soon as the calibration phase ends.
Note: 1 It is recommended to perform a calibration after each power-up.
2 Before starting a calibration the ADC must have been in power-off state (ADON bit = ‘0’) for
at least two ADC clock cycles.

Figure 170. Calibration timing diagram

CLK

Calibration Reset by Hardware

Calibration ongoing
CAL tCAL

Normal ADC Conversion

ADC
Conversion

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19.6 Data alignment

ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion.
Data can be left or right aligned as shown in Figure 171. and Figure 172.
The injected group channels converted data value is decreased by the user-defined offset
written in the ADC_JOFRx registers so the result can be a negative value. The SEXT bit is
the extended sign value.
For regular group channels no offset is subtracted so only twelve bits are significant.

Figure 171. Right alignment of data

Injected group

SEXT SEXT SEXT SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Regular group

0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 172. Left alignment of data

Injected group

SEXT D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0

Regular group

D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0

19.7 Channel-by-channel programmable sample time

ADC samples the input voltage for a number of ADC_CLK cycles which can be modified us-
ing the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can be
sampled with a different sample time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12.5 cycles
Example:
With an ADCCLK = 14 MHz and a sampling time of 1.5 cycles:
Tconv = 1.5 + 12.5 = 14 cycles = 1µs

19.8 Conversion on external trigger

Conversion can be triggered by an external event (e.g. timer capture, external interrupt). If
the EXTTRIG control bit is set then external event are able to trigger a conversion. The EXT-
SEL[2:0] and JEXTSEL[2:0] control bit allow the application to select decide which out of 8
possible events can trigger conversion for the regular and injected groups.
Note: When an external trigger is selected for ADC regular or injected conversion, only the rising
edge of the signal can start the conversion.

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Table 67. External trigger for regular channels

Source Type EXTSEL[2:0]

Timer 1 CC1 output 000

Timer 1 CC2 output 001
Timer 1 CC3 output Internal signal from on-chip 010
Timer 2 CC2 output timers 011
Timer 3 TRGO output 100
Timer 4 CC4 output 101
External Interrupt 11 External pin 110
SWSTART Software control bit 111

Table 68. External trigger for injected channels

Source Connection Type JEXTSEL[2:0]

Timer 1 TRGO output 000

Timer 1 CC4 output 001
Timer 2 TRGO output Internal signal from on-chip 010
Timer 2 CC1 output timers 011
Timer 3 CC4 output 100
Timer 4 TRGO output 101
External Interrupt 15 External pin 110
JSWSTART Software control bit 111

One of these events can be generated by setting a bit in a register (SWSTART and
JSWSTART in ADC_CR2).
A regular group conversion can be interrupted by a injected trigger.

19.9 DMA request

Since converted regular channels value are stored in a unique data register, it is necessary
to use DMA for conversion of more than one regular channel. This avoids the loss of data
already stored in the ADC_DR register.
Only the end of conversion of a regular channel generates a DMA request, which allows the
transfer of its converted data from the ADC_DR register to the destination location selected
by the user.

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19.10 Dual ADC mode

In devices with two ADCs, dual ADC mode can be used (see Figure 173).
In dual ADC mode the start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 slave, depending on the mode selected by the DUALMOD[2:0]
bits in the ADC_CR1 register.
Note: In dual mode, when configuring conversion to be triggered by an external event, the user
must set the trigger for the master only and set a software trigger for the slave to prevent
spurious triggers to start unwanted slave conversion. However, external triggers must be
enabled on both master and slave ADCs.
The following six possible modes are implemented:
– Injected simultaneous mode
– Regular simultaneous mode
– Fast interleaved mode
– Slow interleaved mode
– Alternate trigger mode
– Independent mode
It is also possible to use the previous modes combined in the following ways:
– Injected simultaneous mode + Regular simultaneous mode
– Regular simultaneous mode + Alternate trigger mode
– Injected simultaneous mode + Interleaved mode
Note: In dual ADC mode, to read the slave converted data on the master data register, the DMA
bit must be enabled even if it is not used to transfer converted regular channel data.

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Figure 173. Dual ADC block diagram

REGULAR DATA REGISTER

(12
(16bits)
bits)

INJECTED DATA REGISTERS

(4 x 16 bits)

REGULAR
CHANNELS ADC2 (SLAVE)
INJECTED
CHANNELS

internal triggers

Address/data bus
REGULAR DATA REGISTER
(16 bits)*

INJECTED DATA REGISTERS

(4 x 16 bits)

ADC_IN0
REGULAR
ADC_IN1 CHANNELS
GPIO
Ports
INJECTED
CHANNELS
ADC_IN15

Temp. sensor
VREFINT DUAL MODE
CONTROL

EXTI_11 ADC1 (MASTER)

Start trigger mux
(regular group)

EXTI_15
Start trigger mux
(injected group)

Note: External triggers are present on ADC2 but are not shown for the purposes of this diagram
* In some dual ADC modes, the ADC1 data register (ADC1_DR) contains both ADC1 and ADC2 regular converted
data over the entire 32 bits.

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19.10.1 Injected simultaneous mode

This mode converts an injected channel group. The source of external trigger comes from
the injected group mux of ADC1 (selected by the JEXTSEL[2:0] bits in the ADC1_CR2
register). A simultaneous trigger is provided to ADC2.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
At the end of conversion event on ADC1 or ADC2:
● The converted data is stored in the ADC_JDRx registers of each ADC interface.
● An JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the
ADC1/ADC2 injected channels are all converted.

Figure 174. Injected simultaneous mode on 4 channels

Sampling
Conversion
ADC2 CH0 CH1 CH2 CH3
ADC1 CH3 CH2 CH1 CH0

Trigger End of injected conversion on ADC1 and ADC2

19.10.2 Regular simultaneous mode

This mode is performed on a regular channel group. The source of the external trigger
comes from the regular group mux of ADC1 (selected by the EXTSEL[2:0] bits in the
ADC1_CR2 register). A simultaneous trigger is provided to the ADC2.
Note: Do not convert the same channel on the two ADCs (no overlapping sampling times for the
two ADCs when converting the same channel).
At the end of conversion event on ADC1 or ADC2:
● A 32-bit DMA transfer request is generated (if DMA bit is set) which transfers to SRAM
the ADC1_DR 32-bit register containing the ADC2 converted data in the upper
halfword and the ADC1 converted data in the lower halfword.
● An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when
ADC1/ADC2 regular channels are all converted.

Figure 175. Regular simultaneous mode on 16 channels

Sampling
Conversion
ADC1 CH0 CH1 CH2 CH3 ... CH15
ADC2 CH15 CH14 CH13 CH12 ... CH0

Trigger End of conversion on ADC1 and ADC2

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19.10.3 Fast interleaved mode

This mode can be started only on a regular channel group (usually one channel). The
source of external trigger comes from the regular channel mux of ADC1. After an external
trigger occurs:
● ADC2 starts immediately and
● ADC1 starts after a delay of 7 ADC clock cycles.
If CONT bit is set on both ADC1 and ADC2 the selected regular channels of both ADCs are
continuously converted.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
Note: The maximum sampling time allowed is <7 ADCCLK cycles to avoid the overlap between
ADC1 and ADC2 sampling phases in the event that they convert the same channel.

Figure 176. Fast interleaved mode on 1 channel in continuous conversion mode

Sampling
End of conversion on ADC2
Conversion
ADC2 CH0 ... CH0
ADC1 CH0 ... CH0

Trigger
End of conversion on ADC1

7 ADCCLK
cycles

19.10.4 Slow interleaved mode

This mode can be started only on a regular channel group (only one channel). The source of
external trigger comes from regular channel mux of ADC1. After external trigger occurs:
● ADC2 starts immediately and
● ADC1 starts after a delay of 14 ADC clock cycles.
● ADC2 starts after a second delay of 14 ADC cycles, and so on.
Note: The maximum sampling time allowed is <14 ADCCLK cycles to avoid an overlap with the
next conversion.
After an EOC interrupt is generated by ADC1 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA bit is set) which transfers to SRAM the
ADC1_DR 32-bit register containing the ADC2 converted data in the upper halfword and the
ADC1 converted data in the lower halfword.
A new ADC2 start is automatically generated after 28 ADC clock cycles
CONT bit can not be set in the mode since it continuously converts the selected regular
channel.
Note: The application must ensure that no external trigger for injected channel occurs when
interleaved mode is enabled.

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Figure 177. Slow interleaved mode on 1 channel

End of conversion on ADC2 Sampling

Conversion
ADC2 CH0 CH0
ADC1 CH0 CH0

Trigger End of conversion on ADC1

14 ADCCLK
cycles

28 ADCCLK
cycles

19.10.5 Alternate trigger mode

This mode can be started only on an injected channel group. The source of external trigger
comes from the injected group mux of ADC1.
● When the 1st trigger occurs, all injected group channels in ADC1 are converted.
● When the 2nd trigger arrives, all injected group channels in ADC2 are converted
● and so on....
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are
converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are
converted.
If another external trigger occurs after all injected group channels have been converted then
the alternate trigger process restarts by converting ADC1 injected group channels.

Figure 178. Alternate trigger: injected channel group of each ADCl

1st trigger 3rd trigger (n)th trigger Sampling
EOC, JEOC EOC, JEOC
on ADC1 on ADC1 Conversion

ADC1 ...
ADC2

EOC, JEOC EOC, JEOC

on ADC2 on ADC2
2nd trigger 4th trigger (n+1)th trigger

If the injected discontinuous mode is enabled for both ADC1 and ADC2:
● When the 1st trigger occurs, the first injected channel in ADC1 is converted.
● When the 2nd trigger arrives, the first injected channel in ADC2 are converted
● and so on....
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC1 are
converted.
A JEOC interrupt, if enabled, is generated after all injected group channels of ADC2 are
converted.
If another external trigger occurs after all injected group channels have been converted then
the alternate trigger process restarts.

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Figure 179. Alternate trigger: 4 injected channels (each ADC) in discontinuous model
1st trigger 3rd trigger 5th trigger 7th trigger Sampling
JEOC on ADC1 Conversion

ADC1
ADC2

JEOC on ADC2

2nd trigger 4th trigger 6th trigger 8th trigger

19.10.6 Independent mode

In this mode the dual ADC synchronization is bypassed and each ADC interfaces works
independently.

19.10.7 Combined regular/injected simultaneous mode

It is possible to interrupt simultaneous conversion of a regular group to start simultaneous
conversion of an injected group.

19.10.8 Combined regular simultaneous + alternate trigger mode

It is possible to interrupt regular group simultaneous conversion to start alternate trigger
conversion of an injected group. Figure 180 shows the behavior of an alternate trigger
interrupting a regular simultaneous conversion.
The injected alternate conversion is immediately started after the injected event arrives. If
regular conversion is already running, in order to ensure synchronization after the injected
conversion, the regular conversion of both (master/slave) ADCs is stopped and resumed
synchronously at the end of the injected conversion.

Figure 180. Alternate + Regular simultaneous

1st trig

ADC1 reg CH0 CH1 CH2 CH2 CH3 CH3 CH4

ADC1 inj
CH0

ADC2 reg CH3 CH5 CH6 CH6 CH7 CH7 CH8

ADC2 inj CH0

synchro not lost

2nd trig

If a trigger occurs during an injected conversion that has interrupted a regular conversion, it
will be ignored. Figure 181 shows the behavior in this case (2nd trig is ignored).

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Figure 181. Case of trigger occurring during injected conversion

1st trig 3rd trig

ADC1 reg CH0 CH1 CH2 CH2 CH3 CH3 CH4

CH0 CH0
ADC1 inj

ADC2 reg CH3 CH5 CH6 CH6 CH7 CH7 CH8

CH0
ADC2 inj

2nd trig 4th trig

19.10.9 Combined injected simultaneous + interleaved

It is possible to interrupt an interleaved conversion with an injected event. In this case the
interleaved conversion is interrupted and the injected conversion starts, at the end of the
injected sequence the interleaved conversion is resumed. Figure 182 shows the behavior
using an example.

Figure 182. Interleaved single channel with injected sequence CH11, CH12
Sampling
ADC1 CH0 CH0 CH0 Conversion
ADC2 CH0 CH0 CH0

CH11 CH12
Trigger
CH12 CH11
CH0 CH0

CH0 CH0

19.11 Temperature sensor

The temperature sensor can be used to measure the ambient temperature (TA) of the
device.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value. The sampling time for
temperature sensor analog input must be greater than 2.2 µs.
The block diagram of the temperature sensor is shown in Figure 183.
When not in use, this sensor can be put in power down mode.
Note: The TSVREFE bit must be set to enable both internal channels: ADC_IN16 (temperature
sensor) and ADC_IN17 (VREFINT) conversion.

Main features
● Supported Temperature Range: -40 to 125 degrees
● Precision: +/- 1.5° C

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Figure 183. Temperature sensor and VREFINT channel block diagram

TSVREFE control bit

TEMPERATURE VSENSE
SENSOR ADC_IN16

Address/data bus
converted data

ADC

VREFINT
INTERNAL
ADC_IN17
POWER
BLOCK

Reading the temperature

To use the sensor:
4. Select the ADC_IN16 input channel.
5. Select a sample time greater than 2.2 µs
6. Set the TSVREFE bit in the ADC control register 2 (ADC_CR2) to wake-up the
temperature sensor from power down mode.
7. Start the ADC conversion by setting the ADON bit (or by external trigger).
8. Read the resulting VSENSE data in the ADC data register
9. Obtain the temperature using the following formula:
Temperature (in °C) = {(V25 - VSENSE) / Avg_Slope} + 25.
Where,
V25 = VSENSE value for 25° C and
Avg_Slope = Average Slope for curve between Temperature vs VSENSE (given in
mV/° C or µV/ °C).
Refer to the Electrical characteristics section for the actual values of V25 and
Avg_Slope.
Note: The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADON and TSVREFE bits should be set at the same time.

19.12 Interrupts
An interrupt can be produced on end of conversion for regular and injected groups and
when the Analog Watchdog status bit is set. Separate interrupt enable bits are available for
flexibility.

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Two other two flags are present in the ADC_SR register, but there is no interrupt associated
with them:
● JSTRT (Start of conversion for injected group channels)
● STRT (Start of conversion for regular group channels

Table 69. ADC interrupts

Interrupt Event Event Flag Enable Control Bit

End of Conversion regular group EOC EOCIE

End of Conversion injected group JEOC JEOCIE
Analog Watchdog Status bit is set AWD AWDIE

19.13 ADC register description

Refer to Section 1.1 on page 23 for a list of abbreviations used in register descriptions.

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19.13.1 ADC status register (ADC_SR)

Address Offset: 00h
Reset value: 00000000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved STRT JSTRT JEOC EOC AWD

rw rw rw rw rw

Bits 31:5 Reserved, must be kept cleared.

STRT: Regular channel Start flag
This bit is set by hardware when regular channel conversion starts. It is
Bit 4 cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
JSTRT: Injected channel Start flag
This bit is set by hardware when injected channel group conversion starts. It is
Bit 3 cleared by software.
0: No injected group conversion started
1: Injected group conversion has started
JEOC: Injected channel end of conversion
This bit is set by hardware at the end of all injected group channel conversion.
Bit 2 It is cleared by software.
0: Conversion is not complete
1: Conversion complete
EOC: End of conversion
This bit is set by hardware at the end of a group channel conversion (regular
Bit 1 or injected). It is cleared by software or by reading the ADC_DR.
0: Conversion is not complete
1: Conversion complete
AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values
programmed in the ADC_LTR and ADC_HTR registers. It is cleared by
Bit 0
software.
0: No Analog Watchdog event occurred
1: Analog Watchdog event occurred

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19.13.2 ADC control register 1 (ADC_CR1)

Address offset: 04h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

AWD AWD
Reserved Reserved DUALMOD[3:0]
EN ENJ

rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DISC DISC JAUT AWD JEOC

DISCNUM[2:0] SCAN AWDIE EOCIE AWDCH[4:0]
ENJ EN O SGL IE

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept cleared.

AWDEN: Analog watchdog enable on regular channels
This bit is set/reset by software.
Bit 23
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
JAWDEN: Analog watchdog enable on injected channels
This bit is set/reset by software.
Bit 22
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:20 Reserved, must be kept cleared.
DUALMOD[3:0]: Dual mode selection
These bits are written by software to select the operating mode.
0000: Independent mode.
0001: Combined regular simultaneous + injected simultaneous mode
0010: Combined regular simultaneous + alternate trigger mode
0011: Combined injected simultaneous + fast interleaved mode
0100: Combined injected simultaneous + slow Interleaved mode
0101: Injected simultaneous mode only
Bits 19:16 0110: Regular simultaneous mode only
0111: Fast interleaved mode only
1000: Slow interleaved mode only
1001: Alternate trigger mode only
Notes:
–These bits are reserved in ADC2.
–In dual mode, a change of channel configuration generates a restart that can
produce a loss of synchronization. It is recommended to disable dual mode
before any configuration change.

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DISCNUM[2:0]: Discontinuous mode channel count

These bits are written by software to define the number of regular channels to
be converted in discontinuous mode, after receiving an external trigger.
Bits 15:13 000: 1 channel
001: 2 channels
.......
111: 8 channels
JDISCEN: Discontinuous mode on injected channels
This bit set and cleared by software to enable/disable discontinuous mode on
Bit 12 injected group channels
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
DISCEN: Discontinuous mode on regular channels
This bit set and cleared by software to enable/disable Discontinuous mode on
Bit 11 regular channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
JAUTO: Automatic Injected Group conversion
This bit set and cleared by software to enable/disable automatic injected group
Bit 10 conversion after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
AWDSGL: Enable the watchdog on a single channel in scan mode
This bit set and cleared by software to enable/disable the analog watchdog on
Bit 9 the channel identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
SCAN: Scan mode
This bit is set and cleared by software to enable/disable Scan mode. In Scan
mode, the inputs selected through the ADC_SQRx or ADC_JSQRx registers
are converted.
Bit 8
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC or JEOC interrupt is generated only on the end of conversion of
the last channel if the corresponding EOCIE or JEOCIE bit is set
JEOCIE: Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion
Bit 7 interrupt for injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
AWDIE: Analog Watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog
interrupt. In Scan mode if the watchdog thresholds are crossed, scan is
Bit 6
aborted only if this bit is enabled.
0: Analog Watchdog interrupt disabled
1: Analog Watchdog interrupt enabled

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EOCIE: Interrupt enable for EOC

This bit is set and cleared by software to enable/disable the End of Conversion
Bit 5 interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to
be guarded by the Analog Watchdog.
00000: Channel ADC_IN0
00001: Channel ADC_IN1
Bits 4:0
....
01111: Channel ADC_IN15
10000: Channel ADC_IN16 Temperature sensor
10001: Channel ADC_IN17 VREFINT
Other values reserved.

19.13.3 ADC control register 2 (ADC_CR2)

Address offset: 08h
Reset value: 0000 0000h

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

TS SW SW EXT
Reserved EXTSEL[2:0] Res.
VREFE START STARTJ TRIG

rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JEXTT RST
JEXTSEL[2:0] ALIGN Reserved DMA Reserved CAL CONT ADON
RIG CAL

rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept cleared.

TSVREFE: Temperature Sensor and VREFINT Enable
This bit is set and cleared by software to enable/disable the temperature
sensor and VREFINT channel. In devices with dual ADCs this bit is present only
Bit 23
in ADC1.
0: Temperature sensor and VREFINT channel disabled
1: Temperature sensor and VREFINT channel enabled
SWSTART: Start Conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon
as conversion starts. It starts a conversion of a a group of regular channels if
Bit 22
SWSTART is selected as trigger event by the EXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of regular channels

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JSWSTART: Start Conversion of injected channels

This bit is set by software and cleared by software or by hardware as soon as
the conversion starts. It starts a conversion of a a group of injected channels
Bit 21
(if JSWSTART is selected as trigger event by the JEXTSEL[2:0] bits.
0: Reset state
1: Starts conversion of injected channels
EXTTRIG: External Trigger Conversion mode for regular channels
This bit is set and cleared by software to enable/disable the external trigger
Bit 20 used to start conversion of a regular channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
EXTSEL[2:0]: External Event Select for regular group
These bits select the external event used to trigger the start of conversion of a
regular group:
000: Timer 1 CC1 event
001: Timer 1 CC2 event
Bits 19:17 010: Timer 1 CC3 event
011: Timer 2 CC2 event
100: Timer 3 TRGO event
101: Timer 4 CC4 event
110: External interrupt 11
111: SWSTART
Bit 16 Reserved, must be kept cleared.
JEXTTRIG: External Trigger Conversion mode for injected channels
This bit is set and cleared by software to enable/disable the external trigger
Bit 15 used to start conversion of an injected channel group.
0: Conversion on external event disabled
1: Conversion on external event enabled
JEXTSEL[2:0]: External event select for injected group
These bits select the external event used to trigger the start of conversion of
an injected group:
000: Timer 1 TRGO event
001: Timer 1 CC4 event
Bits 14:12 010: Timer 2 TRGO event
011: Timer 2 CC1 event
100: Timer 3 CC4 event
101: Timer 4 TRGO event
110: External interrupt 15
111: JSWSTART
ALIGN: Data Alignment
This bit is set and cleared by software. Refer to Figure 171.and Figure 172.
Bit 11
0: Right Alignment
1: Left Alignment
Bits 10:9 Reserved, must be kept cleared.

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DMA: Direct Memory access mode

This bit is set and cleared by software. Refer to the DMA controller chapter for
more details.
Bit 8 0: DMA mode disabled
1: DMA mode enabled
Note: In devices with more that one ADC, only ADC1 can generate a DMA
request.
Bits 7:4 Reserved, must be kept cleared.
RSTCAL: Reset Calibration
This bit is reset by software and cleared by hardware. It sets the calibration
registers in the Analog ADC block and the CAL signal to the ADC. This bit will
be cleared after the calibration registers are cleared.
Bit 3
0: Calibration register initialized.
1: Initialize calibration register.
Note: If RSTCAL is reset when conversion is ongoing extra cycles are required
for clearing the calibration register
CAL: A/D Calibration
This bit is set by software to start the calibration. It is reset by hardware after
Bit 2 calibration is complete.
0: Calibration completed
1: Enable calibration
CONT: Continuous Conversion
This bit is set and cleared by software. If set conversion takes place
Bit 1 continuously till this bit is reset.
0: Single conversion mode
1: Continuous conversion mode
ADON: A/D Converter ON / OFF
This bit is set and cleared by software. If this bit holds a value of zero and a 1
is written to it then it wakes up the ADC from Power Down state.
Conversion starts when this bit holds a value of 1 and a 1 is written to it. The
application should allow a delay of tSTAB between power up and start of
Bit 0 conversion. Refer to Figure 167.
0: Disable ADC conversion/calibration and go to power down mode.
1: Enable ADC and to start conversion
Note: If any other bit in this register apart from ADON is changed at the same
time, then conversion is not triggered. This is to prevent triggering an erroneous
conversion.

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19.13.4 ADC sample time register 1 (ADC_SMPR1)

Address offset: 0Ch
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SMP18[2:0] SMP17[2:0] SMP16[2:0] SMP15[2:1]

rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SMP
SMP14[2:0] SMP13[2:0] SMP12[2:0] SMP11[2:0] SMP10[2:0]
15_0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:27 Reserved, must be kept cleared.

SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for
each channel. During sample cycles channel selection bits must remain
unchanged.
000: 1.5 cycles
001: 7.5 cycles
Bits 26:0
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles

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19.13.5 ADC sample time register 2 (ADC_SMPR2)

Address offset: 10h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SMP9[2:0] SMP8[2:0] SMP7[2:0] SMP6[2:0] SMP5[2:1]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SMP
SMP4[2:0] SMP3[2:0] SMP2[2:0] SMP1[2:0] SMP0[2:0]
5_0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept cleared.

SMPx[2:0]: Channel x Sample time selection
These bits are written by software to select the sample time individually for
each channel. During sample cycles channel selection bits must remain
unchanged.
000: 1.5 cycles
001: 7.5 cycles
Bits 29:0
010: 13.5 cycles
011: 28.5 cycles
100: 41.5 cycles
101: 55.5 cycles
110: 71.5 cycles
111: 239.5 cycles

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19.13.6 ADC injected channel data offset register x (ADC_JOFRx)(x=1..4)

Address offset: 14-20h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved JOFFSETx[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept cleared.

JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from
Bits 11:0
the raw converted data when converting injected channels. The conversion
result can be read from in the ADC_JDRx registers.

19.13.7 ADC watchdog high threshold register (ADC_HTR)

Address offset: 24h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved HT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept cleared.

HT[11:0] Analog watchdog high threshold
Bits 11:0 These bits are written by software to define the high threshold for the Analog
Watchdog.

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19.13.8 ADC watchdog low threshold register (ADC_LTR)

Address offset: 28h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved LT[11:0]

rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:12 Reserved, must be kept cleared.

LT[11:0] Analog watchdog low threshold
Bits 11:0 These bits are written by software to define the low threshold for the Analog
Watchdog.

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19.13.9 ADC regular sequence register 1 (ADC_SQR1)

Address offset: 2Ch
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved L[3:0] SQ16[4:1]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SQ16_
SQ15[4:0] SQ14[4:0] SQ13[4:0]
0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:24 Reserved, must be kept cleared.

L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in
the regular channel conversion sequence.
Bits 23:20 0000: 1 conversion
0001: 2 conversions
.....
1111: 16 conversions
SQ16[4:0]: 16th conversion in regular sequence
Bits 19:15 These bits are written by software with the channel number (0..17) assigned
as the 16th in the conversion sequence.
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence

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19.13.10 ADC regular sequence register 2 (ADC_SQR2)

Address offset: 30h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SQ12[4:0] SQ11[4:0] SQ10[4:1]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SQ10_
SQ9[4:0] SQ8[4:0] SQ7[4:0]
0

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept cleared.

SQ12[4:0]: 12th conversion in regular sequence
Bits 29:26 These bits are written by software with the channel number (0..17) assigned as
the 12th in the sequence to be converted.
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence

19.13.11 ADC regular sequence register 3 (ADC_SQR3)

Address offset: 34h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved SQ6[4:0] SQ5[4:0] SQ4[4:1]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SQ4_0 SQ3[4:0] SQ2[4:0] SQ1[4:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:30 Reserved, must be kept cleared.

SQ6[4:0]: 6th conversion in regular sequence
Bits 29:25 These bits are written by software with the channel number (0..17) assigned
as the 6th in the sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence

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Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence

Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence

19.13.12 ADC injected sequence register (ADC_JSQR)

Address offset: 38h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved JL[1:0] JSQ4[4:1]

rw rw rw rw rw rw

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JSQ4_0

JSQ3[4:0] JSQ2[4:0] JSQ1[4:0]

rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw

Bits 31:22 Reserved, must be kept cleared.

JL[1:0]: Injected Sequence length
These bits are written by software to define the total number of conversions in
the injected channel conversion sequence.
Bits 21:20 00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
JSQ4[4:0]: 4th conversion in injected sequence
These bits are written by software with the channel number (0..17) assigned
as the 4th in the sequence to be converted.
Bits 19:15 Note: Unlike a regular conversion sequence, if JL[1:0] length is less than four,
the channels are converted in a sequence starting from (4-JL). Example:
ADC_JSQR[21:0] = 10 00011 00011 00111 00010 means that a scan
conversion will convert the following channel sequence: 7, 3, 3. (not 2, 7, 3)
Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence
Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence
Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence

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19.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)

Address offset: 3C - 48h
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

JDATA[15:0]

r r r r r r r r r r r r r r r r

Bits 31:16 Reserved, must be kept cleared.

JDATA[15:0]: Injected data
These bits are read only. They contain the conversion result from injected
Bits 15:0
channel x. The data is left or right-aligned as shown in Figure 171 and
Figure 172.

19.13.14 ADC regular data register (ADC_DR)

Address offset: 4Ch
Reset value: 0000 0000h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ADC2DATA[15:0]

r r r r r r r r r r r r r r r r

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DATA[15:0]

r r r r r r r r r r r r r r r r

ADC2DATA[15:0]: ADC2 data

– In ADC1: In dual mode, these bits contain the regular data of ADC2. Refer to
Bits 31:16
Section 19.10: Dual ADC mode
– In ADC2: these bits are not used
DATA[15:0]: Regular data
These bits are read only. They contain the conversion result from the regular
Bits 15:0
channels. The data is left or right-aligned as shown in Figure 171 and
Figure 172.

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19.14 ADC register map

The following table summarizes the ADC registers.

Table 70. ADC - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
JSTRT
JEOC
STRT

AWD
EOC
ADC_SR
00h Reserved
Reset Value 0 0 0 0 0

AWD SGL
JDISCEN
JAWDEN

JEOC IE
DISCEN
AWDEN

AWDIE
JAUTO

EOCIE
Reserved

SCAN
DUALMOD DISC
ADC_CR1 AWDCH[4:0]
04h Reserved [3:0] NUM [2:0]

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

JSWSTART

JEXTTRIG
SWSTART
TSVREFE

EXTTRIG

RSTCAL
ALIGN
Reserved

Reserved

ADON
CONT
EXTSEL JEXTSEL

DMA

CAL
ADC_CR2
08h Reserved [2:0] [2:0] Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_SMPR1 Sample time bits SMPx_x

0Ch
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_SMPR2 Sample time bits SMPx_x

10h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JOFR1 JOFFSET1[11:0]
14h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JOFR2 JOFFSET2[11:0]
18h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JOFR3 JOFFSET3[11:0]
1Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JOFR4 JOFFSET4[11:0]
20h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

ADC_HTR HT[11:0]
24h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

ADC_LTR LT[11:0]
28h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0

ADC_SQR1 L[3:0] Regular channel sequence SQx_x bits

2Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reserved Reserved

ADC_SQR2 Regular channel sequence SQx_x bits

30h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_SQR3 Regular channel sequence SQx_x bits

34h
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JSQR JL[1:0] Injected channel sequence JSQx_x bits

38h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 70. ADC - register map and reset values (continued)

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Offset Register

9
8
7
6
5
4
3
2
1
0
ADC_JDR1 JDATA[15:0]
3Ch Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JDR2 JDATA[15:0]
40h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JDR3 JDATA[15:0]
44h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_JDR4 JDATA[15:0]
48h Reserved
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ADC_DR ADC2DATA[15:0] Regular DATA[15:0]

4Ch
Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Refer to Table 1 on page 27 for the register boundary addresses.

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20 Debug support (DBG)

20.1 Overview
The STM32F10x is built around a Cortex-M3 core which contains hardware extensions for
advanced debugging features. The debug extensions allow the core to be stopped either on
a given instruction fetch (breakpoint) or data access (watchpoint). When stopped, the core’s
internal state and the system’s external state may be examined. Once examination is
complete, the core and the system may be restored and program execution resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32F10x MCU.
Two interfaces for debug are available:
● Serial wire
● JTAG debug port

Figure 184. Block diagram of STM32F10x-level and Cortex-M3-level debug support

STM32F10x debug support
Cortex-M3 debug support
Bus Matrix
DCode
interface

Cortex-M3 Data
System
Core interface

JTMS/
SWDIO External Private
TRACESWO
Peripheral Bus (PPB)
JTDI Trace Port
Bridge TPIU TRACECK
JTDO/
TRACESWO SWJ-DP AHB-AP
TRACED[3:0]
JNTRST Internal Private NVIC
Peripheral Bus (PPB)
JTCK/
SWCLK
DWT DBGMCU

FPB

ITM

Note: The debug features embedded in the Cortex-M3 core are a subset of the ARM CoreSight
Design Kit.

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The ARM Cortex-M3 core provides integrated on-chip debug support. It is comprised of:
● SWJ-DP: Serial wire / JTAG debug port
● AHP-AP: AHB access port
● ITM: Instrumentation trace macrocell
● FPB: Flash patch breakpoint
● DWT: Data watchpoint trigger
● TPUI: Trace port unit interface (available on larger packages, where the corresponding
pins are mapped)
It also includes debug features dedicated to STM32F10x:
● Flexible debug pinout assignment
● MCU debug box (support for low-power modes, control over peripheral clocks, etc.)
Note: For further information on debug functionality supported by the ARM Cortex-M3 core, refer
to the Cortex-M3 r1p1 Technical Reference Manual (TRM) and to the CoreSight Design Kit
r1p0 TRM.

20.2 Referenced ARM documentation

● Cortex-M3 r1p1 Technical Reference Manual (TRM)
● ARM Debug Interface V5
● ARM CoreSight Design Kit revision r1p0 Technical Reference Manual

20.3 SWJ debug port (serial wire and JTAG)

The STM32F10x core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM
standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-
pin) interface.
● The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port.
● The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.

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In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
TRACESWO (asynchronous trace)

SWJ-DP
JTDO TDO
TDO
TDI
JTDI TDI
nTRST
JNTRST nTRST
JTAG-DP

TCK

TMS
nPOTRST
From
SWD/JTAG power-on
select nPOTRST reset
DBGRESETn
SWDITMS
DBGDI
JTMS/SWDIO
SWDO
DBGDO
SW-DP
SWDOEN
DBGDOEN

SWCLKTCK
JTCK/SWCLK DBGCLK

The figure above shows that the asynchronous TRACE output (TRACESWO) is multiplexed
with TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-
DP.

20.3.1 Mechanism to select the JTAG-DP or the SW-DP

By default, the JTAG-Debug Port is active.
If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG
sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the
JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only
the SWCLK and SWDIO pins.
This sequence is:
1. Send more than 50 TCK cycles with TMS (SWDIO) =1
2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted
first)
3. Send more than 50 TCK cycles with TMS (SWDIO) =1

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20.4 Pinout and debug port pins

The STM32F10x MCU is available in various packages with different numbers of available
pins. As a result, some functionality related to pin availability may differ between packages.

20.4.1 SWJ debug port pins

Five pins are used as outputs from the STM32F10x for the SWJ-DP as alternate functions of
General Purpose I/Os. These pins are available on all packages.
JTAG Debug Port SW Debug Port Pin
SWJ-DP pin name assign-
Type Description Type Debug Assignment ment

JTAG Test Mode Serial Wire Data

JTMS/SWDIO I I/O PA13
Selection Input/Output
JTCK/SWCLK I JTAG Test Clock I Serial Wire Clock PA14
JTDI I JTAG Test Data Input - - PA15
TRACESWO if async trace
JTDO/TRACESWO O JTAG Test Data Output - PB3
is enabled
JNTRST I JTAG Test nReset - - PB4

20.4.2 Flexible SWJ-DP pin assignment

After RESET (SYSRESETn or PORESETn), all five pins used for the SWJ-DP are assigned
as dedicated pins immediately usable by the debugger host (note that the trace outputs are
not assigned except if explicitly programmed by the debugger host).
However, the STM32F10x MCU implements the REMAP_DBGAFR register to disable some
part or all of the SWJ-DP port and so releases the associated pins for General Purpose I/Os
usage. This register is mapped on an APB bridge connected to the Cortex-M3 System Bus.
Programming of this register is done by the user software program and not the debugger
host.
Three control bits allow the configuration of the SWJ-DP pin assignments. These bits are
reset by the System Reset.
● REMAP_AF_REG (@0x40010004 in STM32F10x MCU)
– READ: APB - No Wait State
– WRITE: APB - 1 Wait State if the write buffer of the AHB-APB bridge is full.
Bit 26:24= SWJ_CFG[2:0]
Set and cleared by software.
These bits are used to configure the number of pins assigned to the SWJ debug port.
The goal is to release as much as possible the number of pins to be used as General
Purpose I/Os if using a small size for the debug port.
The default state after reset is “000” (whole pins assigned for a full JTAG-DP
connection). Only one of the 3 bits can be set (it is forbidden to set more than one bit).

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SWJ I/O pin assigned

SWJ
_ PA14 /
Available DEBUG ports PA13 / PB4/
CFG JTCK/ PA15 / PB3 /
JTMS/ JNTRS
[2:0] SWCL JTDI JTDO
SWDIO T
K

Full SWJ (JTAG-DP + SW-DP) - Reset

000 X X X X X
State
Full SWJ (JTAG-DP + SW-DP) but without
001 X X X X
JNTRST
010 JTAG-DP Disabled and SW-DP Enabled X X
100 JTAG-DP Disabled and SW-DP Disabled Released
other Forbidden

Note: When the APB bridge write buffer is full, it takes one extra APB cycle when writing the
REMAP_AF register. This is because the deactivation of the JTAGSW pins is done in two
cycles to guarantee a clean level on the nTRST and TCK input signals of the core.
● Cycle 1: the JTAGSW input signals to the core are tied to 1 or 0 (to 1 for nTRST, TDI
and TMS, to 0 for TCK)
● Cycle 2: the GPI/O controller takes the control signals of the SWJTAG I/O pins (like
controls of direction, pull-up/down, Schmitt trigger activation, etc.).

20.4.3 Internal pull-up and pull-down on JTAG pins

It is necessary to ensure that the JTAG input pins are not floating since they are directly
connected to flip-flops to control the debug mode features. Special care must be taken with
the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled I/O levels, the STM32F10x embeds internal pull-ups and pull-
downs on JTAG input pins:
● JNTRST: Internal pull-up
● JTDI: Internal pull-up
● JTMS/SWDIO: Internal pull-up
● TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
● JNTRST: Input pull-up
● JTDI: Input pull-up
● JTMS/SWDIO: Input pull-up
● JTCK/SWCLK: Input pull-down
● JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is
no special recommendation for TCK. However, for STM32F10x, an integrated pull-down is
used for JTCK.
Having embedded pull-ups and pull-downs removes the need to add external resistors.

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20.4.4 Using serial wire and releasing the unused debug pins as GPIOs
To use the serial wire DP to release some GPIOs, the user software must set
SWJ_CFG=010 just after reset. This release PA15, PB3 and PB4 which now become
available as GPIOs.
When debugging, the host performs the following actions:
● Under system RESET, all SWJ pins are assigned (JTAG-DP + SW-DP)
● Under system RESET, the debugger host sends the JTAG sequence to switch from the
JTAG-DP to the SW-DP.
● Still under system RESET, the debugger sets a breakpoint on vector reset
● The System Reset is released and the Core halts.
● All the debug communications from this point are done using the SW-DP. The other
JTAG pins can then be reassigned as GPIOs by the user software.
Note: For user software designs, note that:
To release the debug pins, remember that they will be first configured either in input-pull-up
(nTRST, TMS, TDI) or pull-down (TCK) or output tristate (TDO) for a certain duration after
reset until the instant when the user software releases the pins.
When debug pins (JTAG or SW or TRACE) are mapped, changing the corresponding I/O pin
configuration in the IOPORT controller has no effect.

20.5 STM32F10x JTAG TAP connection

The STM32F10x MCU integrates two serially-connected JTAG TAPs, the TMC TAP
dedicated for Test (IR is 5-bit wide) and the Cortex-M3 TAP (IR is 4-bits wide).
To access the TAP of the Cortex-M3 for debug purposes:
1. First, it is necessary to shift the BYPASS instruction of the TMC TAP.
2. Then, for each IR shift, the scan chain contains 9 bits (=5+4) and the unused TAP
instruction must be shifted in using the BYPASS instruction.
3. For each data shift, the unused TAP, which is in BYPASS mode, adds 1 extra data bit in
the data scan chain.
Note: Important: Once Serial-Wire is selected using the dedicated ARM JTAG sequence, the
TMC TAP is automatically disabled (JTMS forced high).

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Figure 185. JTAG TAP connections

STM32F10x

JNTRST
JTMS
SW-DP
Selected

TMS nTRST TMS nTRST

JTDI TDI TDO TDI TDO

TMC TAP Cortex-M3 TAP

IR is 5-bits wide IR is 4-bits wide
JTDO

20.6 ID codes and locking mechanism

There are several ID codes inside the STM32F10x MCU. ST strongly recommends tools
designers to lock their debuggers using the MCU DEVICE ID code located in the external
PPB memory map at address 0xE0042000.

20.6.1 MCU device ID code

The MCU STM32F10x integrates an MCU ID code. This ID identifies the ST MCU part-
number and the die revision. It is part of the DBG_MCU Component and is mapped on the
external PPB bus (see Section 20.15 on page 503). This code is accessible using the JTAG
debug port (4 to 5 pins) or the SW debug port (two pins) or by the user software. It is even
accessible while the MCU is under system reset.

DBGMCU_IDCODE
Address: 0xE0042000
Only 32-bits access supported
Read only = 0xXXXXX410 where X is undefined

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved DEV_ID

r r r r r r r r r r r r

Bits 31:12 Reserved

DEV_ID(11:0): Device Identifier
Bits 11:0
This field indicates the device. For STM32F10x MCU, the device ID is 0x410.

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20.6.2 TMC TAP

JTAG ID code
The TAP of the STM32F10x TMC (Test Mode Controller) integrates a JTAG ID code which is
equal to 0x06410041.

20.6.3 Cortex-M3 TAP

The TAP of the ARM Cortex-M3 integrates a JTAG ID code. This ID code is the ARM default
one and has not been modified. This code is only accessible by the JTAG Debug Port.
This code is 0x3BA00477 (corresponds to Cortex-M3 r1p1)
Only the DEV_ID(15:0) should be used for identification by the debugger/programmer tools.

20.6.4 Cortex-M3 JEDEC-106 ID Code

The ARM Cortex-M3 integrates a JEDEC-106 ID code. It is located in the 4KB ROM table
mapped on the internal PPB bus at address 0xE00FF000_0xE00FFFFF.

20.7 This code is accessible by the JTAG Debug Port (4 to 5 pins) or by the SW Debug Port (two
pins) or by the user software.JTAG debug port
A standard JTAG state machine is implemented with a 4-bit Instruction Register (IR) and five
Data Registers (for full details, refer to the Cortex-M3 r1p1 Technical Reference Manual
(TRM):

Table 71. JTAG debug port data registers

IR(3:0) Data register Details

BYPASS
1111
[1 bit]
IDCODE ID CODE
1110
[32 bits] 0x3BA00477 (ARM Cortex-M3 r1p1 ID Code)
Debug Port Access Register
This initiates a debug port and allows access to a debug port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to transfer for a write request
Bits 2:1 = A[3:2] = 2-bit address of a debug port register.
Bit 0 = RnW = Read request (1) or write request (0).
DPACC – When transferring data OUT:
1010
[35 bits] Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
request
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
Refer to Table 72 for a description of the A(3:2) bits

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Table 71. JTAG debug port data registers

IR(3:0) Data register Details

Access Port Access Register

Initiates an access port and allows access to an access port register.
– When transferring data IN:
Bits 34:3 = DATA[31:0] = 32-bit data to shift in for a write request
Bits 2:1 = A[3:2] = 2-bit address (sub-address AP registers).
Bit 0 = RnW= Read request (1) or write request (0).
– When transferring data OUT:
APACC Bits 34:3 = DATA[31:0] = 32-bit data which is read following a read
1011 request
[35 bits]
Bits 2:0 = ACK[2:0] = 3-bit Acknowledge:
010 = OK/FAULT
001 = WAIT
OTHER = reserved
There are many AP Registers (see AHB-AP) addressed as the
combination of:
– The shifted value A[3:2]
– The current value of the DP SELECT register
Abort Register
ABORT
1000 – Bits 31:1 = Reserved
[35 bits]
– Bit 0 = DAPABORT: write 1 to generate a DAP abort.

Table 72. 32-bit debug port registers addressed through the shifted value A[3:2]
Address A(3:2) value Description

0x0 00 Reserved
DP CTRL/STAT register. Used to:
– Request a system or debug power-up
0x4 01 – Configure the transfer operation for AP accesses
– Control the pushed compare and pushed verify operations.
– Read some status flags (overrun, power-up acknowledges)
DP SELECT register: Used to select the current access port and the
active 4-words register window.
– Bits 31:24: APSEL: select the current AP
0x8 10 – Bits 23:8: reserved
– Bits 7:4: APBANKSEL: select the active 4-words register window on the
current AP
– Bits 3:0: reserved
DP RDBUFF register: Used to allow the debugger to get the final result
0xC 11 after a sequence of operations (without requesting new JTAG-DP
operation)

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20.8 SW debug port

20.8.1 SW protocol introduction

This synchronous serial protocol uses two pins:
● SWCLK: clock from host to target
● SWDIO: bidirectional
The protocol allows two banks of registers (DPACC registers and APACC registers) to be
read and written to.
Bits are transferred LSB-first on the wire.
For SWDIO bidirectional management, the line must be pulled-up on the board (100 KΩ
recommended by ARM).
Each time the direction of SWDIO changes in the protocol, a turnaround time is inserted
where the line is not driven by the host nor the target. By default, this turnaround time is one
bit time, however this can be adjusted by configuring the SWCLK frequency.

20.8.2 SW protocol sequence

Each sequence consist of three phases:
1. Packet request (8 bits) transmitted by the host
2. Acknowledge response (3 bits) transmitted by the target
3. Data transfer phase (33 bits) transmitted by the host or the target

Table 73. Packet request (8-bits)

Bit Name Description

0 Start Must be “1”

0: DP Access
1 APnDP
1: AP Access
0: Write Request
2 RnW
1: Read Request
4:3 A(3:2) Address field of the DP or AP registers (refer to Table 72)
5 Parity Single bit parity of preceding bits
6 Stop 0
Not driven by the host. Must be read as “1” by the target
7 Park
because of the pull-up

Refer to the Cortex-M3 r1p1 TRM for a detailed description of DPACC and APACC registers.
The packet request is always followed by the turnaround time (default 1 bit) where neither
the host nor target drive the line.

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Table 74. ACK response (3 bits)

Bit Name Description

001: FAULT
0..2 ACK 010: WAIT
100: OK

The ACK Response must be followed by a turnaround time only if it is a READ transaction or
if a WAIT or FAULT acknowledge has been received.

Table 75. DATA transfer (33 bits)

Bit Name Description

WDATA or
0..31 Write or Read data
RDATA
32 Parity Single parity of the 32 data bits

The DATA transfer must be followed by a turnaround time only if it is a READ transaction.

20.8.3 SW-DP state machine (Reset, idle states, ID code)

The State Machine of the SW-DP has an internal ID code which identifies the SW-DP. It
follows the JEP-106 standard. This ID code is the default ARM one and is set at
0x1BA01477 (corresponding to Cortex-M3 r1p1).
Note: Note that the SW-DP state machine is inactive until the target reads this ID code.
● The SW-DP state machine is in RESET STATE either after power-on reset, or after the
DP has switched from JTAG to SWD or after the line is high for more than 50 cycles
● The SW-DP state machine is in IDLE STATE if the line is low for at least two cycles after
RESET state.
● After RESET state, it is mandatory to first enter into an IDLE state AND to perform a
READ access of the DP-SW ID CODE register. Otherwise, the target will issue a
FAULT acknowledge response on another transactions.
Further details of the SW-DP state machine can be found in the Cortex-M3 r1p1 TRM and
the CoreSight Design Kit r1p0 TRM.

20.8.4 DP and AP read/write accesses

● Read accesses to the DP are not posted: the target response can be immediate (if
ACK=OK) or can be delayed (if ACK=WAIT).
● Read accesses to the AP are posted. This means that the result of the access is
returned on the next transfer. If the next access to be done is NOT an AP access, then
the DP-RDBUFF register must be read to obtain the result.
The READOK flag of the DP-CTRL/STAT register is updated on every AP read access
or RDBUFF read request to know if the AP read access was successful.
● The SW-DP implements a write buffer (for both DP or AP writes), that enables it to
accept a write operation even when other transactions are still outstanding. If the write
buffer is full, the target acknowledge response is “WAIT”. With the exception of

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IDCODE read or CTRL/STAT read or ABORT write which are accepted even if the write
buffer is full.
● Because of the asynchronous clock domains SWCLK and HCLK, two extra SWCLK
cycles are needed after a write transaction (after the parity bit) to make the write
effective internally. These cycles should be applied while driving the line low (IDLE
state)
This is particularly important when writing the CTRL/STAT for a power-up request. If the
next transaction (requiring a power-up) occurs immediately, it will fail.

20.8.5 SW-DP registers

Access to these registers are initiated when APnDP=0

Table 76. SW-DP registers

CTRLSEL
bit of
A(3:2) R/W Register Notes
SELECT
register

The manufacturer code is not set to ST

00 Read IDCODE
code. 0x1BA01477 (identifies the SW-DP)
00 Write ABORT
Purpose is to:
– request a system or debug power-up
– configure the transfer operation for AP
accesses
01 Read/Write 0 DP-CTRL/STAT
– control the pushed compare and pushed
verify operations.
– read some status flags (overrun, power-up
acknowledges)
Purpose is to configure the physical serial
01 Read/Write 1 WIRE CONTROL port protocol (like the duration of the
turnaround time)
Enables recovery of the read data from a
10 Read READ RESEND corrupted debugger transfer, without
repeating the original AP transfer.
The purpose is to select the current access
10 Write SELECT
port and the active 4-words register window
This read buffer is useful because AP
accesses are posted (the result of a read AP
request is available on the next AP
11 Read/Write READ BUFFER transaction),
This read buffer captures data from the AP,
presented as the result of a previous read,
without initiating a new transaction

20.8.6 SW-AP registers

Access to these registers are initiated when APnDP=1

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There are many AP Registers (see AHB-AP) addressed as the combination of:
● The shifted value A[3:2]
● The current value of the DP SELECT register

20.9 AHB-AP (AHB Access Port) - valid for both JTAG-DP or SW-
DP
Features:
● System access is independent of the processor status.
● Either SW-DP or JTAG-DP accesses AHB-AP.
● The AHB-AP is an AHB master into the Bus Matrix. Consequently, it can access all the
data buses (Dcode Bus, System Bus, internal and external PPB bus) but the ICode
bus.
● Bitband transactions are supported.
● AHB-AP transactions bypass the FPB.
The address of the 32-bits AHP-AP resisters are 6-bits wide (up to 64 words or 256 bytes)
and consists of:
a) Bits [8:4] = the bits[7:4] APBANKSEL of the DP SELECT register
b) Bits [3:2] = the 2 address bits of A(3:2) of the 35-bit packet request for SW-DP.
The AHB-AP of the Cortex-M3 includes 9 x 32-bits registers:
Address
Register Name Notes
offset

Configures and controls transfers through the AHB

AHB-AP Control and
0x00 interface (size, hprot, status on current transfer, address
Status Word
increment type
0x04 AHB-AP Transfer Address
0x0C AHB-AP Data Read/Write
0x10 AHB-AP Banked Data 0
0x14 AHB-AP Banked Data 1 Directly maps the 4 aligned data words without rewriting
0x18 AHB-AP Banked Data 2 the Transfer Address Register.

0x1C AHB-AP Banked Data 3

0xF8 AHB-AP Debug ROM Address Base Address of the debug interface
0xFC AHB-AP ID Register

Refer to the Cortex-M3 r1p1 TRM for further details.

20.10 Core debug

Core debug is accessed through the core debug registers. Debug access to these registers
is by means of the Advanced High-performance Bus (AHB-AP) port. The processor can
access these registers directly over the internal Private Peripheral Bus (PPB).

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It consists of 4 registers:

Register Description

The 32-bit Debug Halting Control and Status Register

DHCSR This provides status information about the state of the processor enable core debug
halt and step the processor
The 17-bit Debug Core Register Selector Register:
DCRSR
This selects the processor register to transfer data to or from.
The 32-bit Debug Core Register Data Register:
DCRDR This holds data for reading and writing registers to and from the processor selected
by the DCRSR (Selector) register.
The 32-bit Debug Exception and Monitor Control Register:
DEMCR This provides Vector Catching and Debug Monitor Control. This register contains a
bit named TRCENA which enable the use of a TRACE.

Note: Important: these registers are not reset by a system reset. They are only reset by a power-
on reset.
Refer to the Cortex-M3 r1p1 TRM for further details.
To Halt on reset, it is necessary to:
● enable the bit0 (VC_CORRESET) of the Debug and Exception Monitor Control
Register
● enable the bit0 (C_DEBUGEN) of the Debug Halting Control and Status Register.

20.11 Capability of the debugger host to connect under system

reset
The STM32F10x MCU reset system comprises the following reset sources:
● POR (Power On Reset) which asserts a RESET at each power-up.
● Internal Watchdog Reset
● Software Reset
● External Reset
The Cortex-M3 differentiates the reset of the debug part (generally PORRESETn) and the
other one (SYSRESETn)
This way, it is possible for the debugger to connect under System Reset, programming the
Core Debug Registers to halt the core when fetching the reset vector. Then the host can
release the system reset and the core will immediately halt without having executed any
instructions. In addition, it is possible to program any debug features under System Reset.
Note: It is highly recommended for the debugger host to connect (set a breakpoint in the reset
vector) under system reset.

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20.12 FPB (Flash patch breakpoint)

The FPB unit:
● implements hardware breakpoints
● patches code and data from code space to system space. This feature gives the
possibility to correct software bugs located in the Code Memory Space.
The use of a Software Patch or a Hardware Breakpoint is exclusive.
The FPB consists of:
● 2 literal comparators for matching against literal loads from Code Space and remapping
to a corresponding area in the System Space.
● 6 instruction comparators for matching against instruction fetches from Code Space.
They can be used either to remap to a corresponding area in the System Space or to
generate a Breakpoint Instruction to the core.

20.13 DWT (data watchpoint trigger)

The DWT unit consists of four comparators. They are configurable as:
● a hardware watchpoint or
● a trigger to an ETM or
● a PC sampler or
● a data address sampler.
The DWT also provides some means to give some profiling informations. For this, some
counters are accessible to give the number of:
● Clock cycle
● Folded instructions
● Load store unit (LSU) operations
● Sleep cycles
● CPI (clock per instructions)
● Interrupt overhead

20.14 ITM (instrumentation trace macrocell)

20.14.1 General description

The ITM is an application-driven trace source that supports printf style debugging to trace
Operating System (OS) and application events, and emits diagnostic system information.
The ITM emits trace information as packets which can be generated as:
● Software trace. Software can write directly to the ITM stimulus registers to emit
packets.
● Hardware trace. The DWT generates these packets, and the ITM emits them.
● Time stamping. Timestamps are emitted relative to packets. The ITM contains a 21-bit
counter to generate the timestamp. The Cortex-M3 clock or the bit clock rate of the
Serial Wire Viewer (SWV) output clocks the counter.

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The packets emitted by the ITM are output to the TPIU (Trace Port Interface Unit). The
formatter of the TPIU adds some extra packets (refer to TPIU) and then output the complete
packets sequence to the debugger host.
The bit TRCEN of the Debug Exception and Monitor Control Register must be enabled
before you program or use the ITM.

20.14.2 Timestamp packets, synchronization and overflow packets

Timestamp packets encode timestamp information, generic control and synchronization. It
uses a 21-bit timestamp counter (with possible prescalers) which is reset at each time
stamp packet emission. This counter can be either clocked by the CPU clock or the SWV
clock.
A synchronization packet consists of 6 bytes equal to 0x80_00_00_00_00_00 which is
emitted to the TPIU as 00 00 00 00 00 80 (LSB emitted first).
A synchronization packet is a timestamp packet control. It is emitted at each DWT trigger.
For this, the DWT must be configured to trigger the ITM: the bit CYCCNTENA (bit0) of the
DWT Control Register must be set. In addition, the bit2 (SYNCENA) of the ITM Trace
Control Register must be set.
Note: If the SYNENA bit is not set, the DWT generates Synchronization triggers to the TPIU which
will send only TPIU synchronization packets and not ITM synchronization packets.
An overflow packet consists is a special timestamp packets which indicates that data has
been written but the FIFO was full.

Table 77. Main ITM registers

Address Register Details

Write 0xC5ACCE55 to unlock Write Access to the other ITM

@E0000FB0 ITM Lock Access
registers
Bits 31-24 = Always 0
Bits 23 = BUSY
Bits 22-16 = 7-bits ATB ID which identifies the source of the
trace data.
Bits 15-10 = Always 0
Bits 9:8 = TSPrescale = Time Stamp Prescaler
Bits 7-5 = Reserved
@E0000E80 ITM Trace Control
Bit 4 = SWOENA = Enable SWV behavior (to clock the
timestamp counter by the SWV clock).
Bit 3 = DWTENA: Enable the DWT Stimulus
Bit 2 = SYNCENA: this bit must be to 1 to enable the DWT to
generate synchronization triggers so that the TPIU can then
emit the synchronization packets.
Bit 1 = TSENA (Timestamp Enable)
Bit 0 = ITMENA: Global Enable Bit of the ITM

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Table 77. Main ITM registers

Address Register Details

Bit 3: mask to enable tracing ports31:24

Bit 2: mask to enable tracing ports23:16
@E0000E40 ITM Trace Privilege
Bit 1: mask to enable tracing ports15:8
Bit 0: mask to enable tracing ports7:0
Each bit enables the corresponding Stimulus port to generate
@E0000E00 ITM Trace Enable
trace.
@E0000000- Stimulus Port Write the 32-bits data on the selected Stimulus Port (32
E000007C Registers 0-31 available) to be traced out.

Example of configuration
To output a simple value to the TPIU:
● Configure the TPIU and enable the I/IO_TRACEN to assign TRACE I/Os in the MCU
● Write 0xC5ACCE55 to the ITM Lock Access Register to unlock the write access to the
ITM registers
● Write 0x00010005 to the ITM Trace Control Register to enable the ITM with Sync
enabled and an ATB ID different from 0x00
● Write 0x1 to the ITM Trace Enable Register to enable the Stimulus Port 0
● Write 0x1 to the ITM Trace Privilege Register to unmask stimulus ports 7:0
● Write the value to output in the Stimulus Port Register 0: this can be done by software
(using a printf function)

20.15 MCU debug component (MCUDBG)

The MCU debug component helps the debugger provide support for:
● Low-power modes
● Clock control for timers, watchdog and bxCAN during a breakpoint
● Control of the trace pins assignment

20.15.1 Debug support for low-power modes

To enter low-power mode, the instruction WFI or WFE must be executed.
The MCU implements several low-power modes which can either deactivate the CPU clock
or reduce the power of the CPU.
The core does not allow FCLK or HCLK to be turned off during a debug session. As these
are required for the debugger connection, during a debug, they must remain active. The
MCU integrates special means to allow the user to debug software in low-power modes.

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For this, the debugger host must first set some debug configuration registers to change the
low-power mode behavior:
● In SLEEP mode, DBG_SLEEP bit of DBGMCU_CR register must be previously set by
the debugger. This will feed HCLK with the same clock that is provided to FCLK
(system clock previously configured by the software).
● In STOP mode, the bit DBG_STOP must be previously set by the debugger. This will
enable the internal RC oscillator clock to feed FCLK and HCLK in STOP mode.

20.15.2 Debug support for timers and watchdog and bxCAN

During a breakpoint, it is necessary to choose how the counter of timers and watchdog
should behave:
● they can continue to count inside a breakpoint. This is usually required when a PWM is
controlling a motor, for example.
● They can stop to count inside a breakpoint. This is required for watchdog purposes.
For the bxCAN, the user can choose to block the update of the receive register during a
breakpoint.

20.15.3 Debug MCU configuration register

This register allows the configuration of the MCU under DEBUG. This concerns:
● Low-power mode support
● Timer and Watchdog counters support
● bxCAN communication support
● Trace pin assignment
This DBGMCU_CR is mapped on the External PPB bus at address 0xE0042000
It is asynchronously reset by the PORESET (and not the system reset). It can be written by
the debugger under system reset.
If the debugger host does not support these features, it is still possible for the user software
to write to these registers.

DBGMCU_CR
Address: 0xE0042004
Only 32-bits access supported
POR Reset: 0x00000000 (not reset by system reset)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DBG_
DBG_ DBG_ DBG_ DBG_ DBG_ DBG_ TRACE_ TRACE DBG_
WWDG DBG_ DBG_
Res. CAN_ TIM4_ TIM3_ TIM2_ TIM1_ IWDG MODE _ Reserved STAND
_ STOP SLEEP
STOP STOP STOP STOP STOP STOP [1:0] IOEN BY
STOP

rw rw rw rw rw rw rw rw rw rw rw rw rw

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Bits 31:15 Reserved, must be kept cleared.

DBG_CAN_STOP: Debug CAN stopped when Core is halted
Bit 14 0: Same behavior as in normal mode.
1: The CAN receive registers are frozen.
DBG_TIMx_STOP: Regular data. x=4..1
Bits 13:10 0: The clock of the involved Timer Counter is fed even if the core is halted.
1: The clock of the involved Timer counter is stopped when the core is halted.
DBG_WWDG_STOP: Debug Window Watchdog stopped when Core is halted
Bit 9 0: The Window Watchdog Counter clock continues even if the core is halted.
1: The Window Watchdog Counter clock is stopped when the core is halted.
DBG_IWDG_STOP: Debug Independent Watchdog stopped when Core is
halted
Bit 8
0: The Watchdog counter clock continues even if the core is halted.
1: The Watchdog counter clock is stopped when the core is halted.
TRACE_MODE[1:0] and TRACE_IOEN: Trace Pin Assignment Control
– With TRACE_IOEN=0:
TRACE_MODE=xx: TRACE pins not assigned (default state)
– With TRACE_IOEN=1:
TRACE_MODE=00: TRACE pin assignment for Asynchronous Mode
Bits 7:5 TRACE_MODE=01: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 1
TRACE_MODE=10: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 2
TRACE_MODE=11: TRACE pin assignment for Synchronous Mode with a
TRACEDATA size of 4
Bit 4:3 Reserved, must be kept cleared.
DBG_STANDBY: Debug Standby mode
0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
From software point of view, exiting from STANDBY is identical than fetching
reset vector (except a few status bit indicated that the MCU is resuming from
Bit 2 STANDBY)
1: (FCLK=On, HCLK=On) In this case, the digital part is not unpowered and
FCLK and HCLK are provided by the internal RC oscillator which remains
active. In addition, the MCU generate a system reset during STANDBY mode
so that exiting from STANDBY is identical than fetching from reset

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DBG_STOP: Debug Stop Mode

0: (FCLK=Off, HCLK=Off) In STOP mode, the clock controller disables all
clocks (including HCLK and FCLK). When exiting from STOP mode, the clock
configuration is identical to the one after RESET (CPU clocked by the 8 MHz
internal RC oscillator (HSI)). Consequently, the software must reprogram the
Bit 1 clock controller to enable the PLL, the Xtal, etc.
1: (FCLK=On, HCLK=On) In this case, when entering STOP mode, FCLK and
HCLK are provided by the internal RC oscillator which remains active in STOP
mode. When exiting STOP mode, the software must reprogram the clock
controller to enable the PLL, the Xtal, etc. (in the same way it would do in case
of DBG_STOP=0)
DBG_SLEEP: Debug Sleep Mode
0: (FCLK=On, HCLK=Off) In SLEEP mode, FCLK is clocked by the system
clock as previously configured by the software while HCLK is disabled.
In SLEEP mode, the clock controller configuration is not reset and remains in
Bit 0 the previously programmed state. Consequently, when exiting from SLEEP
mode, the software does not need to reconfigure the clock controller.
1: (FCLK=On, HCLK=On) In this case, when entering SLEEP mode, HCLK is
fed by the same clock that is provided to FCLK (system clock as previously
configured by the software).

20.16 TPIU (trace port interface unit)

20.16.1 Introduction
The TPIU acts as a bridge between the on-chip trace data from the ITM.
The output data stream encapsulates the trace source ID, that is then captured by a Trace
Port Analyzer (TPA).
The core embeds a simple TPIU, especially designed for low-cost debug (consisting of a
special version of the CoreSight TPIU).
The TPIU only supports ITM debug trace which is a limited trace as it only outputs
information coming from the ITM.

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CLK Domain TRACECLKIN Domain

TPIU

TRACECLKIN

TRACECK

Asynchronous TPIU Trace Out

ITM Formatter TRACEDATA
FIFO (serializer)
[3:0]

TRACESWO

External PPB Bus

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20.16.2 Trace pin assignment

● Asynchronous mode
The asynchronous mode requires 1 extra pin and is available on all packages. It is only
available if using Serial Wire mode (not in JTAG mode).
Trace synchronous mode
STM32F10x pin
TPUI pin name
assignment
Type Description

TRACESWO O TRACE Async Data Output PB3

● Synchronous mode
The synchronous mode requires from 2 to 6 extra pins depending on the data trace
size and is only available in the larger packages. In addition it is available in JTAG mode
and in Serial Wire mode and provides better bandwidth output capabilities than
asynchronous trace.
Trace synchronous mode
STM32F10x pin
TPUI pin name
assignment
Type Description

TRACECK O TRACE Clock PE2

TRACE Sync Data Outputs
TRACED[3:0] O PE[6:3]
Can be 1, 2 or 4.

TPUI Trace pins assignment

By default, these pins are NOT assigned. They can be assigned by setting the IOTRACEN
and IOTRACEMODE bits of the MCU Debug Component Configuration Register. This
configuration has to be done by the debugger host.
In addition, the number of pins to assign depends on the trace configuration (asynchronous
or synchronous).
● Asynchronous mode: 1 extra pin is needed
● Synchronous mode: from 2 to 5 extra pins are needed depending on the size of the
data trace port register (1, 2 or 4):
– TRACECK
– TRACED(0) if port size is configured to 1, 2 or 4
– TRACED(1) if port size is configured to 2 or 4
– TRACED(2) if port size is configured to 4
– TRACED(3) if port size is configured to 4
To assign the TRACE pin, the debugger host must program the bits TRACE_IOEN and
TRACE_MODE[1:0] of the Debug MCU configuration Register (DBGMCU_CR). By default
the TRACE pins are not assigned.
This register is mapped on the external PPB and is reset by the PORESET (and not by the
SYSTEM reset). It can be written by the debugger under SYSTEM reset.

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DBGMCU_CR
TRACE I/O pin assigned
register

MODE[1:0]
TRACE_ Pins assigned for: PB3 /

TRACE_
IOEN PE2 / PE3 / PE4 / PE5 / PE6 /
JTDO/
TRACE TRACE TRACE TRACE TRACE
TRACES
CK D[0] D[1] D[2] D[3]
WO

No Trace (default Released

0 XX (1)
state)
TRACES Released
1 00 Asynchronous Trace
WO (usable as GPIO)
Synchronous Trace TRACE TRACE
1 01
1 bit CK D[0]
Synchronous Trace Released TRACE TRACE TRACE
1 10 (1)
2 bit CK D[0] D[1]
Synchronous Trace TRACE TRACE TRACE TRACE TRACE
1 11
4 bit CK D[0] D[1] D[2] D[3]
(1) When Serial Wire mode is used, it is released. But when JTAG is used, it is assigned to JTDO.

Note: By default, the TRACECLKIN input clock of the TPIU is tied to GND. It is assigned to HCLK
two clock cycles after the bit TRACE_IOEN has been set.
The debugger must then program the Trace Mode by writing the bits PROTOCOL[1:0] of the
SPP_R (Selected Pin Protocol) register of the TPIU.
● PROTOCOL=00: Trace Port Mode (synchronous)
● PROTOCOL=01 or 10: Serial Wire (Manchester or NRZ) Mode (asynchronous mode).
Default state is 01
It then also configures the trace port size by writing the bits [3:0] of the CPSPS_R (Current
Sync Port Size Register) of the TPIU:
● 0x1 for 1 pin (default state)
● 0x2 for 2 pins
● 0x4 for 4 pins

20.16.3 TPUI formatter

The formatter protocol outputs data in 16-byte frames:
● seven bytes of data
● eight bytes of mixed-use bytes consisting of:
– 1 bit (LSB) to indicate it is a DATA byte (‘0’) or an ID byte (‘1’).
– 7 bits (MSB) which can be data or change of source ID trace.
● one byte of auxiliary bits where each bit corresponds to one of the eight mixed-use
bytes:
– if the corresponding byte was a data, this bit gives bit0 of the data.
– if the corresponding byte was an ID change, this bit indicates when that ID change
takes effect.

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Note: Refer to the ARM CoreSight Architecture Specification v1.0 (ARM IHI 0029B) for further
information
Use of the formatter for STM32F10x MCU
For STM32F10x MCU, there is only one TRACE source (the ITM). But the formatter can not
be disabled and must be used in bypass mode because the TRACECTL pin is not assigned.
This way, the Trace Port Analyzer can decode part of the formatter protocol to determine the
position of the trigger.

20.16.4 TPUI frame synchronization packets

The TPUI can generate two types of synchronization packets:
● The Frame Synchronization packet (or Full Word Synchronization packet)
It consists of the word: 0x7F_FF_FF_FF (LSB emitted first). This sequence can not
occur at any other time provided that the ID source code 0x7F has not been used.
It is output periodically between frames.
In continuous mode, the TPA must discard all these frames once a synchronization
frame has been found.
● The Half-Word Synchronization packet
It consists of the half word: 0x7F_FF (LSB emitted first).
It is output periodically between or within frames.
These packets are only generated in continuous mode and enable the TPA to detect
that the TRACE port is in IDLE mode (no TRACE to be captured). When detected by
the TPA, it must be discarded.

20.16.5 Emission of synchronization frame packet

There is no Synchronization Counter register implemented in the TPIU of the core.
Consequently, the synchronization trigger can only be generated by the DWT. Refer to the
registers DWT Control Register (bits SYNCTAP[11:10]) and the DWT Current PC Sampler
Cycle Count Register.
The TPUI Frame synchronization packet (0x7F_FF_FF_FF) is emitted:
● after each TPIU reset release. This reset is synchronously released with the rising
edge of TRACECLKIN clock. This means that this packet is emitted once the bit
IO_TRACEN of the DBGMCU_CFG register has been set. In this case, the word
0x7F_FF_FF_FF is not followed by any formatted packet.
● at each DWT trigger (assuming DWT has been previously configured). Two cases
occur:
– If the bit SYNENA of the ITM is reset, only the word 0x7F_FF_FF_FF is emitted
without any formatted stream which follows.
– If the bit SYNENA of the ITM is set, then the ITM synchronization packets will
follow (0x80_00_00_00_00_00), formatted by the TPUI (trace source ID added).

20.16.6 Synchronous mode

The trace data output size can be configured to 4, 2 or 1 pin: TRACED(3:0)
The output clock is output to the debugger (TRACECK)

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Here, TRACECLKIN is driven internally and is connected to HCLK only when TRACE is
used.
Note: In this synchronous mode, it is not required to provide a stable clock frequency.
The TRACE I/Os (including TRACECK) are driven by the rising edge of TRACLKIN (equal to
HCLK). Consequently, the output frequency of TRACECK is equal to HCLK/2.

20.16.7 Asynchronous mode

This is a low cost alternative to output the trace using only 1 pin: this is the asynchronous
output pin TRACESWO. Obviously there is a limited bandwidth.
TRACESWO is multiplexed with JTDO when using the SW-DP pin. This way, this
functionality is available in all STM32F10x packages.
This asynchronous mode requires a constant frequency for TRACECLKIN. For the standard
UART (NRZ) capture mechanism, 5% accuracy is needed. The Manchester encoded
version is tolerant up to 10%.

20.16.8 TRACECLKIN connection inside STM32F10x

In STM32F10x, this TRACECLKIN input is internally connected to HCLK. This means that
when in asynchronous trace mode, the application is restricted to use to time frames where
the CPU frequency is stable.
Note: Important: when using asynchronous trace: it is important to be aware that:
The default clock of the STM32F10x MCU is the internal RC oscillator. Its frequency under
reset is different from the one after reset release. This is because the RC calibration is the
default one under system reset and is updated at each system reset release.
Consequently, the Trace Port Analyzer (TPA) should not enable the trace (with the bit
IOTRACEN) under system reset, because a Synchronization Frame Packet will be issued
with a different bit time than trace packets which will be transmitted after reset release.

20.16.9 TPIU registers

The TPIU APB registers can be read and written only if the bit TRCENA of the Debug
Exception and Monitor Control Register (DEMCR) is set. Otherwise, the registers are read
as zero (the output of this bit enables the PCLK of the TPIU).

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Table 78. Important TPIU registers

Address Register Description

Allows the trace port size to be selected:

Bit 0: Port size = 1
Bit 1: Port size = 2
0xE0040004 Current Port Size Bit 2: Port Size = 3
Bit 3: Port Size = 4
Only 1 bit must be set. By default, the port size is one bit
(0x00000001)
Allows the Trace Port Protocol to be selected:
Bit1:0=
Selected Pin 00: Sync Trace Port Mode
0xE00400F0
Protocol 01: Serial Wire Output - manchester (default value)
10: Serial Wire Output - NRZ
11: reserved
Bit 31-9 = always ‘0’
Bit 8 = TrigIn = always ‘1’ to indicate that triggers are indicated
Bit 7-4 = always 0
Bit 3-2 = always 0
Bit 1 = EnFCont. In Sync Trace mode (Select_Pin_Protocol
register bit1:0=00), this bit is forced to ‘1’: the formatter is
automatically enabled in continuous mode. In asynchronous
Formatter and
0xE0040304 mode (Select_Pin_Protocol register bit1:0 <> 00), this bit can
Flush Control
be written to activate or not the formatter.
Bit 0 = always 0
The resulting default value is 0x102
Note: In synchronous mode, because the TRACECTL pin is not
mapped outside the chip, the formatter is always enabled in
continuous mode -this way the formatter inserts some control
packets to identify the source of the trace packets).
Formatter and
0xE0040300 Not used in Cortex-M3, always read as 0x00000008
Flush Status

20.16.10 Example of configuration

● Set the bit TRCENA in the Debug Exception and Monitor Control Register (DEMCR)
● Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit
port size)
● Write TPIU Formatter and Flush Control Register to 0x102 (default value)
● Write the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for
async NRZ mode (UART like)
● Write the DBGMCU Control Register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os
for async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F)
● Configure the ITM and write the ITM Stimulus register to output a value

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20.17 DBG register map

The following table summarizes the Debug registers.

Table 79. DBG - register map and reset values

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
Addr. Register

9
8
7
6
5
4
3
2
1
0
0xE0042000

DBGMCU_
DEV_ID
IDCODE Reserved

Reset Value 0 1 0 0 0 0 0 1 0 0 0 0

DBG_WWDG_STOP
DBG_IWDG_STOP
DBG_TIM4_STOP
DBG_TIM3_STOP
DBG_TIM2_STOP
DBG_TIM1_STOP
DBG_CAN_STOP

DBG_STANDBY
TRACE_MODE

TRACE_IOEN

DBG_SLEEP
DBG_STOP
0xE0042004

Reserved
[1:0]
DBGMCU_CR
Reserved

Reset Value 0 0 0 0 0 0 0 0 0 0 0 0 0

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Revision history UM0306

21 Revision history

Table 80. Document revision history

Date Revision Changes

01-Jun-2007 1 Initial release.

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UM0306 Index

Index

A
ADC_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .472
ADC_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .474
ADC_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . .484
ADC_HTR . . . . . . . . . . . . . . . . . . . . . . . . . . .479
ADC_JDRx . . . . . . . . . . . . . . . . . . . . . . . . . . .484
ADC_JOFRx . . . . . . . . . . . . . . . . . . . . . . . . .479
ADC_JSQR . . . . . . . . . . . . . . . . . . . . . . . . . .483
ADC_LTR . . . . . . . . . . . . . . . . . . . . . . . . . . . .480
ADC_SMPR1 . . . . . . . . . . . . . . . . . . . . . . . . .477
ADC_SMPR2 . . . . . . . . . . . . . . . . . . . . . . . . .478
ADC_SQR1 . . . . . . . . . . . . . . . . . . . . . . . . . .481
ADC_SQR2 . . . . . . . . . . . . . . . . . . . . . . . . . .482
ADC_SQR3 . . . . . . . . . . . . . . . . . . . . . . . . . .482
ADC_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .471
AFIO_EVCR . . . . . . . . . . . . . . . . . . . . . . . . . . .91
AFIO_EXTICR1 . . . . . . . . . . . . . . . . . . . . . . . .95
AFIO_EXTICR2 . . . . . . . . . . . . . . . . . . . . . . . .95
AFIO_EXTICR3 . . . . . . . . . . . . . . . . . . . . . . . .96
AFIO_EXTICR4 . . . . . . . . . . . . . . . . . . . . . . . .96
AFIO_MAPR . . . . . . . . . . . . . . . . . . . . . . . . . .92

B
BKP_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
BKP_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . .135
BKP_DRx . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
BKP_RTCCR . . . . . . . . . . . . . . . . . . . . . . . . .134

C
CAN_BTR . . . . . . . . . . . . . . . . . . . . . . . . . . .313
CAN_ESR . . . . . . . . . . . . . . . . . . . . . . . . . . .312
CAN_FA0R . . . . . . . . . . . . . . . . . . . . . . . . . .322
CAN_FFA0R . . . . . . . . . . . . . . . . . . . . . . . . .322
CAN_FM0R . . . . . . . . . . . . . . . . . . . . . . . . . .321
CAN_FMR . . . . . . . . . . . . . . . . . . . . . . . . . . .320
CAN_FS0R . . . . . . . . . . . . . . . . . . . . . . . . . .321
CAN_FxR . . . . . . . . . . . . . . . . . . . . . . . . . . . .322
CAN_IER . . . . . . . . . . . . . . . . . . . . . . . . . . . .310
CAN_MCR . . . . . . . . . . . . . . . . . . . . . . . . . . .300
CAN_MSR . . . . . . . . . . . . . . . . . . . . . . . . . . .303
CAN_RDHxR . . . . . . . . . . . . . . . . . . . . . . . . .319
CAN_RDLxR . . . . . . . . . . . . . . . . . . . . . . . . .318
CAN_RDTxR . . . . . . . . . . . . . . . . . . . . . . . . .318
CAN_RF0R . . . . . . . . . . . . . . . . . . . . . . . . . .308
CAN_RF1R . . . . . . . . . . . . . . . . . . . . . . . . . .309
CAN_RIxR . . . . . . . . . . . . . . . . . . . . . . . . . . .317

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CAN_TDHxR . . . . . . . . . . . . . . . . . . . . . . . . .316
CAN_TDLxR . . . . . . . . . . . . . . . . . . . . . . . . .315
CAN_TDTxR . . . . . . . . . . . . . . . . . . . . . . . . .315
CAN_TIxR . . . . . . . . . . . . . . . . . . . . . . . . . . .314
CAN_TSR . . . . . . . . . . . . . . . . . . . . . . . . . . .305

D
DBGMCU_CR . . . . . . . . . . . . . . . . . . . . . . . .504
DBGMCU_IDCODE . . . . . . . . . . . . . . . . . . . .493
DMA_CMARx . . . . . . . . . . . . . . . . . . . . . . . . .118
DMA_CNDTRx . . . . . . . . . . . . . . . . . . . . . . . .117
DMA_CPARx . . . . . . . . . . . . . . . . . . . . . . . . .118
DMA_IFCR . . . . . . . . . . . . . . . . . . . . . . . . . . .115
DMA_ISR . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

E
EXTI_EMR . . . . . . . . . . . . . . . . . . . . . . . . . . .104
EXTI_FTSR . . . . . . . . . . . . . . . . . . . . . . . . . .105
EXTI_IMR . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
EXTI_PR . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
EXTI_RTSR . . . . . . . . . . . . . . . . . . . . . . . . . .105
EXTI_SWIER . . . . . . . . . . . . . . . . . . . . . . . . .106

G
GPIOx_BRR . . . . . . . . . . . . . . . . . . . . . . . . . . .85
GPIOx_BSRR . . . . . . . . . . . . . . . . . . . . . . . . .84
GPIOx_CRH . . . . . . . . . . . . . . . . . . . . . . . . . . .81
GPIOx_CRL . . . . . . . . . . . . . . . . . . . . . . . . . . .80
GPIOx_IDR . . . . . . . . . . . . . . . . . . . . . . . . . . .82
GPIOx_LCKR . . . . . . . . . . . . . . . . . . . . . . . . . .86
GPIOx_ODR . . . . . . . . . . . . . . . . . . . . . . . . . .83

I
I2C_CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .356
I2C_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
I2C_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
I2C_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350
I2C_OAR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .349
I2C_OAR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .349
I2C_SR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351
I2C_SR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354
I2C_TRISE . . . . . . . . . . . . . . . . . . . . . . . . . . .357
IWDG_KR . . . . . . . . . . . . . . . . . . . . . . . . . . .139
IWDG_PR . . . . . . . . . . . . . . . . . . . . . . . . . . .141
IWDG_RLR . . . . . . . . . . . . . . . . . . . . . . . . . .142
IWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . . .142

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P
PWR_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PWR_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

R
RCC_AHBENR . . . . . . . . . . . . . . . . . . . . . . . .64
RCC_APB1ENR . . . . . . . . . . . . . . . . . . . . . . . .67
RCC_APB1RSTR . . . . . . . . . . . . . . . . . . . . . .62
RCC_APB2ENR . . . . . . . . . . . . . . . . . . . . . . . .65
RCC_APB2RSTR . . . . . . . . . . . . . . . . . . . . . .60
RCC_BDCR . . . . . . . . . . . . . . . . . . . . . . . . . . .69
RCC_CFGR . . . . . . . . . . . . . . . . . . . . . . . . . . .54
RCC_CIR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
RCC_CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
RCC_CSR . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
RTC_ALRH . . . . . . . . . . . . . . . . . . . . . . . . . .131
RTC_ALRL . . . . . . . . . . . . . . . . . . . . . . . . . . .131
RTC_CNTH . . . . . . . . . . . . . . . . . . . . . . . . . .130
RTC_CNTL . . . . . . . . . . . . . . . . . . . . . . . . . .130
RTC_CRH . . . . . . . . . . . . . . . . . . . . . . . . . . .125
RTC_CRL . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
RTC_DIVH . . . . . . . . . . . . . . . . . . . . . . . . . . .129
RTC_DIVL . . . . . . . . . . . . . . . . . . . . . . . . . . .129
RTC_PRLH . . . . . . . . . . . . . . . . . . . . . . . . . .128
RTC_PRLL . . . . . . . . . . . . . . . . . . . . . . . . . . .128

S
SPI_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
SPI_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
SPI_CRCPR . . . . . . . . . . . . . . . . . . . . . . . . . .374
SPI_DR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .374
SPI_RXCRCR . . . . . . . . . . . . . . . . . . . . . . . .374
SPI_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
SPI_TXCRCR . . . . . . . . . . . . . . . . . . . . . . . .375

T
TIM1_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . .212
TIM1_BDTR . . . . . . . . . . . . . . . . . . . . . . . . . .216
TIM1_CCER . . . . . . . . . . . . . . . . . . . . . . . . . .209
TIM1_CCMR1 . . . . . . . . . . . . . . . . . . . . . . . .204
TIM1_CCMR2 . . . . . . . . . . . . . . . . . . . . . . . .208
TIM1_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . . .213
TIM1_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . .214
TIM1_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . .214
TIM1_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . .215
TIM1_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . .212
TIM1_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .191
TIM1_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .193
TIM1_DCR . . . . . . . . . . . . . . . . . . . . . . . . . . .218

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TIM1_DIER . . . . . . . . . . . . . . . . . . . . . . . . . .198
TIM1_DMAR . . . . . . . . . . . . . . . . . . . . . . . . .218
TIM1_EGR . . . . . . . . . . . . . . . . . . . . . . . . . . .202
TIM1_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . .212
TIM1_RCR . . . . . . . . . . . . . . . . . . . . . . . . . . .213
TIM1_SMCR . . . . . . . . . . . . . . . . . . . . . . . . .195
TIM1_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
TIMx_ARR . . . . . . . . . . . . . . . . . . . . . . . . . . .276
TIMx_CCER . . . . . . . . . . . . . . . . . . . . . . . . . .274
TIMx_CCMR1 . . . . . . . . . . . . . . . . . . . . . . . .268
TIMx_CCMR2 . . . . . . . . . . . . . . . . . . . . . . . .272
TIMx_CCR1 . . . . . . . . . . . . . . . . . . . . . . . . . .276
TIMx_CCR2 . . . . . . . . . . . . . . . . . . . . . . . . . .277
TIMx_CCR3 . . . . . . . . . . . . . . . . . . . . . . . . . .277
TIMx_CCR4 . . . . . . . . . . . . . . . . . . . . . . . . . .278
TIMx_CNT . . . . . . . . . . . . . . . . . . . . . . . . . . .275
TIMx_CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . .257
TIMx_CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . .259
TIMx_DCR . . . . . . . . . . . . . . . . . . . . . . . . . . .279
TIMx_DIER . . . . . . . . . . . . . . . . . . . . . . . . . . .263
TIMx_DMAR . . . . . . . . . . . . . . . . . . . . . . . . . .279
TIMx_EGR . . . . . . . . . . . . . . . . . . . . . . . . . . .267
TIMx_PSC . . . . . . . . . . . . . . . . . . . . . . . . . . .275
TIMx_SMCR . . . . . . . . . . . . . . . . . . . . . . . . . .260
TIMx_SR . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

U
USART_BRR . . . . . . . . . . . . . . . . . . . . . . . . .409
USART_CR1 . . . . . . . . . . . . . . . . . . . . . . . . .410
USART_CR2 . . . . . . . . . . . . . . . . . . . . . . . . .413
USART_CR3 . . . . . . . . . . . . . . . . . . . . . . . . .415
USART_DR . . . . . . . . . . . . . . . . . . . . . . . . . .409
USART_GTPR . . . . . . . . . . . . . . . . . . . . . . . .417
USART_SR . . . . . . . . . . . . . . . . . . . . . . . . . .406

W
WWDG_CFR . . . . . . . . . . . . . . . . . . . . . . . . .148
WWDG_CR . . . . . . . . . . . . . . . . . . . . . . . . . .148
WWDG_SR . . . . . . . . . . . . . . . . . . . . . . . . . .149

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