Digital Circuits

EE/CE 3320 / Spring 2020 / Lecture 12

University of Texas Dallas
Dr. Tooraj Nikoubin Sequential Elements
 How to keep 1-bit data with logic gates ?

What about a memory cell structure ?

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Inverter-Based Latch,

In Out

Out In

In Out
Out In

0 1
1 0
EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nand-Based Latch,

S Q

Q
R

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nor-Based Latch

S Q

Q
R

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Inverter-Based Latch, Nand-Based Latch, Nor-Based Latch

In Out
S Q S Q

Out In
Q Q
In Out R R
Out In

0 1
1 0
EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nand-Based Latch with level sensitive CLK

S S1
Q

Q
R
R1

Clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nor-Based Latch with level sensitive CLK

S S1
Q

Q
R
R1

Clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nand-Based Latch with level sensitive CLK
Nor-Based Latch with level sensitive CLK
S S1 S S1
Q Q

Q Q

R R
R1 R1

Clk Clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 SR Flip-Flop
Maser-Slave structure
High to Low Effective Edge

S S Q
S S1
Q
S1
Q S M S S
Q
R R R
Q Q
R R1 R1
R
clk
Clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 D-Flip-Flop
Maser-Slave structure
High to Low Effective Edge

D Q
S M S S
Q
R R
clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 T-Flip-Flop
Maser-Slave structure
High to Low Effective Edge

Q
S M S S
Q
R R
clk
T

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 D-Flip-Flop T-Flip-Flop
Maser-Slave structure Maser-Slave structure
High to Low Effective Edge High to Low Effective Edge

Q
D Q S M S S
S M S S
Q
Q R R
R R
clk
clk
T

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 JK-MS-Flip-Flop
Maser-Slave structure
High to Low Effective Edge

Q
J S M S S
Q
K R R

clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 Shift Register

Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 Shift Register
I3 I2 I1 I0
Load t2

Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 Shift Register

I3 I2 I1 I0
Load t2

Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 I3 I2 I1 I0
Load t2

Example
Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

X t

A
B
C
D

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 I3 I2 I1 I0
Load t2

Example
Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK
Hold time
X t Setup time

Maximum CLK Rate

A or
Maximum
B Frequency

C
D

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 1-SR-FF
2-D-FF
3-T-FF
4-JK-MS-FF

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Inverter-Based Latch, Nand-Based Latch, Nor-Based Latch
In Out
S Q S Q

Out In
Q Q
In Out R R
Out In

0 1
1 0

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nand-Based Latch with level sensitive CLK
Nor-Based Latch with level sensitive CLK
S S1 S S1
Q Q

Q Q

R R
R1 R1

Clk Clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 SR Flip-Flop
Maser-Slave structure
High to Low Effective Edge

S Q
S S1
Q
S S1
Q
S M S S
Q
R R R
Q Q
R R1 R1
R clk
Clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 D-Flip-Flop T-Flip-Flop
Maser-Slave structure Maser-Slave structure
High to Low Effective Edge High to Low Effective Edge

D Q
S M S S
Q
R R
Q S M S S
Q
clk R R
clk
T

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 JK-MS-Flip-Flop
Maser-Slave structure
High to Low Effective Edge

Q
J S M S S
Q
K R R

clk

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 Shift Right

Input Output
D D D D
A B C D

CLK

High to Low Edge

Low to High Edge

Efective Edge

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 Shift Right

Input Output
D D D D
A B C D

CLK

Shift Left
Output
Input

D D D D
A B C D

CLK

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 X
Shift Right and Left
0 Shift _Right

1 Shift_Left

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 X Shift Right and Left
0 Shift _Right

1 Shift_Left

Output_Left
Input_Left
Input_Right 0 0 0 0
MUX MUX MUX MUX
1 2x1 1 2x1 1 2x1 1 2x1
s s s s

D D D D
A C D Output_Right
B

CLK

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 X Shift Right and Left
0 Shift _Right

1 Shift_Left

Output_Left
Input_Left
Input_Right 0 0 0 0
MUX MUX MUX MUX
1 2x1 1 2x1 1 2x1 1 2x1
s s s s

X
Control Signal
D D D D
A C D Output_Right
B

CLK
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 ❑ Parallel Load
( with Asynchronous inputs)

❑ Parallel Load
( with Synchronous inputs )

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 Nand-Based Latch with Asynchronous Inputs
S S1 S S1
Q Q

Q Q
R R
R1 R1

Clk Clk

S S

S S1 S S1
Q
Q

Q
Q
R
R R1
R1

Clk
Clk R
R

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 Nand-Based Latch with Asynchronous Inputs
S S

S S1 S1
Q S Q

Q
Q
R R
R1 R1

Clk
Clk R
R

Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
 ❑ Parallel Load ( Asynchronous pins)
I3 I2 I1 I0
Load t2

Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

S: Preset , Primary Set

R: Clear , Primary Reset

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 ❑ Parallel Load ( Asynchronous pins )

I3 I2 I1 I0
Load

Input s s s s Output
D D D D
A B C D
Clear R R R R

CLK
t1 t2

S: Preset , Primary Set

R: Clear , Primary Reset

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 ❑ Parallel Load ( Synchronous pins)

I3 I2 I1 I0
Load

s s s s
D D D D
A B C D
R R R R

CLK

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 ❑ Parallel Load ( Asynchronous pins )
I3 I2 I1 I0
Load t2

Input s s s s Output
D D D D
A B C D

Clear t1 R R R R

CLK

❑ Parallel Load ( Synchronous pins )

I3 I2 I1 I0
Load

s s s s
D D D D
A B C D
R R R R

CLK

EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements
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 Send
Serial output Serial input

Serial input Serial output

Receive

Parallel Parallel
processor processor
No. 1 No. 2

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 Serial to parallel & Parallel to serial convertor

I3 I2 I1 I0
Load

Input s s s s Output
D D D D
A B C D

Clear R R R R

CLK

D3 D2 D1 D0

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 Parallel to serial convertor
I3 I2 I1 I0
Load

s s s Output
? 0 Input
D D D D
s
A B C D

Clear R R R R

CLK

D3 D2 D1 D0

CLK
Load

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 Serial to parallel convertor
I3 I2 I1 I0
Load

Input s s s Output
s
D D D D
A B C D

Clear R R R R

CLK

Load

D3 D2 D1 D0

CLK
Load

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 Buffer
I0
D D Q

I1
D C Q

I2
D B Q

I3 D Q
A

CP

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 Buffer
I0 I0 0 0
D D Q D D Q
Q Q

I1 I1 0 1
D C Q C
D Q
Q Q

I2 I2 1 0
D B Q D B Q
Q Q

I3 1
D A Q I3 1 D Q
A
Q
Q

CP
CP
T1
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 Buffer
I0 0 I0 0
D D Q I0 0 D D Q
D D Q
Q Q Q

I1 I1 0 1 I1 0
D C Q C D C Q
D Q
Q Q Q

I2 0 I2 1
D B Q I2 1 D B Q
D B Q
Q Q Q

I3 1 I3 1
D A Q I3 1 D Q D A Q
A
Q Q
Q

CP CP
CP
T1 T2
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EE/CE 3320 / Dr. Tooraj Nikoubin / Spring 2020 / Lecture 12 / Sequential elements