Name:__________________________________ Number:___________________

Spring 2010
CPE231 Digital Logic

n
Section 1
Quiz 3-A
Problem 1
Design a sequential circuit with two D flip-flops A and B and one input X. When X=0, the
state of the circuit remains the same. When X=1, the circuit goes through the state
transitions from 00 to 10 to 11 to 01, back to 00, and then repeats. You do not have to
draw the logic diagram.
1 mark

χ©
1 mark

eno
fl@Ú«
‹ü@Â
2 marks 2 marks

a@Új
4 marks

ç܉:
a@M@Ú
»flb¶
â˛a@Ú
ÚÓ„Ö

Page 1 of 1
Name:__________________________________ Number:___________________

Spring 2010
CPE231 Digital Logic

n
Section 1
Quiz 3-B
Problem 1
Design a sequential circuit with two D flip-flops A and B and one input X. When X=1, the
state of the circuit remains the same. When X=0, the circuit goes through the state
transitions from 00 to 11 to 01 to 10, back to 00, and then repeats. You do not have to
draw the logic diagram.

χ©
Present state Input Next state
A B X A B
0 0 0 1 1

eno 0 0 1 0 0

fl@Ú«
0 1 0 1 0 4 marks
0 1 1 0 1
1 0 0 0 0
1 0 1 1 0

‹ü@Â
1 1 0 0 1
1 1 1 1 1

a@Új
DA B
1 1
1 1
1 mark
A

ç܉:
X

DA=AX+A'X' 2 marks
a@M@Ú
»flb¶

DB B
1 1
1 1
1 mark
â˛a@Ú

A
X

DB=AB+BX+A'B'X' 2 marks
ÚÓ„Ö

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Name:__________________________________ Number:___________________

Spring 2010
CPE231 Digital Logic

n
Section 2 ; Quiz 3-A
A serial leading 0’s detector is to be designed. A binary integer of arbitrary length is presented to the
serial leading 0’s detector, most significant bit first, on input X. When a given bit is presented on input X,
the corresponding output bit is to appear during the same clock cycle on output Z. As long as the bits
applied to X are 1, Z = 1. When the first 0 is applied to X, Z = 0. For all bit values applied to X after the
first 0 is applied, Z = 1. To indicate that a sequence is complete and that the circuit is to be initialized to
receive another sequence, input Y becomes 1 for one clock cycle. Otherwise, Y is 0.

χ©
(a) Find the state diagram for the serial leading 0’s detector.
(b) Find the state table for the serial leading 0’s detector.

eno
fl@Ú«
a.

‹ü@Â
a@Új
b.

A(present X Y A(next Z
ç܉:
a@M@Ú
state) state)
0 0 0 1 0
0 0 1 0 0
0 1 0 0 1
»flb¶

0 1 1 0 1
1 0 0 1 1
1 0 1 0 1
â˛a@Ú

1 1 0 1 1
1 1 1 0 1
ÚÓ„Ö

Page 1 of 1
Name:__________________________________ Number:___________________

Spring 2010
CPE231 Digital Logic

n
Section 2 ; Quiz 3-B

Problem
A communication network link requires a circuit that produces the sequence 01111110. You are to
design a synchronous sequential circuit that starts producing this sequence for input E = 1. Once the
sequence starts, it completes. If E = 1, during the last output in the sequence, the sequence repeats.
Otherwise, if E 0, the output remains constant at 0.

χ©
(a) Draw the Moore state diagram for the circuit.
(b) Find the state table and make a state assignment.

eno
a.

fl@Ú«
‹ü@Â
a@Új
b.
ç܉:
a@M@Ú
D2D1D0 E=0 E=1 Z
000 001 001 0
001 010 010 1
»flb¶

010 011 011 1

011 100 100 1
100 101 101 1
â˛a@Ú

101 110 110 1

110 111 111 1
111 111 000 0
ÚÓ„Ö

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