AN IMPLEMENTATION OF DETECTING AND CORRECTING

MULTIPLE BIT UPSETS IN STATIC RANDOM ACCESS

MEMORIES
A Project Report Submitted to
Jawaharlal Nehru Technological University Anantapur, Anantapuram

In partial fulfillment of the requirements

For the award of the degree of
MASTER OF TECHNOLOGY
IN
VLSI Design

By

A.Rupavathi
(14JE1D5703)

Under the guidance of

Mrs. K . Yogitha Bali M.Tech
ASISSTANT PROFESSOR
Department of E.C.E

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SHREE RAMA EDUCATIONAL SOCIETY GROUP OF INSTITUTIONS
(Affiliated to JNTUA, Anantapur and Approved by AICTE, New Delhi)
Rami Reddy Nagar, Karakambadi Road, Tirupathi – 517 507, A.P
(2014 -2016)
 SHREE RAMA EDUCATIONAL SOCIETY GROUP OF
INSTITUTIONS
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE

Certified that this is a bonafide record of the project work entitled,” AN

IMPLEMENTATION OF DETECTING AND CORRECTING MULTIPLE BIT
UPSETS IN STATIC RANDOM ACCESS MEMORIES", done by A.Rupavathi
(14je1d5703), Submitted to the department of ELECTRONICS AND
COMMUNICATION ENGINEERING, in partial fulfillment of the requirements for
the Degree of MASTER OF TECHNOLOGY in VLSI DESIGN from Jawaharlal
Nehru Technological University Anantapur, Anantapur during the year 2014-2016.

Guide: Head of the Department:

Mrs.K. Yogitha Bali, M.Tech Mr. P. Giri Babu, M.Tech
Assistant Professor, Associate Professor & HOD,
Dept of ECE, Dept of ECE,
SRES GROUP OF INSTITUTIONS, SRES GROUP OF INSTITUTIONS,
Tirupati. Tirupati.

Viva-Voce held on……………………………………………

Internal Examiner External Examiner

 ACKNOWLEDGEMENT

I consider it is my privilege to express my gratitude and respect to all those who guided,
inspired and helped me in the completion of this Project.

I am thankful to our chairman Mr.MANNEM RAMI REDDY, Director

Mr.V.V.R.NARASIMHA RAO and Vic- Principal Mr.B.THIRVIKRAM for permitting me to
use facilities available in this college to accomplish the Project completely.

I express my deep sense of gratitude to Mr. P.GIRI BABU, Head of the department ECE
for his kind help that he extended at every stage of my work for all provisions made me to
complete this endeavor successfully.

I am thankful to my guide Mrs K .Yogitha Bali, Assistant professor, all for his guidance
and co-operation of Project work.

I am also thankful to all our staff members of electronics and communication engineering
for their co-operation.

Last but not least, I wish to thank to all my friends, and who helped directly or indirectly
in completion of my Project.
 DECLARATION BY THE STUDENT

I hereby declare that this project report titled “AN IMPLEMENTATION OF

DETECTING AND CORRECTING MULTIPLE BIT UPSETS IN STATIC
RANDOM ACCESS MEMORIES” is a genuine project work carried out by me, in
M.Tech, VLSI DESIGN degree course of Jawaharlal Nehru Technology University
Anantapur, Anantapur and has not been submitted to any other course or university for the
award of any degree.

Signature of the Student

(A.Rupavathi).

s
 ABSTRACT
Now a days to maintain good level of reliability, it is necessary to protect memory bits using
protection codes, for this purpose, various error detection and correction methods are being
used. In this paper 32-bit Matrix Code was proposed to assure the reliability of memory. Here to
detect and correct up to 8 errors. The proposed protection code utilized procedure to detect
errors, so that more errors were detected and corrected. The results showed that the proposed
scheme has a protection level against large MBUs in memory. Besides, the proposed error
detection technique is a striking opinion to detect MBUs in CAM since it can be combined with
BICS to provide an adequate level of immunity. Transient multiple bit upsets (MBUs) are
suitable major problems in the reliability of memories exposed to radiation environment. In the
proposed method we are implement 32-bit matrix for error correction in memories. To prevent
MBUs from causing data corruption, more complex error correction codes (ECCs) are widely
used to protect memory, but the main problem is that they would require higher delay overhead.
Recently, matrix codes (MCs) based on Hamming codes include been proposed for memory
protection. The main issue is that they are double error correction codes and the error
correction capabilities are not enhanced in all cases. Moreover, the erasure codes is proposed to
reduce the area overhead of extra circuits exclusive of disturbing the total encoding and
decoding processes.
 TABLE OF CONTENTS
S.No CHAPTER NAME OF THE TITLE PAGE NO
NO
LIST OF TABLES i
LIST OF FIGURE ii-iv
ABBREVIATIONS v
1 1 INTRODUCTION 1-3
2 2 LITERATURE SURVEY 4-14
3 3 EXISTING SYSTEM 15-26
3.1 HIGHER-ORDER ECCS 15
3.2 BURST CODES 15
3.3 ERROR-LOCALITY-AWARE CODES 16
3.4 CONTRIBUTIONS 18
3.5 ERROR DETECTION CORRECTION CODES 19
3.5.1 TYPES OF ERRORS 19
3.5.1.1 SINGLE-BIT ERROR 19
3.5.1.2 BURST ERROR 20
3.5.2 ERROR DETECTION 21
3.5.2.1 REDUNDANCY 21
3.5.2.1.1 VERTICAL REDUNDANCY CHECK VRC 21
3.5.2.1.2 LONGITUDINAL REDUNDANCY CHECK 22
LRC
3.5.2.1.3 CHECKSUM 23
3.5.2.1.4 CYCLIC REDUNDANCY CHECK CRC 23
3.5.3 ERROR CORRECTION 23
3.5.3.1 SINGLE-BIT ERROR CORRECTION 24
3.5.4 HAMMING CODE 24
4 4 PROPOSED SYSTEM 27-34
 4.1 LOW-COST MBU DETECTION 28
4.1.1 IND PARITY 28
4.1.2 I2D PARITY 29
4.1.3 I3D PARITY 30
4.2 RECOVERY BASED ON ERASURE CODES 32
4.2.1 EFFECTIVE ERASURE CODE FOR ERROR 32
RECOVERY IN CONFIGURATION FRAMES
4.2.2 ERROR DETECTION AND RECOVERY UNIT 33
4.3 APPLICATIONS 34
4.4 ADVANTAGES 34
5 5 HISTORY OF VERILOG 35 -69
5.1 BASIC CONCEPTS 35
5.1.1 HARDWARE DESCRIPTION LANGUAGE 35
5.2 VERILOG INTRODUCTION 36
5.2.1 VERILOG FEATURES 36
5.3 DESIGN FLOW 36
5.3.1 DESIGN SPECIFICATION 36
5.4 RTL DESCRIPTION 36
5.4.1 CODING STYLES 37
5.5 FUNCTIONAL VERIFICATION &TESTING 37
5.5.1 LOGIC SYNTHESIS 38
5.5.2 LOGICAL VERIFICATION AND TESTING 39
5.6 FLOOR PLANNING AUTOMATIC PLACE 39
AND ROUTE
5.6.1 PHYSICAL LAYOUT 39
5.6.2 LAYOUT VERIFICATION 39
5.6.3 IMPLEMENTATION 39
5.7 DESIGN HIERARCHIES 40
5.7.1 BOTTOM UP DESIGN 40
5.7.2 TOP-DOWN DESIGN 40
5.8 LEXICAL CONVENTIONS 41
5.8.1 WHITESPACE 41
5.8.2 COMMENTS 42
5.8.3 IDENTIFIERS AND KEYWORDS 43
5.8.3.1 EXAMPLES OF LEGAL IDENTIFIERS 43
5.8.3.2 EXAMPLES OF KEYWORDS 43
5.8.4 ESCAPED IDENTIFIERS 43
5.9 NUMBERS IN VERILOG 43
5.9.1 INTEGER NUMBERS 44
5.9.2 REAL NUMBERS 44
5.9.3 STRINGS 46
5.9.4 DATA TYPES 46
5.9.4.1 DATA TYPES VALUE SET 46
5.9.4.2 VALUE LEVEL CONDITION IN HARDWARE 46
CIRCUITS
5.9.4.3 REGISTER DATA TYPES 46
5.9.5 VECTORS 47
5.9.5.1 INTEGER, REAL AND TIME REGISTER 47
DATA TYPES INTEGER
5.9.5.1.1 REAL 48
5.9.5.1.2 TIME 48
5.9.6 ARRAYS 49
5.9.7 MEMORIES 49
5.9.8 PARAMETERS 49
5.9.8.1 STRINGS 49
5.9.9 MODULES 50
5.9.9.1 INSTANCES 51
5.9.9.2 PORTS 52
5.9.9.2.1 PORT DECLARATION 52
5.9.9.2.2 VERILOG KEYWORD TYPE OF PORT 52
5.9.9.2.3 PORT CONNECTION RULES 53
5.9.9.2.4 INPUTS 53
5.9.9.2.5 OUTPUTS 53
5.9.9.2.6 INOUTS 53
5.9.9.2.7 PORTS CONNECTION TO EXTERNAL 53
SIGNALS
5.9.9.2.8 PORT BY ORDER LIST 53
5.9.9.2.9 PORT BY NAME 54
5.9.9.3 MODELING CONCEPTS 54
5.9.9.3.1 BEHAVIORAL OR ALGORITHMIC LEVEL 55
5.9.9.3.2 DATAFLOW LEVEL 55
5.9.9.3.3 GATE LEVEL 55
5.9.9.3.4 SWITCH LEVEL 55
5.9.9.4 GATE LEVEL MODELING 56
5.9.9.4.1 GATE TYPES 56
5.9.9.4.1.1 AND/OR GATES 56
5.9.9.4.1.2 AND OR XORNAND NOR XNOR 56
5.9.9.4.1.3 BUF/BUFIF1/BUFIF0/NOT/NOTFIF1/NOTFIF0 57
GATES
5.9.9.4.1.4 GATES BUT, NOT, BUFIF1, BUFIF0, NOTIF1, 58
NOTIFO
5.9.9.5 BEHAVIORAL AND RTL MODELING 62
5.9.9.5.1 OPERATORS 62
5.9.9.5.1.1 ARITHMETIC OPERATORS 63
5.9.9.5.1.2 RELATIONAL OPERATORS 64
5.9.9.5.1.3 BIT-WISE OPERATORS 65
5.9.9.5.1.4 LOGICAL OPERATORS 66
5.9.9.5.1.5 REDUCTION OPERATORS 66
5.9.9.5.1.6 SHIFT OPERATORS 67
5.9.9.5.1.7 CONCATENATION OPERATOR 67
 5.9.9.5.2 OPERATOR PRECEDENCE 68
5.9.9.5.3 PROCEDURAL BLOCKS 68
6 6 SIMULATION RESULTS 70-74
6.1 BLOCK DIAGRAM 70
6.2 RTL SCHEMATIC DIAGRAM 70
6.3 TECHNOLOGY SCHEMATIC 71
6.4 DESIGN SUMMARY 72
6.5 SIMULATION OUTPUT WAVEFORM 72
6.5.1 SUB MODULE WAVE FORMS 73
6.5.1.1 ENCODING 73
6.5.1.2 ENCODING//DECODING 74
7 7 CONCLUSION AND FUTURE SCOPE 75
8 8 REFERENCES 76
APPENDIX
A.SOURCE CODE
B.JOURNAL PAPER& CERTIFICATE
 A. SOURCE CODE
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module Multiple_bit_upset(clk,rst,wrrd,address,error,din,d1,dout
);

input [31:0]din;
input clk,rst,wrrd;
input [3:0]address;
input [7:0]error;

output reg [31:0]dout;

output [31:0]d1; //memory output

wire [31:0]d; // storage or memory data

wire [19:0]h,hd; //horizontal bits
wire [15:0]v,vd,s; // vertical bits and syndrome bits
wire [4:0]h0h4,h5h9,h10h14,h15h19;

encoding inst(din,h,v); // encoding

//assign dm = din; //memory

sram instsram(clk,rst,wrrd,address,din,error,d1);

//assign d1 = dm + 937; //output

encoding inst1(d1,hd,vd); //decoding

decoding inst2(v,vd,s);
 detecting inst3(h,hd,h0h4,h5h9,h10h14,h15h19);

correcting inst4(clk,rst,d1,s,h0h4,h5h9,h10h14,h15h19,d);

always @ (posedge clk)

begin
if(rst || wrrd)
dout <= 32'd0;

else
dout <= d;

end

endmodule
ENCODING
module encoding(d,h,v);
input [31:0]d;
output [19:0]h;
output [15:0]v;

assign h[4:0] = d[3:0] + d[11:8];

assign h[9:5] = d[7:4] + d[15:12];
assign h[14:10]= d[19:16] +d[27:24];
assign h[19:15]= d[23:20]+d[31:28];

assign v[0] = d[0] ^ d[16];

assign v[1] = d[1] ^ d[17];
assign v[2] = d[2] ^ d[18];
assign v[3] = d[3] ^ d[19];
assign v[4] = d[4] ^ d[20];
 assign v[5] = d[5] ^ d[21];
assign v[6] = d[6] ^ d[22];
assign v[7] = d[7] ^ d[23];
assign v[8] = d[8] ^ d[24];
assign v[9] = d[9] ^ d[25];
assign v[10] = d[10] ^ d[26];
assign v[11] = d[11] ^ d[27];
assign v[12] = d[12] ^ d[28];
assign v[13] = d[13] ^ d[29];
assign v[14] = d[14] ^ d[30];
assign v[15] = d[15] ^ d[31];
endmodule
SRAM
timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module sram(clk,rst,wrrd,address,data_in,error,data_out
);

input clk,rst,wrrd;
input [3:0]address;
input [7:0]error;
input [31:0]data_in;

output reg [31:0]data_out;

reg [31:0]ram[0:15];

always @ (posedge clk)

begin
if(rst)
data_out <= 32'd0;

else
begin
 if(wrrd)
ram[address] <= data_in;

else
data_out <= ram[address] + error;

end

end

endmodule
ENCODING
module encoding(d,h,v);

input [31:0]d;
output [19:0]h;
output [15:0]v;

assign h[4:0] = d[3:0] + d[11:8];

assign h[9:5] = d[7:4] + d[15:12];
assign h[14:10]= d[19:16] +d[27:24];
assign h[19:15]= d[23:20]+d[31:28];

assign v[0] = d[0] ^ d[16];

assign v[1] = d[1] ^ d[17];
assign v[2] = d[2] ^ d[18];
assign v[3] = d[3] ^ d[19];
assign v[4] = d[4] ^ d[20];
assign v[5] = d[5] ^ d[21];
assign v[6] = d[6] ^ d[22];
assign v[7] = d[7] ^ d[23];
assign v[8] = d[8] ^ d[24];
 assign v[9] = d[9] ^ d[25];
assign v[10] = d[10] ^ d[26];
assign v[11] = d[11] ^ d[27];
assign v[12] = d[12] ^ d[28];
assign v[13] = d[13] ^ d[29];
assign v[14] = d[14] ^ d[30];
assign v[15] = d[15] ^ d[31];
endmodule
DECODING
module decoding(v,vd,s);

input [15:0]v,vd;
output [15:0]s;

assign s[0] = v[0] ^ vd[0];

assign s[1] = v[1] ^ vd[1];
assign s[2] = v[2] ^ vd[2];
assign s[3] = v[3] ^ vd[3];
assign s[4] = v[4] ^ vd[4];
assign s[5] = v[5] ^ vd[5];
assign s[6] = v[6] ^ vd[6];
assign s[7] = v[7] ^ vd[7];
assign s[8] = v[8] ^ vd[8];
assign s[9] = v[9] ^ vd[9];
assign s[10] = v[10] ^ vd[10];
assign s[11] = v[11] ^ vd[11];
assign s[12] = v[12] ^ vd[12];
assign s[13] = v[13] ^ vd[13];
assign s[14] = v[14] ^ vd[14];
assign s[15] = v[15] ^ vd[15];
endmodule
DETECTING
module detecting(h,hd,h0h4,h5h9,h10h14,h15h19);

input [19:0]h,hd;
output [4:0]h0h4,h5h9,h10h14,h15h19;

assign h0h4 = hd[4:0] - h[4:0];

assign h5h9 = hd[9:5] - h[9:5];
assign h10h14 = hd[14:10] - h[14:10];
assign h15h19 = hd[19:15] - h[19:15];
endmodule
CORRECTING
module correcting(clk,rst,d1,s,h0h4,h5h9,h10h14,h15h19,d);

input clk,rst;
input [31:0]d1;
input [15:0]s;
input [4:0]h0h4,h5h9,h10h14,h15h19;

output [31:0]d;

correct inst5(clk,rst,h0h4,s[3:0],s[11:8],d1[3:0],d1[11:8],d[3:0],d[11:8]);
correct inst6(clk,rst,h5h9,s[7:4],s[15:12],d1[7:4],d1[15:12],d[7:4],d[15:12]);
correct
inst7(clk,rst,h10h14,s[3:0],s[11:8],d1[19:16],d1[27:24],d[19:16],d[27:24]);
correct
inst8(clk,rst,h15h19,s[7:4],s[15:12],d1[23:20],d1[31:28],d[23:20],d[31:28]);

endmodule