3.

BOUNDARY SCAN
JOINT TEST ACTION GROUP (JTAG):
JTAG is an industry standard for verifying designs and testing PCB after manufacture. The term
JTAG refers to the interface or test access port used for communication. It includes TCK, TDI,
TDO, TMS, TRST connections. For some applications this interface may be used to interrogate or
communicate with internal instruments within the core of the chip.
BOUNDARY SCAN:
It is an integrated method for testing interconnections (wire lines) on PCB or sub blocks
inside an integrated circuit that are implemented at IC level.
It is also widely used as a debugging method to watch integrated circuit pin states, measure
voltage or analyze sub blocks inside an integrated circuit.
Boundary Scan Methods:
For testing interconnects –PCBs used as a debugging method to watch integrated circuit pin
states, measure voltage, or analyze sub-blocks inside an integrated circuit. Boundary scan is a
family of test methodologies aiming at resolving many test problems.
 From chip level to system level,
 Logic cores to interconnects between cores
 Digital circuits to analog or mixed-mode circuits.

IEEE standards of JTAG:

Boundary Scan Architecture:

The boundary-scan test architecture provides a means to test interconnects between integrated
circuits on a board without using physical test probes. It adds a boundary-scan cell that includes a
multiplexer and latches, to each pin on the device. Figure illustrates the main elements of a
universal boundary-scan device. The Figure shows the following elements:
• Test Access Port (TAP) with a set of four dedicated test pins: Test Data In (TDI), Test
Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) and one optional test pin Test Reset
(TRST*).
 • A boundary-scan cell on each device primary input and primary output pin, connected
internally to form a serial boundary-scan register (Boundary Scan).
• A TAP controller with inputs TCK, TMS, and TRST*.
• An n-bit (n >= 2) instruction register holding the current instruction.
• A 1-bit Bypass registers (Bypass).
• An optional 32-bit Identification register capable of being loaded with a permanent device
identification code.

The test access ports (TAP), which define the bus protocol of boundary scan, are the additional
I/O pins needed for each chip employing Std.1149.1a. The TAP controller is a 16-state final state
machine that controls each step of the operations of boundary scan. Each instruction to be carried
out by the boundary scan architecture is stored in the Instruction Register. The various control
signals associated with the instruction are then provided by a decoder. Several Test Data Registers
are used to stored test data or some system related information such as the chip ID, company name,
etc.
TAP Controller Signals:
Test Clock Input (TCK) -- Clock for test logic
Can run at different rate from system clock
Test Mode Select (TMS) -- Switches system from functional to test mode
Test Data Input (TDI) -- Accepts serial test data and instructions -- used to shift in vectors or one of
many test instructions
Test Data Output (TDO) -- Serially shifts out test results captured in boundary scan chain (or
device ID or other internal registers)
Test Reset (TRST) -- Optional asynchronous TAP controller reset
Boundary Scan Instructions:
The IEEE 1149.1 standard defines a set of instructions that must be available for a device to be
considered compliant. These instructions are:

 BYPASS – this instruction causes the TDI and TDO lines to be connected via a single-bit
pass-through register (the BYPASS register). This instruction allows the testing of other devices
in the JTAG chain without any unnecessary overhead.
 EXTEST – this instruction causes the TDI and TDO to be connected to the Boundary
Scan Register (BSR). The device’s pin states are sampled with the ‘capture dr’ JTAG state and
new values are shifted into the BSR with the ‘shift dr’ state; these values are then applied to the
pins of the device using the ‘update dr’ state.
 SAMPLE/PRELOAD – this instruction causes the TDI and TDO to be connected to the
BSR. However, the device is left in its normal functional mode. During this instruction, the BSR
can be accessed by a data scan operation to take a sample of the functional data entering and
leaving the device. The instruction is also used to preload test data into the BSR prior to loading
an EXTEST instruction.
Other commonly available instructions include:

 IDCODE – this instruction causes the TDI and TDO to be connected to the IDCODE
register.
 INTEST – this instruction causes the TDI and TDO lines to be connected to the
Boundary Scan Register (BSR). While the EXTEST instruction allows the user to set and read
pin states, the INTEST instruction relates to the core-logic signals of a device.

Boundary Scan Cell:

The IEEE Std. 1149.1a specifies the design of four test data registers as shown in Figure. Two
mandatory test data registers, the bypass and the boundary-scan resisters, must be included in any
boundary scan architecture. The boundary scan register, though may be a little confusing by its
name, refers to the collection of the boundary scan cells. The other registers, such as the device
identification register and the design-specific test data registers, can be added optionally.
The cell has four modes of operation: normal, update, capture, and serial shift. The memory
elements are two D type flip-flops with front-end and back-end multiplexing of data. It is important
to note that the circuit shown in Figure is only an example of how the requirement defined in the
Standard could be realized. The IEEE 1149.1 Standard does not mandate the design of the circuit,
only its functional specification. The four modes of operation are as follows:
1) During normal mode also called serial mode, Data In is passed straight through to Data Out.
2) During update mode, the content of the Update Hold cell is passed through to Data Out. Signal
values already present in the output scan cells to be passed out through the device output pins.
Signal values already present in the input scan cells will be passed into the internal logic.
3) During capture mode, the Data In signal is routed to the input Capture Scan cell and the value
is captured by the next Clock DR. Clock DR is a derivative of TCK. Signal values on device input
pins to be loaded into input cells, and signal values passing from the internal logic to device output
pins to be loaded into output cells
4) During shift mode, the Scan Out of one Capture Scan cell is passed to the Scan In of the next
Capture Scan cell via a hard-wired path. The Test Clock, TCK, is fed in via yet another dedicated
device input pin and the various modes of operation are controlled by a dedicated Test Mode Select
(TMS) serial control signal.
Note that both capture and shift operations do not interfere with the normal passing of data
from the parallel-in terminal to the parallel-out terminal. This allows on the fly capture of
operational values and the shifting out of these values for inspection without interference. This
application of the boundary-scan register has tremendous potential for real-time monitoring of the
operational status of a system — a sort of electronic camera taking snapshots — and is one reason
why TCK is kept separate from any system clocks.
Operation Modes:
S.No Mode Description

1 Normal Mode=0
IN=OUT

2 Scan Shift DR=1 clock DR,

TDI à…….àSINàSOUT….TDO

3 capture Shift DR=0, clock DR,

INàQA output driven by IN or QB

4 Update Mode=1,update DR
QAàout.

EXTEST:
It tests the interconnection between the chips.
Test the internal logic of the chip
TAP Controller:

The operation of the test interface is controlled by the Test Access Port (TAP) controller. This is a
16-state finite state-machine whose state transitions are controller by the TMS signal.
TAP Controller State Diagram:
A transition between the states only occurs on the rising edge of TCK, and each state has a different
name. 

The two vertical columns with seven states each represent the Instruction Path and the Data Path.

The data registers operate in the states whose names end with "DR" and the instruction register
operates in the states whose names end in "IR". The states are otherwise identical.

The operation of each state is described below.

Test-Logic-Reset

All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP
controller state machine is designed so that, no matter what the initial state of the controller is, the
Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times. This is
why the Test Reset (TRST) pin is optional.

Run-Test-Idle

In this controller state, the test logic in the IC is active only if certain instructions are present. For
example, if an instruction activates the self test, then it is executed when the controller enters this
state. The test logic in the IC is idle otherwise.

Select-DR-Scan

This controller state controls whether to enter the Data Path or the Select-IR-Scan state.

Select-IR-Scan

This controller state controls whether or not to enter the Instruction Path. The Controller can return
to the Test-Logic-Reset state otherwise.

Capture-IR

In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of
fixed values on the rising edge of TCK. The last two significant bits must always be "01".
Shift-IR

In this controller state, the instruction register gets connected between TDI and TDO, and the
captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is
also shifted in to the instruction register.

Exit1-IR

This controller state controls whether to enter the Pause-IR state or Update-IR state.

Pause-IR

This state allows the shifting of the instruction register to be temporarily halted.

Exit2-DR

This controller state controls whether to enter either the Shift-IR state or Update-IR state.

Update-IR

In this controller state, the instruction in the instruction register is latched to the latch bank of the
Instruction Register on every falling edge of TCK. This instruction becomes the current instruction
once it is latched.

Capture-DR

In this controller state, the data is parallel-loaded into the data registers selected by the current
instruction on the rising edge of TCK.

Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR and Update-DR

These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR
states in the Instruction path.

Bypass and Identification Registers:

It is a 1-bit register, selected by the Bypass instruction and provides a basic serial-shift function.
It is a 1-bit register, selected by the Bypass instruction and provides a basic serial-shift function.
There is no parallel output (which means that the Update DR control has no effect on the register),
but there is a defined effect with the Capture DR control — the register captures a hard-wired value
of logic 0.
Instruction Register:

Each instruction to be carried out by the boundary scan architecture is stored in the Instruction
Register. An Instruction register has a shift scan section that can be connected between TDI and
TDO, and a hold section that holds the current instruction. There may be some decoding logic
beyond the hold section depending on the width of the register and the number of different
instructions. The control signals to the Instruction register originate from the TAP controller and
either causes a shift-in/shift-out through the Instruction register shift section, or cause the contents
of the shift section to be passed across to the hold section (parallel Update operation). It is also
possible to load (Capture) internal hard-wired values into the shift section of the Instruction register.
The Instruction register must be at least two-bits long to allow coding of the four mandatory
instructions — Extest, Bypass, Sample, Preload — but the maximum length of the Instruction
register is not defined. In capture mode, the two least significant bits must capture a 01 pattern.
(Note: by convention, the least-significant bit of any register connected between the device TDI
and TDO pins, is always the bit closest to TDO.) The values captured into higher-order bits of the
Instruction register are not defined in the Standard. One possible use of these higher-order bits is to
capture an informal identification code if the optional 32-bit Identification register is not
implemented. In practice, the only mandated bits for the Instruction register capture are the 01
pattern in the two least-significant bits.
Instruction Set:
The IEEE 1149.1 Standard describes four mandatory instructions: Extest, Bypass, Sample, and
Preload, and six optional instructions: Intest, Idcode, Usercode, Runbist, Clamp and HighZ.
Whenever a register is selected to become active between TDI and TDO, it is always possible to
perform three operations on the register: parallel Capture followed by serial Shift followed by
parallel Update. The order of these operations is fixed by the state-sequencing design of the TAP
controller. For some target Data registers, some of these operations will be effectively null
operations, no ops.

EXTEST:
This instruction is used to test interconnect between two chips. The code for Extest used to be
defined to be the all-0s code. The EXTEST instruction places an IEEE 1149.1 compliant device into
an external boundary test mode and selects the boundary scan register to be connected between TDI
and TDO. During this instruction, the boundary scan cells associated with outputs are preloaded
with test patterns to test downstream devices. The input boundary cells are set up to capture the
input data for later analysis.
BYPASS:
A device's boundary scan chain can be skipped using the BYPASS instruction, allowing the data
to pass through the bypass register. The Bypass instruction must be assigned an all-1s code and
when executed, causes the Bypass register to be placed between the TDI and TDO pins. This allows
efficient testing of a selected device without incurring the overhead of traversing through other
devices. The BYPASS instruction allows an IEEE 1149.1 compliant device to remain in a functional
mode and selects the bypass register to be connected between the TDI and TDO pins. The BYPASS
instruction allows serial data to be transferred through a device from the TDI pin to the TDO pin
without affecting the operation of the device.
SAMPLE/PRELOAD:
The Sample and Preload instructions, and their predecessor the Sample/Preload instruction,
selects the Boundary-Scan register when executed. The instruction sets up the boundary-scan cells
either to sample (capture) values or to preload known values into the boundary-scan cells prior to
some follow-on operation. During this instruction, the boundary scan register can be accessed via a
data scan operation, to take a sample of the functional data entering and leaving the device. This
instruction is also used to preload test data into the boundary-scan register prior to loading an
EXTEST instruction.

INTEST:
With this command the boundary scan register (BSR) is connected between the TDI and the
TDO signals. The chip's internal core-logic signals are sampled and captured by the BSR cells at the
entry to the "Capture DR" state as shown in TAP state transition diagram. The contents of the BSR
register are shifted out via the TDO line at exits from the "Shift DR" state. As the contents of the
BSR (the captured data) are shifted out, new data are sifted in at the entries to the "Shift DR" state.
The new contents of the BSR are applied to the chip's core-logic signals during the "Update DR"
state.

Benefits of Boundary Scan:

 Lower test generation cost.
 Reduced test time
 Reduced time to market
 Simpler and less costly testers
 Compatibility with tester interfaces
 High-density packaging devices accommodation

Disadvantages of Boundary Scan:

 Internal scan design cannot have multiple chains
 Cannot test at system clock speed.