FPGA Practice Set for computer Sc.

Students RTU VIII Sem

1. What is the defining difference between microprocessor/DSP systems and other
digital systems?
The digital system follows a programmed sequence of instructions that the
designer specified.
The microprocessor/DSP is faster.

The microprocessor follows a programmed sequence of instructions that the

designer specified.
The digital system is faster.

2. Why have PLDs taken over so much of the market?

One PLD does the work of many ICs.

The PLDs are cheaper.

Less power is required.

All the above

3. Which is a major digital system category?

Standard logic devices

ASICs

Microprocessor/DSP devices

All the above

4. What is the major downfall of microprocessor/DSP systems?

Too much flexibility

Speed—they are too fast

FPGA Practice Set for computer Sc. Students RTU VIII Sem
Not enough flexibility

Speed—they are too slow

5. ASIC stands for:

application speedy integrated circuit.

advanced standard integrated circuit.

advanced speed integrated circuit.

application specific integrated circuit.

6. MPGA stands for:

mass produced gated array.

memory programmed ROM.

mask programmed ROM.

Morgan-Phillips gated array.

7. When did the first PLD appear?

More than 10 years ago

More than 30 years ago

More than 40 years ago

More than 20 years ago

8. What is an OTP device?

Optical transporting port

FPGA Practice Set for computer Sc. Students RTU VIII Sem
Octal transmitting pixel

One-time programmable

Operational topical portable

9. What programmable technology is used in FPGA devices?

SRAM

FLASH

Antifuse

All the above

10. What does a dot mean when placed on a PLD circuit diagram?

A point that is programmable

An intersection of logic blocks

An input or output point

A point that cannot change

11. A PROM is one of many different architectural designs of what type of device?

HPLD

SPLD

PLD

QPLD

12. Which is not a type of PLD?

FPGA Practice Set for computer Sc. Students RTU VIII Sem
FPGA

SPLD

HPLD

CPLD

13. FPLA is:

a nonmemory programmable device.

a programmable AND array.

a programmable OR array.

All the above

14. A PAL16L8 has:

8 inputs and 8 outputs.

16 inputs and 16 outputs.

16 inputs and 8 outputs.

10 inputs and 8 outputs.

15. The GAL16V8 has:

16 dedicated inputs.

8 special function pins.

8 pins that are used as inputs or outputs.

All the above

16. Now many times can a GAL be erased and reprogrammed?

FPGA Practice Set for computer Sc. Students RTU VIII Sem

Over 10,000

At least 100

At least 1000

17. What gives a GAL its flexibility?

Its programmable OLMCs

Its speed

Its large size logic arrays

Its reprogrammable EPROM

18. Which is not a part of a GAL16V8's OLMC?

TSMUX

FMUX

OMUX

PSMUX

19. In an OLMC, where does the FMUX signal go?

PAL

D flip-flop

OMUX

Matrix
FPGA Practice Set for computer Sc. Students RTU VIII Sem
20. Which is a mode of operation of the GAL16V8?

Simple mode

Complex Mode

Registered mode

All the above

21. What is the input/output pin configuration of the GAL22V10?

2 special purpose pins

All the above

10 output pins and 12 input pins

8 pins that are either inputs or outputs

22. What can the ispGAL22V10 do that the GAL16V8 can not?

It has an extra large array.

It is in-system programmable.

It has twice the special function pins.

All the above

23. What is an EPM7128S?

An Altera UP2

A BSR PL DT-2

A DeVry eSOC

An Altera MAX7000S CPLD

FPGA Practice Set for computer Sc. Students RTU VIII Sem
24. How many macrocells are in a MAX700S LAB?

32

16

64

25. What is the status of a tristate output buffer on a MAX7000S family device?

It is permanently enabled or disabled.

It is controlled by one of the two global output enable pins.

It is controlled by other inputs or functions generated by other macrocells.

All the above

26. How many product terms can a MAX+Plus II compiler borrow from adjacent
macrocells in the same LAB?
20

10

27. What does the Altera FLEX10K PLD use in place of AND and OR arrays?

SRAM-based memory

HPLD architecture

Look-up tables

Nothing, it uses AND and OR arrays.

28. How many combinations are handled in a LUT?

16
FPGA Practice Set for computer Sc. Students RTU VIII Sem
32

29. In a FLEX10K, what two outputs will the LE produce?

Hi-Z and ON

ON and OFF

The LAB and the fast track

Hi-Z and OFF

30. How many pins are in an EDF10K70 package?

532

140

How many pins are in an EDF10K70 package?

240

31. The inputs in the PLD is given through:

o NAND gates
o OR gates
o NOR gates
o AND gates

32. PAL refers to

o Programmable Array Loaded

o Programmable Logic Array
o Programmable Array Logic
o Programmable AND Logic

33. Outputs of the AND gate in PLD is known as

o Input lines
o Output lines
FPGA Practice Set for computer Sc. Students RTU VIII Sem
o Strobe lines
o Control lines

34. PLA contains

o AND and OR arrays

o NAND and OR arrays
o NOT and AND arrays
o NOR and OR arrays

35. PLA is used to implement

o A complex sequential circuit

o A simple sequential circuit
o A complex combinational circuit
o A simple combinational circuit

36. A PLA is similar to a ROM in concept except that

o It hasn’t capability to read only

o It hasn’t capability to read or write operation
o It doesn’t provide full decoding to the variables
o It hasn’t capability to write only

37. For programmable logic functions, which type of PLD should be used?

o PLA
o PAL
o CPLD
o SLD

38. The complex programmable logic device contains several PLD blocks and

o A language compiler
o AND/OR arrays
o Global interconnection matrix
o Field-programmable switches

39. Which type of device FPGA are?

o SLD
o SROM
o EPROM
o PLD

40. The difference between a PAL & a PLA is

o PALs and PLAs are the same thing

FPGA Practice Set for computer Sc. Students RTU VIII Sem
o The PLA has a programmable OR plane and a programmable AND plane, while
the PAL only has a programmable AND plane
o The PAL has a programmable OR plane and a programmable AND plane, while
the PLA only has a programmable AND plane
o The PAL has more possible product terms than the PLA

41. If a PAL has been programmed once

o Its logic capacity is lost

o Its outputs are only active HIGH
o Its outputs are only active LOW
o It cannot be reprogrammed

42. The FPGA refers to

o First programmable Gate Array

o Field Programmable Gate Array
o First Program Gate Array
o Field Program Gate Array

43. The full form of VLSI is

o Very Long Single Integration

o Very Least Scale Integration
o Very Large Scale Integration
o Very Long Scale Integration

44. In FPGA, vertical and horizontal directions are separated by

o A line
o A channel
o A strobe
o A flip-flop

45. Applications of PLAs are

o Registered PALs
o Configurable PALs
o PAL programming
o All of the Mentioned

46. If a variable is not assigned in all possible executions of an always statement then:

o A don’t care is inferred

o A latch is inferred
FPGA Practice Set for computer Sc. Students RTU VIII Sem
o The variable is set to 0
o The synthesis process will fail

47. In which of the situations listed below would a designer use an FPGA?

o The system should be as power efficient.

o The system should be fast.
o Only few copies of the system will be produced and we have a limited budget to
spend on all the components.
o All of the above

48. Designing an 8-state FSM requires:

o At least 8 Flip-Flops
o At most 3 Flip-Flops
o 3 Flip-Flops
o 8 Flip-Flops

49. Carry select adder is faster than carry-look ahead because:

o Carry select adder computes two high order sums in parallel

o Carry select adder computes low order sums in parallel
o Carry select adder computes two high order overflows in series
o Non of the above

50. An 8:1 multiplexer can implement any function of

o Three variables
o Four variables
o Five variables
o Non of the above