ECR – 209: Microprocessors and Interfacing

The Intel 8086 Microprocessor

 8086 Functional blocks
Microprocessor
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 8086 Overview
Microprocessor
20-bit address to access memory  can
address up to 220 = 1 megabytes of
First 16- bit processor released by memory space.
INTEL in the year 1978.
16 bit words of the addressable memory
The term 16 bit means that its ALU, space is organized in to two banks of 512
internal registers and most of its kb each; Even (or lower) bank and Odd
instructions are designed to work (or higher) bank.
with 16 bit binary word. Low Byte High Byte
07 26

Originally based on HMOS (High- Address 00520 Address 00521

performance n-channel Metal Oxide
Semiconductor) technology. The 16 bit word stored at the even
address 00520 is 2607. For, word
Contains approximately 29, 000 addresses the low-order address is used
transistors, 40 pin DIP (Dual In-line to specify the whole 16 bit address.
Package), 5V supply
If the first byte of a word is at an even
address, the read operation is done in
one operation. Otherwise two.

8086 has a 16 bit data bus so it can read

data from or write data to memory and
ports either 16 or 8 bits at a time.
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8086 Microprocessor – Pins and Signals
 8086 Pins and Signals Common signals
Microprocessor

AD0-AD15 (Bidirectional)
Address/Data bus

These are 16 address/data bus.

When AD lines are used to transmit
memory address the symbol A is used
instead of AD, for example A0-A15.
When data are transmitted over AD lines
the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.
ALE=1, carries address
ALE=0 carries data.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

the 4 address/status buses.

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 8086 Pins and Signals Common signals
Microprocessor

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

BHE stands for Bus High Enable. It is
available at pin 34 and used to indicate
the transfer of data using data bus D8-
D15. This signal is low during the first
clock cycle, thereafter it is active.

MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in. In minimum
mode, control signal. Max mode
multiprocessing occurs to facilitate the
system .

RD (Read) (Active Low)

The signal is used for read operation.

It is active when low.

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 8086 Pins and Signals Common signals
Microprocessor

TEST

TEST pin is examined by the "WAIT"

instruction. If the TEST pin is Low, the
execution continues. Otherwise the
processor waits in an "idle" state.

READY
It is available at pin 32. It is an
acknowledgement signal from I/O
devices that data is transferred. It is an
active high signal. When it is high, it
indicates that the device is ready to
transfer data. When it is low, it indicates
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wait state.
 8086 Pins and Signals Common signals
Microprocessor

RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input which is used to

request a hardware interrupt. If any
interrupt request is pending, the
processor enters the interrupt
acknowledge cycle.

This signal is active high and internally

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synchronized.
 8086 Pins and Signals Min/ Max Pins
Microprocessor

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor does not associate with any
co-processors and cannot be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

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 8086 Pins and Signals Minimum mode signals
Microprocessor

Pins 24 -31
For minimum mode operation, the MN/ MX is tied
low

DT/R (Data Transmit/ Receive) It is available at pin 27. It

decides the direction of data flow through the transreceiver.
When it is high, data is transmitted out and vice-a-versa.

(Data Enable) Output signal from the processor

used as output enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines.

M/IO Used to differentiate memory access and I/O access.

For memory reference instructions, it is high. For IN and
OUT instructions, it is low.

Write control signal; asserted low whenever processor

𝐖𝐑
writes data to memory of I/O port

(Interrupt Acknowledge) When the interrupt request

INTA
is accepted by the processor the output is
low on this line.

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 8086 Pins and Signals Minimum mode signals
Microprocessor

HOLD This signal indicates to the processor that external

devices are requesting to access the address/data
buses. It is available at pin 31

HLDA (Hold Acknowledge) It stands for Hold

Acknowledgement signal and is available at pin
30. This signal acknowledges the HOLD signal.

The acknowledge is asserted high, when the

processor accepts HOLD.

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 8086 Pins and Signals Maximum mode signals
Microprocessor

During maximum mode operation,

Pins 24 -31 are reassigned

Status signals; used by the 8086 external bus

𝑺 𝟎, 𝑺 𝟏, 𝑺 𝟐
controller to generate bus timing and control signals. These are
decoded as shown.

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 8086 Pins and Signals Maximum mode signals
Microprocessor

(Queue Status) The processor provides the status

𝑸𝑺𝟎, 𝑸𝑺𝟏
for the instruction queue.

The queue status can be used by external device to

track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

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 8086 Pins and Signals Maximum mode signals
Microprocessor

𝐑𝐐/𝐆𝐓𝟎, (Bus Request/ Bus Grant) These are the

𝐑𝐐/𝐆𝐓𝟏 Request/Grant signals used by the other processors
requesting the CPU to release the system bus. When
the signal is received by CPU, then it sends
acknowledgment
These pins are bidirectional.
The request on 𝐆𝐓𝟎 will have higher priority than 𝐆𝐓𝟏

LOCK When this signal is active, it indicates to the other

processors not to ask the CPU to leave the system bus.
It is activated using the LOCK prefix on any
instruction and is available at pin 29.

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8086 Microprocessor – Architecture
 8086 Architecture
Microprocessor

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Dedicated
De Adder to generate
20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 18

 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Segment
Registers

8086’s 1-megabyte The 8086 can directly Programs obtain access

memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.

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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Code Segment Register

Registers
16-bit

CS contains the base or start of the current code segment;

IP contains the distance or offset from this address to the
next instruction byte to be fetched.

BIU computes the 20-bit physical address by logically

shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.

That is, all instructions of a program are relative to the

contents of the CS register multiplied by 16 and then offset
is added provided by the IP.

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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Data Segment Register

Registers

16-bit

Points to the current data segment; operands for most

instructions are fetched from this segment.

The 16-bit contents of the Source Index (SI) are used as

offset for computing the 20-bit physical address.

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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Stack Segment Register

Registers
16-bit

Points to the current stack.

The 20-bit physical stack address is calculated from the

Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions.

In based addressing mode, the 20-bit physical stack

address is calculated from the Stack segment (SS) and the
Base Pointer (BP).

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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Extra Segment Register

Registers

16-bit

Points to the extra segment in which data (in excess of

64K pointed to by the DS) is stored.

String instructions use the ES and DI to determine the 20-

bit physical address for the destination.

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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed within

the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution

of the next instruction takes place.

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 8086 Architecture Bus Interface Unit (BIU)
Microprocessor

Instruction queue

A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.

This is done in order to

speed up the execution
by overlapping
instruction fetch with
execution.

This mechanism is known

as pipelining.

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 8086 Architecture Execution Unit (EU)
Microprocessor

EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 26
DX can be used as DH and DL
 8086 Architecture Execution Unit (EU)
Microprocessor

EU Accumulator Register (AX)

Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

Multiplication and Division instructions also use the AX or

AL.

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 8086 Architecture Execution Unit (EU)
Microprocessor

EU Base Register (BX)

Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

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 8086 Architecture Execution Unit (EU)
Microprocessor

EU Counter Register (CX)

Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

When combined, CL register contains the low order byte of

the word, and CH contains the high-order byte.

Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

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 8086 Architecture Execution Unit (EU)
Microprocessor

EU Data Register (DX)

Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.

When combined, DL register contains the low order byte of

the word, and DH contains the high-order byte.

Used to hold the high 16-bit result (data) in 16 X 16

multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.

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 8086 Architecture Execution Unit (EU)
Microprocessor

EU Stack Pointer (SP) and Base Pointer (BP)

Registers
SP and BP are used to access data in the stack segment.

SP is used as an offset from the current SS during

execution of instructions that involve the stack segment in
the external memory.

SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

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 8086 Architecture Execution Unit (EU)
Microprocessor

EU Source Index (SI) and Destination Index (DI)

Registers
Used in indexed addressing.

Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.

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 8086 Architecture Execution Unit (EU)
Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of the This flag is set to 1, if the lower
result of any computation computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF SF ZF AF PF CF

.
Over flow Flag
This flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit
sign operations, then the overflow will be set.

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