Faults

A failure is said to have occurred in a logic circuit or system if it deviates from its specified
behaviour. A fault, on the other hand, refers to a physical defect in a circuit. For example, a
short between two signal lines in the circuit or a break in a signal line is a physical defect. An
error is usually the manifestation of a fault in the circuit; thus, a fault may change the value of
a signal in a circuit from 0 (correct) to 1 (erroneous) or vice versa. However, a fault does not
always cause an error; in that case, the fault is considered to be latent.

A fault is characterized by its nature, value, extent, and duration. The nature of a fault can be
classified as logical or nonlogical. A logical fault causes the logic value at a point in a circuit
to become opposite to the specified value. Nonlogical faults include the rest of the faults such
as the malfunction of the clock signal, power failure, etc. The value of a logical fault at a
point in the circuit indicates whether the fault creates fixed or varying erroneous logical values.
The extent of a fault specifies whether the effect of the fault is localized or distributed. A
local fault affects only a single variable, whereas a distributed fault affects more than one. A
logical fault, for example, is a local fault, whereas the malfunction of the clock is a distributed
fault. The duration of a fault refers to whether the fault is permanent or temporary.

Types of Fault: 1) Stuck-At and 2) Bridging

Stuck-At Fault
The most common model used for logical faults is the single stuck-at fault. It assumes that a
fault in a logic gate results in one of its inputs or output is fixed at either a logic 0 (stuck-
at-0) or at logic 1 (stuck-at-1). Stuck-at-0 and stuck-at-l faults are often abbreviated to s-a-0
and s-a-1, respectively.
 Fig. 1

Let us assume that in Figure given below (Fig. 2), the A input of the NAND gate is s-a-1.
A B Zgood Zfaulty
0 0 1 1
0 1 1 0
1 0 1 1
1 1 0 0

Fig. 2
The NAND gate perceives the A input as a logic 1 irrespective of the logic value placed on the
input. For example, the output of the NAND gate is 0 for the input pattern A=0 and B=1, when
input A is s-a-1 in. In the absence of the fault, the output will be 1. Thus, AB=01 can be
considered as the test for the A input s-a-l, since there is a difference between the output of the
fault-free and faulty gate. The single stuck-at fault model is often referred to as the classical
fault model and offers a good representation for the most common types of defects [e.g., shorts
and opens in the CMOS technology] Figure given below (Fig. 3) illustrates the CMOS
realization of the two-input NAND:

Fig. 3
The number 1 in the figure-3 indicates an open, whereas the numbers 2 and 3 identify the short
between the output node and the ground and the short between the output node and the VDD,
respectively. A short in a CMOS results if not enough metal is removed by the
photolithography, whereas over-removal of metal results in an open circuit. Fault 1 in Figure
3 will disconnect input A from the gate of transistors T1 and T3. It has been shown that in
such a situation one transistor may conduct and the other remain nonconducting. Thus, the
fault can be represented by a stuck at value of A; if A is s-a-0, T1 will be ON and T3 OFF, and
if A is s-a-l, T1 will be OFF and T3 ON. Fault 2 forces the output node to be shorted to VDD,
that is, the fault can be considered as an s-a-l fault. Similarly, fault 3 forces the output node to
be s-a-0.

The stuck-at model is also used to represent multiple faults in circuits. In a multiple stuck-at
fault, it is assumed that more than one signal line in the circuit are stuck at logic 1 or logic 0;
in other words, a group of stuck-at faults exist in the circuit at the same time. A variation of
the multiple fault is the unidirectional fault. A multiple fault is unidirectional if all of its
constituent faults are either s-a-0 or s-a-l but not both simultaneously. The stuck-at model has
gained wide acceptance in the past mainly because of its relative success with small scale
integration. However, it is not very effective in accounting for all faults in present day very
large scale integrated (VLSI), circuits which mainly uses CMOS technology. Faults in CMOS
circuits do not necessarily produce logical faults that can be described as stuck-at faults.

Example 1
For the circuit shown below, find the test vector to detect α s-a-0 fault.

f good= ((AB)’.(B’C)’)’ = AB+B’C  A=0 B=1 C= don’t care

f faulty = ((AB)’.0)’= 1  A=0 C=0 B= don’t care
F good XOR f faulty =1  B=0 C=0 A= don’t care
(AB+ B’C) XOR 1 = 1
A B C fgood F faulty
(AB+B’C)’ = 1
0 1 0 0 1
(AB)’.(B’C)’ =1
0 1 1 0 1
(A’+B’)(B+C’)=1
0 0 0 0 1
A’B+A’C’+B’C’ = 1 1 0 0 0 1
Example 2
For the circuit shown in Figure, find all test vectors to detect stuck-at- 0 fault.

L_good= (AB+(BC)’).E
L_faulty = E
L_good XOR L_faulty =1
(AB+B’+C’).E XOR E =1
=(AB+B’+C’).E . E’ + E. ((AB+B’+C’).E)’=1
=E.(AB+B’+C’)’ = 1
=E.(A+B’+C’)’=1
 E=1 and A+B’+C’ =0
A=0, B=1,C=1,E=1
 Bridging Fault

A bridging fault is said to have occurred when two or more signal lines in a circuit are
accidentally connected together. They can be modelled as AND bridging fault or OR- bridging
fault.

Bridging faults form an important class of permanent faults that cannot be modeled as stuck-
at faults. A bridging fault is said to have occurred when two or more signal lines in a circuit
are accidentally connected together. Earlier study of bridging faults concentrated only on the
shorting of signal lines in gate-level circuits. It was shown that the shorting of lines resulted
in wired logic at the connection.
Bridging faults at the gate level has been classified into two types: input bridging and feedback
bridging. An input bridging fault corresponds to the shorting of a certain number of primary
input lines. A feedback bridging fault results if there is a short between an output and input
line. A feedback bridging fault may cause a circuit to oscillate, or it may convert it into a
sequential circuit.
Bridging faults in a transistor-level circuit may occur between the terminals of a transistor or
between two or more signal lines. Figure 1.5 shows the CMOS logic realization of the Boolean
function:
Zl = Z2 = AB’ + CD’
A short between two lines, as indicated by the dotted line in the diagram will change the
function of the circuit.

Example 3
For the circuit shown below, find the test vector to detect OR bridging fault between lines d
and e.
To determine the test vector,
F good XOR F faulty =1 (ab+bc) xor abc =1
F_good= ((ab)’.(bc)’)’ = (ab+bc).(abc)’ + abc.(ab+bc)’ =1
= ab+bc =(ab+bc)(a’+b’+c’)+abc(ab)’.(bc)’ =1
F_faulty = ((ab)’+(bc)’)’ =abc’+a’bc+0 =1
= ab. bc = abc => 110, 011